US20070187767A1 - Semiconductor device including misfet - Google Patents

Semiconductor device including misfet Download PDF

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US20070187767A1
US20070187767A1 US11/673,278 US67327807A US2007187767A1 US 20070187767 A1 US20070187767 A1 US 20070187767A1 US 67327807 A US67327807 A US 67327807A US 2007187767 A1 US2007187767 A1 US 2007187767A1
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layer
source
germanium
semiconductor device
silicon germanium
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Nobuaki Yasutake
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Toshiba Corp
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Toshiba Corp
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Publication of US20070187767A1 publication Critical patent/US20070187767A1/en
Priority to US12/723,251 priority Critical patent/US7880228B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Definitions

  • the present invention relates to a semiconductor device, and more particularly to an MISFET (Metal Insulator Semiconductor Field Effect Transistor)
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • a carrier (hole) mobility in a channel region of a p-channel MOSFET (which will be referred to as a pMOS hereinafter) is slower than a carrier (electron) mobility in a channel region of an n-channel MOSFET (which will be referred to as an nMOS hereinafter), and hence increasing a speed of the pMOS is demanded.
  • a CMOSFET Complementally MOS Field Effect Transistor
  • a semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a source/drain layer formed on both sides of the gate electrode, the source/drain layer containing silicon germanium and having a germanium layer in a surface layer portion; and a germanide layer formed on the germanium layer of the source/drain layer.
  • a semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a first sidewall insulating film formed on a side surface of the gate electrode; a second sidewall insulating film formed on a side surface of the first sidewall insulating film; a first source/drain layer formed below the second sidewall insulating film, the first source/drain layer containing silicon germanium; a second source/drain layer formed in contact with the first source/drain layer on an outer side of the second sidewall insulating film, the second source/drain layer containing silicon germanium and having a germanium layer in a surface layer portion; and a germanide layer formed on the germanium layer of the second source/drain layer.
  • a semiconductor device comprising: a semiconductor substrate; a first silicon germanium layer formed on the semiconductor substrate; a second silicon germanium layer formed on the semiconductor substrate apart from the first silicon germanium layer; a gate insulating film formed on the semiconductor substrate between the first silicon germanium layer and the second silicon germanium layer; a gate electrode formed on the gate insulating film; a first germanium layer formed on the first silicon germanium layer; a first germanide layer formed on the first germanium layer; a second germanium layer formed on the second silicon germanium layer; and a second germanide layer formed on the second germanium layer.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention.
  • FIGS. 2 to 8 are cross-sectional views showing a manufacturing method of a semiconductor device according to Embodiment 1;
  • FIG. 9 is a process cross-sectional view of a semiconductor device according to a modification of Embodiment 1;
  • FIG. 10 is a cross-sectional view showing a semiconductor device according to Embodiment 2 of the present invention.
  • FIGS. 11A, 11B , 11 C, 12 A, 12 B, 12 C, 13 A, and 13 B are cross-sectional views showing a manufacturing method of the semiconductor device according to Embodiment 2;
  • FIG. 14 is a cross-sectional view showing a semiconductor device according to Modification 1 of Embodiment 2 of the present invention.
  • FIG. 15 is a cross-sectional view showing a semiconductor device according to Modification 2 of Embodiment 2 of the present invention.
  • FIG. 16 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 17 is a cross-sectional view showing a semiconductor device according to Modification of Embodiment 3 of the present invention.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to this embodiment that functions as a pMOS of a CMOSFET.
  • an element isolating region 101 is provided in a semiconductor substrate, e.g., a single-crystal silicon semiconductor substrate (which will be referred to as a silicon substrate hereinafter) 100 , and an element forming region 100 a is partitioned by this element isolating region 101 .
  • a gate electrode 104 is formed on the silicon substrate 100 via a gate insulating film 103 .
  • a first sidewall insulating film 105 is formed on a side surface of the gate electrode 104
  • a second sidewall insulating film 106 is formed on a side surface of the first sidewall insulating film 105 .
  • a first source/drain layer 108 as an extension layer in which a p-type impurity ion is implanted is formed on the silicon substrate 100 below the second sidewall insulating film 106 .
  • a silicon germanium layer 109 is formed on the silicon substrate 100 on each of both sides (an outer side) of the second sidewall insulating film 106 , and a germanium layer 110 is formed on the silicon germanium layer 109 . Furthermore, a second source/drain layer in which a p-type impurity ion is implanted is formed on the silicon germanium layer 109 and the germanium layer 110 . When the second source/drain layer contains the silicon germanium in this manner, a compression stress can be given to a channel region to increase a mobility of a carrier.
  • a silicide layer 112 is formed on an upper side of the gate electrode 104
  • a germanide layer 113 is formed on the germanium layer 110 of the second source/drain layer.
  • This germanide layer 113 is formed by forming a high-melting point metal film of, e.g., nickel (Ni), cobalt (Co), titanium (Ti), iridium (Ir), platinum (Pt), or palladium (Pd) on the germanium layer 110 of the second source/drain layer, and then performing a heat treatment to react the germanium layer 110 with the high-melting point metal film.
  • the germanide layer 113 is constituted of a binary compound, e.g., NiGe, CoGe, TiGe, IrGe, PtGe, or Pd 2 Ge without containing Si.
  • a barrier insulating film 114 is formed on the element isolating region 101 , the gate electrode 104 , the sidewall insulating films 105 and 106 , and the germanide layer 113 .
  • An interlayer insulating layer 115 is formed on the barrier insulating film 114 .
  • a wiring layer 116 is formed on the interlayer insulating layer 115 . The wiring layer 116 is electrically connected with the germanide layer 113 via a contact plug 117 .
  • FIGS. 2 to 8 are process cross-sectional views showing a manufacturing method of the semiconductor device according to Embodiment 1. It is to be noted that the element isolating region 101 is not depicted and omitted in FIGS. 2 and 8 .
  • the element isolating region 101 is formed in the silicon substrate 100 .
  • the element isolating region 101 it is possible to use so-called STI (shallow trench isolation) obtained by forming a shallow groove in the silicon substrate 100 by a photo engraving process and filling this groove with an insulating film, e.g., an silicon oxide film (an SiO 2 film) formed by a CVD (Chemical vapor deposition) method.
  • STI shallow trench isolation
  • an insulating film e.g., an silicon oxide film (an SiO 2 film) formed by a CVD (Chemical vapor deposition) method.
  • the gate insulating film 103 having, e.g., an SiO 2 film or a silicon oxynitride film (an SiON film) as a material is formed on the silicon substrate 100 by using the CVD method or the like.
  • An electroconductive material film e.g., a polycrystal silicon film, in which, e.g., boron (B) is added at a high concentration, serving as the gate electrode 104 is deposited on the gate insulating film 103 .
  • an oxide film 118 e.g., an SiO 2 film formed by the CVD method is deposited on the polycrystal silicon film.
  • a gate electrode pattern is processed on the oxide film 118 by lithography and etching, and then the polycrystal silicon film is etched with this oxide film 118 being used as a mask, thereby forming the gate electrode 104 . Additionally, the gate insulating film 103 is etched and removed while avoiding a part below the gate electrode 104 .
  • a silicon nitride film (an SiN film) having a film thickness of, e.g., 10 nm is formed on the silicon substrate 100 and the gate electrode 104 by the CVD method and the like. Further, the silicon nitride film formed on the gate electrode 104 , the silicon substrate 100 , and others is subjected to anisotropic etched to form the first sidewall insulating film 105 on the side surface of the gate electrode 104 as shown in FIG. 4 .
  • the first source layer 108 as the extension layer is formed on the silicon substrate 100 on both sides of the first sidewall insulating film 105 .
  • a p-type impurity ion is implanted into the silicon substrate 100 with the gate electrode 104 and the first sidewall insulating film 105 being used as a mask.
  • boron (B) can be used, for example.
  • a silicon nitride film (an SiN film) or a silicon oxide film (an SiO 2 film) having a film thickness of, e.g., 20 to 30 nm is formed on the silicon substrate 100 , the gate electrode 104 , and the first sidewall insulating film 105 by the CVD method and the like.
  • the silicon nitride film or the silicon oxide film formed on the gate electrode 104 and the silicon substrate 100 is subjected to anisotropic etching.
  • the second sidewall insulating film 106 is formed on the first sidewall insulating film 105 on the side surface of the gate electrode 104 as shown in FIG. 6 .
  • a surface portion of the silicon substrate 100 is etched to be removed with the gate electrode 104 and the second sidewall insulating film 106 being used as a mask, thereby forming a shallow groove 121 for the second source/drain layer serving as a source/drain layer. It is to be noted that the upper surface of the gate electrode 104 is covered with the oxide film 118 at the time of this etching, and hence the gate electrode 104 is not etched.
  • the silicon germanium layer 109 and the germanium layer 110 are sequentially subjected to selective epitaxial growth on the groove 121 .
  • This selective epitaxial growth of the silicon germanium layer 109 can be realized by adding, e.g., approximately 0.4 vol % to 0.5 vol % of hydrogen chloride (HCl) to hydrogen (H 2 ) as a carrier gas and using a mixed gas containing dichlorsilane (SiH 2 Cl 2 ) and monogermane (Ge 4 ) as a raw material at a temperature of, e.g., 650° C. to 750° C.
  • a gas flow rate of GeH 4 with respect to SiH 2 Cl 2 can be set to, e.g., 2 vol % to 5 vol %. Changing this gas flow ratio enables controlling a germanium concentration in the silicon germanium layer 109 to a desired value.
  • a germanium concentration in this silicon germanium layer 109 is determined to fall within a range of, e.g., 10 at % to 30 at % in order to give a compression stress to the channel region and effectively improve a carrier mobility by containing the germanium and also to suppress an influence of occurrence of a crystal defect due to excessively containing the germanium.
  • a thickness of the silicon germanium layer 109 can be changed in dependence on a gate length. When the gate length is, e.g., 70 nm, a thickness of the silicon germanium layer 109 can be set to, e.g., 35 nm to 40 nm. However, this value can be increased to enlarge a compression stress given to the channel region.
  • a gas flow ratio at the time of selective epitaxial growth of the silicon germanium layer 109 i.e., a gas flow rate of GeH 4 with respect to SiH 2 Cl 2 can be greatly increased, thereby subjecting the germanium layer 110 to selective epitaxial growth on the silicon germanium layer 109 .
  • growth is effected in such a manner that a germanium concentration of the silicon germanium layer 109 becomes 10 at % to 30 at %, and growth is performed in such a manner that a germanium concentration of the germanium layer 110 becomes approximately 100 at %.
  • a boron (B) ion or the like is implanted into the silicon germanium layer 109 and the germanium layer 110 with the gate electrode 104 and the second sidewall insulating film 106 being used as a mask.
  • Ion implantation conditions of the second source/drain layer are a higher energy and a higher concentration than those in ion implantation of the first source/drain layer 108 .
  • a junction depth of the second source/drain layer can be formed larger than a junction depth of the first source/drain layer 108 as the extension layer.
  • the second source/drain layer is formed in contact with the first source/drain layer 108 . It is to be noted that the second source/drain layer may be formed to be deeper than the silicon germanium layer 109 .
  • the oxide film 118 on the gate electrode 104 is removed by, e.g., wet etching to expose a surface of the polycrystal silicon layer of the gate electrode 104 .
  • the silicide layer 112 is formed on the gate electrode 104
  • the germanide layer 113 is formed on the second source/drain layer, i.e., the germanium layer 110 .
  • a metal film (not shown) is formed on the gate electrode 104 and the germanium layer 110 by, e.g., sputtering.
  • the second source/drain layer has the germanium layer 110 on an interface between itself and the germanide layer 113 .
  • a metallic material of the metal film it is possible to use a high-melting point metal, e.g., nickel (Ni), cobalt (Co), titanium (Ti), iridium (Ir), platinum (Pt), or palladium (Pd). Thereafter, an unreacted metal film other than the silicide layer 112 and the germanide layer 113 is removed.
  • a high-melting point metal e.g., nickel (Ni), cobalt (Co), titanium (Ti), iridium (Ir), platinum (Pt), or palladium (Pd).
  • the barrier insulating film 114 is deposited on the structure depicted in FIG. 8 .
  • the interlayer insulating layer 115 is deposited on the barrier insulating film 114 and flattened by, e.g., CMP (Chemical Mechanical Polishing).
  • CMP Chemical Mechanical Polishing
  • a contact hole reaching the germanide layer 113 is formed in the interlayer insulating layer 115 , and then the contact hole is filled with an electroconductive material to form the contact plug 117 .
  • the wiring layer 116 connected with the contact plug 117 is formed on the interlayer insulating layer 115 .
  • a process required for a semiconductor device e.g., multilayer wiring is carried out, thus manufacturing the semiconductor device according to this embodiment.
  • the second source/drain layer contains the silicon germanium as a compound of silicon and germanium having a larger atomic radium than silicon, a compression stress can be given to the channel region, and a carrier mobility can be improved.
  • a silicide layer is formed on a source/drain layer using the silicon germanium in order to reduce a resistance of the source/drain layer.
  • a thermally unstable compound is generated.
  • transistor characteristics may be deteriorated in some cases.
  • a surface layer of the source/drain layer containing the silicon germanium is constituted of a silicon layer having a fixed thickness and the silicide layer is formed on this silicon layer along to suppress generation of a compound due to reaction of the silicon germanium and the silicide layer, a contact resistance between the silicon layer and the silicide layer is increased, and hence an improvement in transistor characteristics may possibly become insufficient.
  • the surface layer of the second source/drain layer using the silicon germanium is constituted of the germanium layer 110 having a fixed thickness, and the germanide layer 113 is provided on the germanium layer 110 to prevent reaching the silicon germanium layer 109 .
  • the silicon germanium layer 109 of the second source/drain layer does not directly come into contact with the germanide layer 113 , and a thermally unstable compound is not generated. Therefore, deterioration in transistor characteristics can be avoided.
  • a contact resistance between the germanium layer 110 and the germanide layer 113 is lower than a contact resistance between the silicon layer and the silicide layer, thus effectively suppressing deterioration in transistor characteristics.
  • a compression stress can be given to the channel region, a carrier mobility can be improved, and a resistance of the source/drain layer can be reduced without generating a thermally unstable compound on the source/drain layer. As a result, deterioration in transistor characteristics can be suppressed.
  • the germanium layer 110 is formed on the silicon germanium layer 109 having a predetermined germanium concentration in this embodiment.
  • a silicon germanium layer 109 A whose germanium concentration continuously varies from the surface layer portion toward the deep layer portion may be used, and the germanium layer 110 may be formed on this silicon germanium layer 109 A.
  • the germanium concentration in a lower part of the silicon germanium layer 109 A is set to 10 to 30 at %.
  • the germanium concentration in the interface between the silicon germanium layer 109 A and the germanium layer 110 is set to 100 at %.
  • the germanide layer is formed on the germanium layer in the source/drain layer.
  • a contact resistance between the germanium layer and the germanide layer in this example can be represented by the following Expression (1).
  • ⁇ C is a contact resistance between the germanium layer and the germanide layer
  • N D is an impurity concentration in an interface, i.e., a boron ion concentration in an interface between the germanium layer and the germanide layer.
  • ⁇ B is a height of a Schottky barrier.
  • ⁇ B is reduced by approximately 0.1 eV and becomes 0.33 eV, 0.10 to 0.14 eV, or 0.25 eV. It is to be noted that a germanium concentration of the silicon germanium layer in this example is 15 at %. Therefore, as compared with the conventional technology where the silicide film is formed on the silicon layer or the silicon germanium layer, the contact resistance in the source/drain layer can be reduced in this embodiment where the germanide layer is formed on the germanium layer on the silicon germanium layer.
  • FIG. 10 is a cross-sectional view showing a semiconductor device according to this embodiment that functions as a pMOS of a CMOSFET.
  • an element isolating region 101 is provided in a single-crystal silicon semiconductor substrate (a silicon substrate) 100 , and an n-type well region 102 having an n-type impurity ion is formed in an element forming region 100 partitioned by this element isolating region 101 .
  • a gate insulating film 103 is formed on the n-type well region 102 of the silicon substrate 100 , and a gate electrode 104 is formed on the gate insulating film 103 .
  • a first sidewall insulating film 105 is formed on a side surface of the gate electrode 104 , and a second sidewall insulating film 106 is formed on a side surface of the first sidewall insulating film 105 .
  • a semiconductor layer 107 is formed in the n-type well region 102 below the second sidewall insulating film 106 . Further, a first source/drain layer 108 as an extension layer in which a p-type impurity ion is implanted is formed on this semiconductor layer 107 .
  • the semiconductor layer 107 it is preferable for the semiconductor layer 107 to be a semiconductor layer containing silicon germanium in order to give a compression stress to a channel region and improve a mobility of a carrier.
  • the first source/drain layer 108 to be formed with a so-called elevated structure in which a surface thereof is placed above a surface of the silicon substrate 100 where a channel moves.
  • a silicon germanium layer 109 is formed on the n-type well region 102 on both sides (an outer side) of the second sidewall insulating film 106 .
  • a germanium layer 110 is formed on the silicon germanium layer 109 .
  • a second source/drain layer 111 in which a p-type impurity ion is implanted is formed in this silicon germanium layer 109 and the germanium layer 110 .
  • the second source/drain layer 111 in order to suppress a short channel effect, it is preferable for the second source/drain layer 111 to be formed with the elevated structure in which a surface thereof is formed at a higher position than a height of the surface of the silicon substrate 100 .
  • a silicide layer 112 is formed on the gate electrode 104
  • a germanide layer 113 is formed on the germanium layer 110 of the second source/drain layer 111 .
  • This germanide layer 113 is formed by forming a high-melting point metal film of, e.g., nickel (Ni), cobalt (Co), titanium (Ti), iridium (Ir), platinum (Pt), or palladium (Pd) on the germanium layer 110 of the second source/drain layer 111 , and then carrying out a heat treatment to react the germanium layer 110 of the second source/drain layer 111 with the high-melting point metal film.
  • the germanide layer 113 is constituted of a binary compound, e.g., NiGe, CoGe, TiGe, IrGe, PtGe, or Pd 2 Ge without containing Si.
  • a barrier insulating film 114 is formed on the element isolating region 101 , the gate electrode 104 , the sidewall insulating films 105 and 106 , and the germanide layer 113 .
  • An interlayer insulating layer 115 is formed on the barrier insulating film 114 .
  • a wiring layer 116 is formed on the interlayer insulating layer 115 . The wiring layer 116 is electrically connected with the germanide layer 113 via a contact plug 117 .
  • FIGS. 11A to 13 B are process cross-sectional views showing the manufacturing method of a semiconductor device according to this embodiment.
  • the element isolating region 101 is formed in the silicon substrate 100 .
  • the element isolating region 101 it is possible to use so-called STI (shallow trench isolation) obtained by forming a shallow groove in the silicon substrate 100 by a photo engraving process and filling this groove with a silicon oxide film (an SiO 2 film) formed by, e.g., a CVD (Chemical vapor deposition) method.
  • STI shallow trench isolation
  • an SiO 2 film silicon oxide film
  • CVD Chemical vapor deposition
  • the gate insulating film 103 having, e.g., an SiO 2 film or a silicon oxynitride film (an SiON film) as a material is formed on the silicon substrate 100 and the element isolating region 101 by using the CVD method and the like.
  • An electroconductive material film serving as the gate electrode 104 e.g., a polycrystal silicon film having boron (B) added therein with a high concentration is deposited on the gate insulating film 103 .
  • an oxide film 118 e.g., an SiO 2 film formed by the CVD method is deposited on the polycrystal silicon film.
  • a gate electrode pattern is processed on the oxide film 118 by lithography and etching. Thereafter, this oxide film 118 is used as a mask to etch the polycrystal silicon film, thereby forming the gate electrode 104 . Moreover, the gate insulating film 103 is etched to be removed except a part below the gate electrode 104 .
  • a silicon nitride film (an SiN film) having a film thickness of, e.g., 10 nm is formed on the element isolating region 101 , the silicon substrate 100 , and the gate electrode 104 by the CVD method and the like. Additionally, the silicon nitride film formed on the gate electrode 104 , the silicon substrate 100 , and others is subjected to anisotropic etching, thus forming the first sidewall insulating film 105 on the side surface of the gate electrode 104 .
  • a surface portion of the silicon substrate 100 is etched to be removed with the gate electrode 104 and the first sidewall insulating film 105 being used as a mask, thereby forming a shallow groove 119 for the first source/drain layer 108 serving as an extension layer.
  • the gate electrode 104 is not etched since the oxide film 118 covers the upper surface of the gate electrode 104 .
  • the semiconductor layer 107 e.g., a silicon germanium layer is subjected to selective epitaxial growth on the groove 119 .
  • This selective epitaxial growth of the silicon germanium layer 107 can be realized by adding, e.g., approximately 0.4 vol % to 0.5 vol % of hydrogen chloride (HCl) to hydrogen (H 2 ) as a carrier gas and using a mixed gas containing dichlorsilane (SiH 2 Cl 2 ) and monogermane (GeH 4 ) as a raw material at a temperature of, e.g., 650° C. to 750° C.
  • a gas flow rate of GeH 4 with respect to SiH 2 Cl 2 can be set to, e.g., 2 vol % to 5 vol %. Varying this gas flow ratio enables controlling a germanium concentration in the silicon germanium layer 107 to a desired value.
  • the germanium concentration in this silicon germanium layer 107 is determined to fall within a range of, e.g., 10 at % to 30 at % in order to give a compression stress to the channel region and effectively improve a carrier mobility based on containing germanium, and also to suppress an influence of occurrence of a crystal defect due to excessively containing germanium.
  • a thickness of the silicon germanium layer 107 can be changed in dependence on a gate length.
  • a thickness of the silicon germanium layer 107 can be set to, e.g., 35 nm to 40 nm. However, this value can be increased to enlarge a compression stress that is given to the channel region.
  • a surface of this silicon germanium layer 107 is set higher than that of the silicon substrate 100 in the channel region.
  • a depth of the groove 119 required to form the silicon germanium layer 107 is set to, e.g., 30 nm, and a film thickness of the silicon germanium layer 107 is set to 40 nm.
  • the silicon germanium layer 107 has the elevated structure in this manner, the silicon germanium layer 107 can be formed thick to improve a compression stress.
  • a later-explained effective junction depth of the first source/drain layer 108 can be reduced, thereby suppressing a short channel effect as compared with a flat structure.
  • the first source/drain layer 108 is formed.
  • an impurity that is implanted into the silicon germanium layer 107 it is possible to use, e.g., boron (B).
  • boron (B) when forming the first source/drain layer 108 based on ion implantation, adjusting an implantation energy enables controlling the junction depth. For example, as shown in FIG. 12A , the junction depth of the first source/drain layer 108 can be reduced to be smaller than a thickness of the silicon germanium layer 107 . Additionally, diffusion of boron (B) in the silicon germanium layer 107 is suppressed as compared with diffusion in the silicon substrate, and hence this is advantageous to reduce the junction depth of the first source/drain layer 108 and thereby suppress the short channel effect.
  • an insulating film serving as the second sidewall insulating film 106 e.g., an SiN film or an SiO 2 film having a film thickness of 20 to 30 nm is deposited on the gate electrode 104 and the silicon germanium layer 107 by the CVD method and the like. Thereafter, the insulating film on the gate electrode 104 and the silicon germanium layer 107 is removed by anisotropic etching so that the insulating film remains on the side surface of the gate electrode 104 along, thereby forming the second sidewall insulating film 106 .
  • the gate electrode 104 and the second sidewall insulating film 106 are used as a mask to etch the exposed silicon germanium layer 107 , and a groove 120 required to form the second source/drain layer 111 is thereby formed.
  • the groove 120 can have a depth that allows removing the silicon germanium layer 107 , for example. It is to be noted that an upper surface of the gate electrode 104 is covered with the oxide film 118 in this etching, and hence the gate electrode 104 is not etched. In this manner, the silicon germanium layer 107 remains below the second sidewall insulating film 106 alone, and the first source/drain layer 108 is formed below the second sidewall insulating film 106 .
  • the silicon germanium layer 109 and the germanium layer 110 are sequentially subjected to selective epitaxial growth in the groove 120 .
  • This selective epitaxial growth of the silicon germanium layer 109 can be carried out by adding a small amount of HCl to an H 2 gas as a carrier gas and using SiH 2 Cl 2 and GeH 4 as a raw material gas like the above-explained selective epitaxial growth of the silicon germanium layer 107 .
  • the silicon germanium layer 109 is grown, and then a gas flow ratio at the time of selective epitaxial growth of the silicon germanium layer 109 , i.e., a gas flow rate of GeH 4 with respect to SiH 2 Cl 2 is greatly increased, thereby subjecting the germanium layer 110 to selective epitaxial growth on the silicon germanium layer 109 .
  • growth is effected in such a manner that a germanium concentration in the silicon germanium layer 109 becomes 10 at % to 30 at %, and that a germanium concentration in the germanium layer 110 becomes approximately 100 at %, for example.
  • a total thickness of the silicon germanium layer 109 and the germanium layer 110 is set larger than a depth of the groove 120 , i.e., a thickness of the silicon germanium layer 107 in order to provide the elevated structure to the second source/drain layer 111 formed at this position in a later process.
  • a depth of the groove 120 i.e., a thickness of the silicon germanium layer 107 in order to provide the elevated structure to the second source/drain layer 111 formed at this position in a later process.
  • the gate electrode 104 and the second sidewall insulating film 106 are used as a mask to implant, e.g., a boron (B) ion into the silicon germanium layer 109 and the germanium layer 110 .
  • Ion implantation conditions of the second source/drain layer 111 are a higher energy and a higher concentration than those in ion implantation of the first source/drain layer 108 .
  • the second source/drain layer 11 can be formed to be deeper than the junction depth of the first source/drain layer 108 as extension layer.
  • the second source/drain layer 111 is formed in contact with the first source/drain layer 108 , and it may be formed to be deeper than the silicon germanium layer 109 .
  • the silicon germanium layer 107 exposed on the outer side of the second sidewall insulating film 106 is etched to form the groove 120 , and then the silicon germanium layer 109 is formed in the groove 120 in this embodiment as shown in FIGS. 12B and 12C .
  • the silicon germanium layer 107 may be left as it is without being etched.
  • the germanium layer 110 can be formed on the left silicon germanium layer 107 on the outer side of the second sidewall insulating film 106 .
  • the second source/drain layer 111 may be formed on the silicon germanium layer 107 and the germanium layer 110 on the outer side of the second sidewall insulating film 106 .
  • the oxide film 118 on the gate electrode 104 is removed by wet etching to expose the surface of the polycrystal silicon layer of the gate electrode 104 .
  • the silicide layer 112 is formed on the gate electrode 104
  • the germanide layer 113 is formed on the second source/drain layer 111 . That is, a metal film (not shown) is deposited on the gate electrode 104 and the second source/drain layer 111 by, e.g., sputtering, and then a heat treatment is carried out to react the polycrystal silicon layer on the surface of the gate electrode with the metal film, thereby forming the silicide layer 112 on the gate electrode 104 .
  • the germanium layer 110 at a surface layer portion of the second source/drain layer 111 is reacted with the metal film to form the germanide layer 113 on the second source/drain layer 111 .
  • the second source/drain layer 111 has the germanium layer 110 on an interface between itself and the germanide layer 113 .
  • a metallic material of the metal film it is possible to use a high-melting point metal, e.g., nickel (Ni), cobalt (Co), titanium (Ti), iridium (Ir), platinum (Pt), or palladium (Pd). Then, an unreacted metal film other than the silicide layer 112 and the germanide layer 113 is removed.
  • the barrier insulating film 114 is deposited on the structure depicted in FIG. 13A , and then the interlayer insulating layer 115 is deposited on the barrier insulating film 114 and flattened by, e.g., CMP (Chemical Mechanical Polishing). Further, a contact hole reaching the second source/drain layer 111 is formed in the interlayer insulating layer 115 . Thereafter, the contact hole is filled with an electroconductive material to form a contact plug 117 . Furthermore, the wiring layer 116 connected with the contact plug 117 is formed on the interlayer insulating layer 115 . Subsequently, a process required for a semiconductor device, e.g., multilayer wiring is carried out, thereby manufacturing the semiconductor device according to this embodiment.
  • CMP Chemical Mechanical Polishing
  • the source/drain layers 108 and 111 contain the silicon germanium as a compound of silicon and germanium having a larger atomic radius than silicon, a compression stress can be given to the channel region, and a carrier mobility can be improved.
  • a silicide layer is formed on the source/drain layer.
  • a thermally unstable compound is generated.
  • transistor characteristics may be deteriorated in some cases.
  • the surface layer of the source/drain layer containing the silicon germanium is constituted of a silicon layer having a fixed thickness and the silicide layer is formed on this silicon layer alone to suppress generation of a compound due to a reaction of the silicon germanium and the silicide layer, a contact resistance between the silicon layer and the silicide layer is increased. Therefore, an improvement in transistor characteristics may become insufficient.
  • the surface layer of the second source/drain layer 111 using the silicon germanium is constituted of the germanium layer 110 having a fixed thickness, and the germanide layer 113 is provided on the germanium layer 110 to avoid reaching the silicon germanium layer 109 .
  • the silicon germanium layer 109 of the second source/drain layer 111 does not directly come into contact with the germanide layer 113 , and a thermally unstable compound is not produced, thereby avoiding deterioration in transistor characteristics.
  • a contact resistance between the germanium layer 110 and the germanide layer 113 is lower than a contact resistance between the silicon layer and the silicide layer, deterioration in transistor characteristics can be effectively suppressed.
  • a compression stress can be given to the channel region, a carrier mobility can be improved, and a resistance of the source/drain layer can be reduced without producing a thermally unstable compound on the source/drain layer. As a result, deterioration in transistor characteristics can be suppressed.
  • FIG. 14 is a cross-sectional view of a semiconductor device according to Modification of Embodiment 2.
  • the semiconductor device according to this modification is different from the semiconductor device according to Embodiment 2 in that a thickness of a first source/drain layer 108 as an extension layer is substantially the same as a thickness of a semiconductor layer 107 below a second sidewall insulating film 106 . Therefore, in the following description of the semiconductor device according to this modification, like reference numerals denote parts equal to those in the structure and the manufacturing method of the semiconductor device according to Embodiment 2, thereby omitting a detailed explanation thereof.
  • a first source/drain layer 108 in a semiconductor device according to this modification is formed by doping, e.g., boron (B) simultaneously with selective epitaxial grow of a silicon germanium layer as a semiconductor layer 107 . Therefore, as shown in FIG. 14 , a thickness of the first source/drain layer 108 is substantially the same as a thickness of the silicon germanium layer 107 .
  • a compression stress can be given to a channel region, a carrier mobility can be improved, and a resistance of the source/drain layer can be reduced without producing a thermally unstable compound on the source/drain layer. As a result, deterioration in transistor characteristics can be suppressed.
  • a process of implanting an ion into the semiconductor layer 107 can be omitted in manufacture of the semiconductor device according to Embodiment 2.
  • boron (B) is doped simultaneously with selective epitaxial growth of the semiconductor layer 107 to form the first source/drain layer 108 in this modification.
  • a second source/drain layer 111 may be likewise formed by doping boron (B) simultaneously with selective epitaxial growth of a silicon germanium layer 109 and a germanium layer 110 .
  • FIG. 15 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 2.
  • a semiconductor device according to this modification is different from the semiconductor device according to Embodiment 2 in that a germanide layer 113 formed on a second source/drain layer 111 is in contact with a first source/drain layer 108 as an extension layer. Therefore, in the following description of the semiconductor device according to this modification, like reference numerals denote parts equal to those in the structure and the manufacturing method of the semiconductor device according to Embodiment 2, thereby omitting a detailed explanation thereof.
  • a metal film is formed on a second source/drain layer 111 , and then a heat treatment is carried out to form a germanide layer 113 .
  • the germanide layer 113 is formed to reach a position where it comes into contact with a germanium layer 210 constituting a first source/drain layer 108 formed in proximity to the second source/drain layer 111 .
  • the second source/drain layer 111 likewise has a germanium layer 110 on an interface between itself and the germanide layer 113 in the semiconductor device according to this modification.
  • a contact portion of a semiconductor layer 107 with respect to the germanide layer 113 has a germanium layer 210 in order to prevent a thermally unstable ternary compound NiSiGe being formed on an interface between the germanide layer 113 and the semiconductor layer 107 .
  • a compression stress can be given to a channel region, a carrier mobility can be improved, and a resistance of the source/drain layer can be reduced without producing a thermally unstable compound on the source/drain layer. As a result, deterioration in transistor characteristics can be suppressed.
  • FIG. 16 is a cross-sectional view of a semiconductor device according to this Embodiment.
  • the semiconductor device according to this embodiment is different from the semiconductor device according to Embodiment 2 in that a portion of a silicon germanium layer 109 on both sides of a second sidewall insulating film 106 on a side surface of a gate electrode 104 has a concentration gradient. Therefore, in the following description of this embodiment, like reference numerals denote parts equal to those in the structure and the manufacturing method of the semiconductor device according to Embodiment 2, thereby omitting a detailed explanation thereof.
  • the silicon germanium layer 109 includes a silicon germanium layer 109 B having a predetermined germanium concentration, and a silicon germanium layer 109 C in which the germanium concentration increased toward the upper portion.
  • the silicon germanium layer 109 of this structure is formed on a silicon substrate 100 on both sides of the second sidewall insulating film 106 .
  • the germanium layer 110 is formed on the silicon germanium layer 109 C.
  • germanium concentrations in the silicon germanium layer 109 B and the germanium layer 110 are 10 to 30 at % and approximately 100 at %, respectively.
  • the germanium concentration of the silicon germanium layer 109 C is approximately 10 to 30 at % on an interface between the silicon germanium layer 109 C and the silicon germanium layer 109 B, and increased toward the upper portion.
  • the germanium concentration of the silicon germanium layer 109 C is approximately 100 at % on an interface between the silicon germanium layer 109 C and the germanium layer 110 .
  • a second source/drain layer 111 having an impurity ion implanted therein is formed with respect to this silicon germanium layer 109 B, 109 C, and the germanium layer 110 .
  • a germanide layer 113 is formed on the germanium layer 110 in order to reduce a resistance of the second source/drain layer 111 .
  • a gate electrode 104 , a first source/drain layer 108 , and others are formed on the silicon substrate 100 . Then, a groove 120 is formed in the silicon substrate on both sides of the second sidewall insulating film 106 formed on a side surface of the gate electrode 104 .
  • the silicon germanium layer 109 is subjected to selective epitaxial growth in the groove 120 .
  • the silicon germanium layer 109 B can be grown by adding hydrogen chloride (HCl) to hydrogen (H 2 ) as a carrier gas and performing heating with a mixed gas containing dichlorsilane (SiH 2 Cl 2 ) and monogermane (GeH 4 ) being used as a raw material gas.
  • a gas flow rate of GeH 4 with respect to SiH 2 Cl 2 can be set to, e.g., 2 vol % to 5 vol %.
  • the silicon germanium layer 109 C is continuously subjected to selective epitaxial growth while gradually increasing a gas flow ratio of GeH 4 with respect to SiH 2 Cl 2 to gradually raise a germanium concentration.
  • the gas flow ratio of GeH 4 with respect to SiH 2 Cl 2 is adjusted in such a manner that the germanium concentration of the silicon germanium layer 109 C has a concentration gradient rising to approximately 100 at %.
  • germanium layer 110 whose germanium concentration becomes approximately 100 at % is continuously subjected to epitaxial growth in such a manner that this layer has a thickness of, e.g., approximately 30 nm.
  • the silicon germanium layer 109 B, 109 C, and the germanium layer 110 in the semiconductor device according to this embodiment can be sequentially formed.
  • the silicon germanium is contained in the source/drain layers 108 and 111 to give a compression stress to a channel region and improve a carrier mobility. Further, the germanium layer is formed on the silicon germanium layer, and a high-melting point metal film is formed on this germanium layer to form the germanide layer. As a result, a thermally unstable compound is not produced on the source/drain layer. Therefore, a resistance of the source/drain layer can be reduced, and deterioration in transistor characteristics can be suppressed.
  • a gas flow ratio of GeH 4 with respect to SiH 2 Cl 2 must be precipitously changed to grow the germanium layer 110 on the silicon germanium layer 109 .
  • the silicon germanium layer 109 B, 109 C, and the germanium layer 110 where the second source/drain layer 111 is formed in manufacture of the semiconductor device according to this embodiment the silicon germanium layer 109 B, 109 C, and the germanium layer 110 are continuously grown while gradually increasing a gas flow ratio of GeH 4 with respect to SiH 2 Cl 2 , thereby forming the second source/drain layer 111 . Therefore, manufacture is simple.
  • Embodiment 3 may be modified as shown in FIG. 17 . That is, the semiconductor layer 107 shown in FIG. 16 may include a silicon germanium layer 107 B, a silicon germanium layer 107 C having a concentration gradient, and the germanium layer 210 . In addition, boron (B) may be introduced when the silicon germanium layer is formed.
  • the surface of the first source/drain layer 108 or the surface of the second source/drain layer 111 is placed at a height above the surface of the silicon substrate 100 , but it may be placed at a height equal to or below the surface of the silicon substrate 100 .
  • the silicon germanium layer is used for the semiconductor layer 107 , but a silicon layer may be used as any other material, for example.
  • the germanium layer 110 is directly formed on the silicon germanium layer 109 , but the germanium layer 110 may be formed on the silicon germanium layer 109 via, e.g., a silicon layer.
  • the semiconductor device that improves a carrier mobility and suppresses deterioration in transition characteristics.

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