TWI819682B - 氣相塗佈之方法及氣相沈積製程 - Google Patents

氣相塗佈之方法及氣相沈積製程 Download PDF

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TWI819682B
TWI819682B TW111124341A TW111124341A TWI819682B TW I819682 B TWI819682 B TW I819682B TW 111124341 A TW111124341 A TW 111124341A TW 111124341 A TW111124341 A TW 111124341A TW I819682 B TWI819682 B TW I819682B
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vapor
deposition
passivation
passivated
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瓦倫 夏瑪
艾娃 E 多益斯
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荷蘭商Asmip私人控股有限公司
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Abstract

抑制氣相沈積之鈍化層可在反應器表面上使用以在沈積在容納於其中之基板上的同時使沈積減到最少,或沈積在特定基板表面(諸如半導體基板上之金屬性表面)上使用以促進在相鄰介電性表面上之選擇性沈積。小於典型自組裝單層前驅物之鈍化劑可具有疏水性或非反應性末端,且比自組裝單層更快速地促進更緻密鈍化層,尤其於複雜三維結構上。

Description

氣相塗佈之方法及氣相沈積製程
本申請案大體上為關於在所選表面上,諸如在反應器表面或基板上之所選表面上抑制氣相沈積的鈍化。
原子層沈積(Atomic layer deposition;ALD)為在半導體工業中已知的用於在諸如矽晶圓的基板上形成材料薄膜之製程。ALD為以下類型之氣相沈積,其中膜經由在循環中執行之自飽和表面反應來積聚。在ALD製程中,氣態前驅物被交替且重複地供應至基板,以在基板上形成材料薄膜。一種反應物在自限性過程中吸附在晶圓上。後續反應物脈衝與所吸附之材料反應以形成合乎期望之材料的分子層。後續脈衝可減少或吸收來自所吸附之層的配位體,可置換此類配位體或以其他方式添加原子(例如氧化、氮化等)。在典型ALD反應中,每循環形成不超過一個分子單層。循環可更複雜,且依序涉及三種或超過三種反應物。ALD之一些公認優點為低溫加工及接近完美之保形性,使用於半導體加工之ALD收到較大關注。
除ALD以外,存在其他用於在基板上形成材料薄膜之製程。一種此類製程為化學氣相沈積(chemical vapor deposition;CVD),其中使基板暴露於一或多種揮發性前驅物,該等前驅物在基板上反應及/或分解以形成薄膜。不同於純ALD,在CVD中,相互反應性反應物時常同時暴露於基板上。混合ALD/CVD製程可允許前驅物的某些重疊,以獲得ALD之一些保形性優點及CVD之一些速度優點。ALD及CVD兩者皆可能對暴露表面敏感;視前驅物及沈積條件而定,氣相沈積製程可能在不同表面上充分或不充分地成核。
在加工期間,除可能需要沈積之彼等表面以外,沈積始終在暴露表面上發生。舉例而言,隨著依序加工多個基板,膜積聚可能在反應器之暴露表面上發生。膜積聚可能自反應器之表面分層或片狀剝落,且污染基板表面。在反應器表面上之大量鬆散黏附之膜積聚亦增加暴露於反應物脈衝之總表面積,藉此增加使基板表面飽和所需之脈衝及吹掃時間。另外,膜可能沈積於半導體裝置結構的不合期望之區域,諸如介電性表面上,從而需要額外圖案化及蝕刻步驟。
目前,可獲得防止不合需要之膜沈積於反應器表面及裝置結構上或減小其沈積量的選擇性製程。一些此類製程利用在反應器表面上方產生保護性自組裝單層(self-assembled monolayer;SAM)的處理製程,諸如美國專利第7,914,847號及第8,293,658號中所描述之彼等製程,兩者揭示內容皆出於所有目的以全文引用之方式併入本文中。其他製程利用選擇性沈積於一些類型之基板表面上而在其他基板表面上沈積最少或無沈積的處理製程,諸如上文併入之美國專利第8,293,658號、及美國專利公開案第2016-0247695 A1號、第2015-0299848 A1號、第2015-0217330 A1號及美國專利第9,112,003號中所描述的選擇性沈積製程,其等揭示內容出於所有目的以全文引用之方式併入本文中。
自氣相產生SAM,相對於自液相產生者,其有許多原因為有利的,包括使用與在ALD及CVD中所用相同或類似類型之設備的可能性。有機矽烷類(Organosilane based)之SAM可經由氣相製程產生,但此類SAM通常採用多次及長期暴露,以便產生合乎期望之有機矽烷SAM。
在一個態樣中,提供一種用於氣相塗佈之方法。該方法包括使導電性表面針對氣相沈積而鈍化,其中鈍化包括使該導電性表面暴露於氣相鈍化劑以形成經鈍化之導電性表面。該方法進一步包括藉由使經鈍化之導電性表面及介電性表面兩者暴露於氣相沈積反應物,將一個層相對於經鈍化之導電性表面選擇性地沈積於介電性表面上。
在一些具體例中,鈍化劑包括小於自組裝單層(self-assembled monolayer;SAM)前驅物的具有多於五(5)個碳原子之碳鏈的分子。在一些具體例中,鈍化劑包括鹵素封端。在一些具體例中,經鈍化之導電性表面包括疏水性封端或對氣相沈積反應物之選擇性沈積呈惰性的封端。在一些具體例中,鈍化劑包括具有一或多個烷基鏈之化合物,其中該等烷基鏈各自具有少於5個碳原子。在一些具體例中,鈍化劑包括分子量小於或等於330 g/mol之化合物。
在一些具體例中,鈍化劑包括式C nH 2n+1X、C nH 2nX 2、R 1R 2CX或R 1R 2CX之鹵代烷。在一些具體例中,R 1及R 2各自單獨地為氫或烷基。在一些具體例中,X為鹵素。在一些具體例中,n小於5。
在一些具體例中,鈍化劑包括含鹵素之矽烷、含鹵素之鍺烷、或式SiH 2X 2、SiH 3X、GeH 2X 2或GeH 3X之化合物。在一些具體例中,X為鹵素。
在一些具體例中,鈍化劑包括含鹵素之矽烷、含鹵素之鍺烷、含鹵素之錫烷、或式GeR aX b、SiR aX b、GeR aH cX b、SiR aH cX b、SnR aX b、SnR aH cX b、Sn 2R aH cX b、SiH cXR a之化合物。在一些具體例中,各R單獨地為氫或具有少於5個碳原子之烷基。在一些具體例中,X為鹵素。在一些具體例中,a、b及c為化學計量之整數值,其各自單獨地選自0、1、2、3、4、5、6、7或8。
在一些具體例中,鈍化劑包括式RZ、CF 2HZ、CFH 2Z、(CH 3) 3SiZ、CF 3Z、(CH 3) 3CZ、SnH cR aZ或CH cR aZ之化合物。在一些具體例中,各R單獨地為氫或各自具有少於5個碳原子之烷基。在一些具體例中,Z為烷基、乙酸酯、腈、異腈、異氰酸酯、胺、硫醇、磺醯氯、醯氯或烷氧基。在一些具體例中,a及c為化學計量之整數值,其各自單獨地選自0、1、2、3或4。
在一些具體例中,鈍化劑包括式R 1R 2SiX或R 1R 2R 3SiX之化合物。在一些具體例中,R 1、R 2及R 3各自單獨地為氫或各自具有少於5個碳原子之烷基。在一些具體例中,X為鹵素。
在一些具體例中,鈍化劑在引入以使導電性表面暴露之前未經加熱。
在一些具體例中,導電性表面包括金屬性表面。在一些具體例中,導電性表面包括氮化鈦(TiN)、鎢(W)、鈷(Co)、銅(Cu)、銥(Ir)或氮化鉭(TaN)中之一或多者。在一些具體例中,導電性表面包括TiN、W、Co、Cu或TaN中之一或多者。
在一些具體例中,介電性表面包括氧化物或氮化物表面。在一些具體例中,介電性表面包括氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、氧化鈦(titanium oxide)、氮化矽(silicon nitride)或原生氧化物(native oxide)。
在一些具體例中,選擇性地沈積包括原子層沈積。在一些具體例中,選擇性地沈積包括沈積介電層。在一些具體例中,選擇性地沈積進一步包括供應水、氧(O 2)、氨(NH 3)或臭氧(O 3)。在一些具體例中,選擇性地沈積包括供應包括環戊二烯基、烷基、醯胺基或烷氧基配位體之金屬前驅物。
在一些具體例中,導電性表面之鈍化相對於介電性表面選擇性地形成經鈍化之導電性表面。在一些具體例中,在不阻擋介電性表面上之鈍化且在導電性表面上無催化劑的情況下,鈍化直接形成在導電性表面上。在一些具體例中,導電性表面之鈍化在約1天或少於1天內執行。
在另一態樣中,提供一種氣相沈積製程。該製程包括使導電性表面針對氣相沈積而鈍化,其中鈍化包括使該導電性表面暴露於包括氣相鹵化物之鈍化劑以形成經鈍化之導電性表面。進一步包括藉由使經鈍化之導電性表面及介電性表面兩者皆暴露於氣相沈積反應物,將一個層相對於經鈍化之導電性表面選擇性地沈積於介電性表面上。
在一些具體例中,導電性表面為金屬表面或金屬氮化物表面。在一些具體例中,導電性表面包括氧。在一些具體例中,導電性表面包括TiN,且介電性表面包括氧化鋯(zirconium oxide;ZrO 2)。
在一些具體例中,鈍化劑為有機鹵化物。在一些具體例中,鈍化劑包括二氯甲烷。
在一些具體例中,鈍化劑包括式C nH 2n+1X、C nH 2nX 2、R 1R 2CX或R 1R 2CX之鹵代烷。在一些具體例中,R 1及R 2為氫或烷基。在一些具體例中,X為鹵素。在一些具體例中,n小於5。
在一些具體例中,鈍化劑包括含鹵素之矽烷、含鹵素之鍺烷、或式SiH 2X 2、SiH 3X、GeH 2X 2或GeH 3X之化合物。在一些具體例中,X為鹵素。
在一些具體例中,鈍化劑包括含鹵素之矽烷、含鹵素之鍺烷、含鹵素之錫烷、或式GeR aX b、SiR aX b、GeR aH cX b、SiR aH cX b、SnR aX b、SnR aH cX b、Sn 2R aH cX b、SiH cXR a之化合物。在一些具體例中,各R單獨地為氫或具有少於5個碳原子之烷基。在一些具體例中,X為鹵素。在一些具體例中,a、b及c為化學計量之整數值,其各自單獨地選自0、1、2、3、4、5、6、7或8。
在一些具體例中,鈍化劑包括含鹵素之矽烷、含鹵素之鍺烷、含鹵素之錫烷、或式RZ、CF 2HZ、CFH 2Z、(CH 3) 3SiZ、CF 3Z、(CH 3) 3CZ、SnH cR aZ或CH cR aZ之化合物。在一些具體例中,各R單獨地為氫或各自具有少於5個碳原子之烷基。在一些具體例中,Z為烷基、乙酸酯、腈、異腈、異氰酸酯、胺、硫醇、磺醯氯、醯氯或烷氧基。在一些具體例中,a及c為化學計量之整數值,其各自單獨地選自0、1、2、3或4。
在一些具體例中,鈍化劑包括式R 1R 2SiX或R 1R 2R 3SiX之化合物。在一些具體例中,R 1、R 2及R 3可為氫或各自具有少於5個碳原子之烷基。在一些具體例中,X為鹵素。
在一些具體例中,選擇性地沈積包括進行原子層沈積製程。
在一些具體例中,導電性表面之鈍化在約1天或少於1天內執行。
本文描述用於使表面針對氣相沈積製程而鈍化之製程,該等表面諸如經部分加工之半導體基板表面或半導體處理設備表面。本文中所教示之製程尤其適用於使導電性(例如金屬性)表面鈍化以允許後續在介電性表面上選擇性沈積。
如在先前技術部分中所指出,存在使特定表面(例如反應器表面及經部分製造之積體電路結構的表面)針對氣相沈積而失活的製程,諸如ALD,以允許在未經處理之表面上選擇性沈積。一種此類製程涉及在不需要膜沈積之暴露表面上方形成自組裝單層(self-assembled monolayer;SAM)。SAM為自氣相或液相前驅物自發地吸附(亦稱為以化學方式吸附)在表面上的相對有序之分子組裝體。典型SAM分子包括末端官能基、烴鏈及頭基。藉由在所選表面上方形成SAM,該SAM可防止暴露表面上的膜生長,此乃使用某些類型之氣相前驅物,藉由阻擋在該等暴露表面上方之反應性位點,否則其將與彼等沈積前驅物反應。此類選擇性失活可尤其有效針對吸附驅動之製程,如ALD,但亦可阻礙某些類型之CVD。
圖1A及1B繪示經歷ALD前驅物138的上覆有緻密填充之理想SAM 122的表面106。如上文所指出,表面106可為於其上方之後續沈積待抑制的任何表面。所形成之SAM 122通常由相對長鏈單體形成,通常包括長度長於6個碳之碳鏈,諸如十八烷基三氯矽烷(octadecyltrichlorosilane;ODTS),以使得可藉由自組裝形成高度有序之單層。形成SAM之單體可以液體或蒸氣形式遞送。如圖1A中所顯示,SAM分子134在理論上緻密填充,以使得其佔據表面106上方之所有反應性位點。在ALD製程期間,可將諸如四氯化鉿(HfCl 4)、四氯化鋯(ZrCl 4)、四氯化鈦(TiCl 4) 或三甲基鋁(trimethyl aluminum;TMA)之ALD前驅物引入至反應器中。此等前驅物將傾向於與反應器中之暴露表面反應,包括反應器壁及暴露之基板表面。然而,對於上覆有由長鏈單體形成之緻密填充之SAM 122的彼等表面106,當ALD前驅物如圖1A中所顯示接近時,如圖1B中所顯示,SAM 122可藉由阻擋下方表面106之反應性位點來防止該下方表面106與ALD前驅物反應。藉由使用SAM 122來阻擋反應性位點,有可能將膜沈積於某些暴露表面上,同時防止膜沈積於由失活性SAM覆蓋之其他表面上或使該膜沈積減到最少,以使得沈積製程具有選擇性。在一個實施例中,可阻擋基板上之絕緣體,同時在同一基板之相鄰導體表面上進行沈積。在另一個實施例中,可阻擋反應器壁,同時在該反應器中的未經處理之基板上進行沈積。
較大有機分子可在反應器表面上形成極穩定且不容易自該表面解吸附的自組裝單層(SAM)。另外,較大有機尾部提供所期望之位阻作用,且不允許ALD反應物到達反應器表面。
不利的是,阻擋性SAM之分子很少佔據表面106上之每個反應性位點,以使得該SAM下方之表面106時常具有暴露之反應性位點,例如-OH封端位點(顯示於圖2A中),其可能不合期望地與沈積前驅物反應。雖然不受理論的束縛,可能的是位阻可具有此副作用:吸附在反應性位點上之SAM分子可本身彼此相互作用,而非形成完美定向的緻密填充之分子,使得所吸附之SAM分子不能恰當地定向且因此其等本身妨礙其他SAM分子與可用反應性位點吸附。使未被佔據之反應性位點減到最少,通常意謂暴露於SAM單體,通常在液態前驅物中,持續數小時或甚至數天。即使在暴露於氣相或液相SAM化學物質中數天之後,下方表面之反應性位點仍保持未被佔據,且可在後續沈積期間充當用於生長之成核位點,尤其用於不受不完美SAM中之位阻阻擋的較小沈積前驅物。
圖2A及2B繪示自組裝單層122經歷ALD前驅物138之表面106。如圖2A中所顯示,即使在將SAM 122沈積於表面106上方之後,該表面106仍具有暴露之原生氧化物羥基,該等羥基充當ALD前驅物138在沈積期間可接近之反應性位點144。此外,在複雜三維結構的情況下獲得完全表面覆蓋可甚至更具挑戰性,該等複雜三維結構越來越多地用於半導體加工,諸如MEMS裝置、finFET結構、高縱橫比電容式結構等。如圖2B中所顯示,當在沈積製程期間引入諸如HfCl 4之ALD前驅物138時,該等ALD前驅物138可與暴露之反應性位點144反應,引起不合期望之生長或成核。 基板表面
根據本案揭示內容之一些態樣,可使用選擇性沈積來將相關膜相對於第一表面優先沈積於第二表面上。兩個表面可具有不同材料性質以容許於其上選擇性形成鈍化材料,諸如使鈍化層相對於第二表面選擇性形成於第一表面上,其繼而容許後續將相關層相對於經鈍化之第一層選擇性沈積於第二表面上。
舉例而言,在本文中所描述之具體例中,其中一表面可為基板之導電性(例如,金屬或金屬性)表面,同時另一表面可為基板之非導電性(例如,無機介電性)表面。兩個表面之間的材料差異為使得氣相沈積方法可使鈍化層相對於第二表面選擇性地形成於第一表面上。在一些具體例中,使用循環氣相沈積,例如,使用循環CVD或原子層沈積(atomic layer deposition;ALD)製程。在一些具體例中,可達成用於形成鈍化層之選擇性,而不用表面上之鈍化/阻擋劑以接收較少鈍化層;及/或不用表面上之催化劑以接收較多鈍化層。舉例而言,在其中第一表面為金屬性且第二表面為介電性之具體例中,鈍化層可相對於介電性表面直接選擇性地形成於金屬性表面上。在完成鈍化層之選擇性形成之後,相關材料之進一步選擇性沈積(諸如介電層在介電性材料上之進一步選擇性沈積)可相對於經鈍化之第一表面於未經鈍化之第二表面上進行。
對於一個表面包含金屬而另一表面不包含的具體例,除非另外指示,否則若在本文中將一表面稱為金屬表面,則其可為金屬表面或金屬性表面。在一些具體例中,金屬或金屬性表面可包含金屬、金屬氧化物及/或其混合物。在一些具體例中,金屬或金屬性表面可包含表面氧化。在一些具體例中,金屬或金屬性表面之金屬或金屬性材料在存在或不存在表面氧化的情況下具有導電性。在一些具體例中,金屬或金屬性表面包含一或多種過渡金屬。在一些具體例中,金屬或金屬性表面包含TiN、W、Co、Cu、Ir或TaN中之一或多者。在一些具體例中,金屬或金屬性表面包含鋁(Al)、鎳(Ni)、鈮(Nb)、鐵(Fe)中之一或多者。在一些具體例中,金屬或金屬性表面包含一或多種貴金屬,諸如釕(Ru)。在一些具體例中,金屬或金屬性表面包含導電性金屬氧化物、氮化物、碳化物、硼化物或其組合。舉例而言,金屬或金屬性表面可包含RuO x、NbC x、NbB x、NiO x、CoO x、NbO x、WNC x、TaN或TiN中之一或多者。在下文所指出之實驗中,金屬性表面包含氮化鈦。
在一些具體例中,金屬或金屬性表面包含鈷(Co)、銅(Cu)或鎢(W)。在一些具體例中,金屬或金屬性表面可為任何可接受本文中所描述的用於鈍化層之選擇性沈積製程中之鈍化劑或與其配位的表面。
在一些具體例中,將鈍化材料相對於第二介電性表面選擇性地沈積於第一表面(其為金屬性材料之經氧化表面)上。
在一些具體例中,第一表面為基板之金屬或金屬性表面,且另一表面為基板之介電性表面。術語介電性在本文說明中用於簡單地與另一表面(即金屬或金屬性表面)相區分。熟悉技藝人士應理解,並非所有非導電性表面皆為介電性表面,且反之,並非所有金屬性表面皆具導電性。舉例而言,金屬或金屬性表面可包含可產生高電阻率之一定氧化。不論導電性程度如何,本文中所教示之選擇性沈積製程可在介電性表面上沈積而在經鈍化之金屬性表面上沈積最少。
在一些具體例中,可在選擇性沈積製程之前或在其開始時對基板進行預處理或清潔。在一些具體例中,可在選擇性沈積製程之前或在其開始時使基板經歷電漿清潔製程。在一些具體例中,電漿清潔製程可不包括離子轟擊,或可包括相對少量之離子轟擊。舉例而言,在一些具體例中,可在選擇性鈍化之前或在其開始時使基板表面暴露於電漿、自由基、受激發物種及/或原子物種。在一些具體例中,可在選擇性鈍化之前或在其開始時使基板表面暴露於氫電漿、自由基或原子物種。在一些具體例中,可在選擇性鈍化之前或在其開始時用暴露於氫氣、氨氣及其混合物中來對基板表面進行熱處理。在一些具體例中,可在與選擇性沈積製程相同之反應腔室中進行預處理或清潔製程,然而,在一些具體例中,可在另外單獨反應腔室中進行預處理或清潔製程,且亦可在與後續選擇性沈積不同之另外單獨腔室中進行鈍化製程。
未經鈍化且其上可在使導電性表面鈍化之後進行選擇性沈積的介電性表面之實施例包括無機介電性材料,諸如氧化鉿、氧化鋯、氧化鈦、矽之原生氧化物、氮化矽、氮氧化矽等。 選擇性
熟悉技藝人士應瞭解,鈍化層及後續相關層之選擇性形成可具有完全選擇性或部分選擇性。部分選擇性製程可藉由自表面B上方移除所有沈積材料而不自表面A上方移除所有沈積材料之沈積後蝕刻來產生完全選擇性層。由於簡單回蝕製程可無需昂貴之遮蔽製程而留下完全選擇性結構,因此選擇性沈積無需具完全選擇性以便獲得合乎期望之效益。
相對於表面B沈積於表面A上之選擇性可以藉由[(於表面A上之沈積)-(於表面B上之沈積)]/(於表面A上之沈積)所計算的百分比形式給出。沈積可以多種方式中之任一者加以測量。舉例而言,沈積可以沈積材料之厚度的測量值形式給出,或可以沈積材料之量的測量值形式給出。在本文中所描述之具體例中,鈍化層之選擇性形成可相對於第二表面(B)於第一表面(A)上進行。隨後,將相關層相對於第一表面上方之鈍化層(其出於應用上式之目的成為B)選擇性地沈積於第二表面(其出於應用上式之目的成為A)上。
在一些具體例中,鈍化層(相對於第二表面)選擇性形成於第一表面上之選擇性及/或相關層(相對於第一表面上之鈍化層)於第二表面上之選擇性為大於約10%,大於約50%,大於約75%,大於約85%,大於約90%,大於約93%,大於約95%,大於約98%,大於約99%或甚至大於約99.5%。視表面及前驅物化學物質而定,相對於經鈍化之金屬性表面沈積於介電性表面上方之選擇性可在沈積之持續時間或厚度內變化。若為該情況,則可藉由重複暴露於鈍化劑來提昇選擇性,例如在多個ALD循環與一個鈍化製程之間循環。
在一些具體例中,鈍化層僅於第一表面上形成,而不於第二表面上形成。在一些具體例中,相對於基板之表面B沈積於基板之表面A上具有至少約80%選擇性,其對於一些特定應用可為足夠選擇性。在一些具體例中,相對於基板之表面B沈積於基板之表面A上具有至少約50%選擇性,其對於一些特定應用可為足夠選擇性。在一些具體例中,相對於基板之表面B沈積於基板之表面A上具有至少約10%選擇性,其對於一些特定應用可為足夠選擇性。熟悉技藝人士應瞭解,部分選擇性製程可藉由自表面B上方移除所有沈積材料而不自表面A上方移除所有沈積材料之沈積後蝕刻來產生完全選擇性結構層。
在一些具體例中,鈍化層選擇性地於基板之第一表面上形成,且可具有小於約3 nm、小於約2 nm或小於約1 nm之厚度,同時沈積於基板之第一表面上相對於基板之第二表面上的材料比率可大於或等於約20:1、大於或等於約15:1、大於或等於約10:1、大於或等於約5:1、大於或等於約3:1、或大於或等於約2:1。
在一些具體例中,本文中所描述之選擇性沈積製程的選擇性可視構成基板之第一表面及/或第二表面的材料而定。舉例而言,在一些具體例中,在第一表面包含經鈍化之Cu表面且第二表面包含自然或化學二氧化矽表面的情況下,相關層之選擇性可大於約8:1或大於約15:1。在一些具體例中,在第一表面包含金屬且第二表面包含自然或化學二氧化矽表面的情況下,選擇性可大於約5:1或大於約10:1。 導電性表面之鈍化及介電質上之選擇性沈積
圖3A-3D示意性地繪示用於相對於第二表面使第一表面選擇性鈍化,隨後再相對於經鈍化之第一表面選擇性沈積於第二表面上的第一具體例。在所繪示之具體例中,第一表面包含金屬性材料,第二表面包含介電性材料;且沈積於第二表面上之相關材料包含介電性材料。因此,具體例包含選擇性介電質於介電質上之沈積。
圖3A繪示具有材料上不同之暴露表面的基板。舉例而言,第一表面可包含金屬,諸如氮化鈦(TiN)、鎢(W)、鈷(Co)、銅(Cu)或氮化鉭(TaN)。第二表面可包含介電質,諸如低k層(通常為氧化矽類(silicon oxide-based)之層)、在其上方形成有原生氧化物(亦為一種形式之氧化矽)的矽表面、氧化鉿(HfO x)、氧化鋯(ZrO x)、氧化鈦(TiO x)、氮化矽(SiN x)等。
圖3B顯示在將鈍化層選擇性沈積於第一表面上方之後的圖3A之基板。舉例而言,鈍化層可藉由使圖3A的經圖案化之表面暴露於二氯甲烷(DCM)來形成。下文提供關於使用具有疏水性或非反應性末端之小分子來選擇性形成鈍化層的進一步資訊及實施例。
圖3C顯示在將相關層X相對於第一表面上之鈍化層選擇性沈積於第二表面(在此實施例中為介電性表面)上之後的圖3B之基板。相關層X可為介電性材料,特定言之金屬氮化物或金屬氧化物,諸如氧化鋯、氧化鉿或氧化鈦。用於選擇性介電質沈積之前驅物包括(但不限於)包括環戊二烯基、烷基、醯胺基及/或烷氧基配位體之金屬前驅物;及氧或氮前驅物,諸如H 2O、O 2、NH 3或O 3。用於藉由氣相沈積技術,採用疏水性前驅物輔助相對於一些類型之鈍化層的選擇性來選擇性地沈積此類金屬氧化物層之方法揭示於美國專利公開案 第2017/0323776號中,其全部揭示內容出於所有目的以引用之方式併入本文中。下文提供關於金屬氧化物及其他相關層之選擇性沈積的進一步資訊及實施例。
沈積於第一表面上方之鈍化層上的任何X材料皆可藉由回蝕製程來移除。由於相關層選擇性地沈積於第二表面上,因此留在鈍化表面上之任何X材料皆將比形成於金屬性表面上之鈍化層薄。因此,可控制回蝕製程以移除鈍化層上方之所有X材料,而不自介電性表面上方移除所有相關層。以此方式重複地選擇性沈積及回蝕可導致於介電質上之X材料的厚度隨各循環的沈積及蝕刻而增加。可替代地,形成於鈍化層上之任何X材料皆可在後續移除鈍化層期間,如下文圖3D中所繪示,在剝離製程中移除。如技藝中所已知,剝離製程藉由利用移除下方材料底切來移除上覆材料。在短暫選擇性沈積製程中形成於鈍化層上之任何X材料皆傾向於為非連續的,從而容許蝕刻劑到達待移除之下方材料。剝離蝕刻無需完全地移除鈍化層以自鈍化層表面移除所有不合期望之X材料,以使得可使用直接蝕刻或剝離方法來於循環選擇性沈積及移除中自鈍化層表面移除X材料。
圖3D顯示在自第一表面移除鈍化層之後的圖3C之基板。在一些具體例中,蝕刻製程可包含使基板暴露於電漿中。在一些具體例中,可藉由包含氧原子、氧自由基、氧電漿或其組合之電漿來移除鈍化層。在一些具體例中,電漿可包含氫原子、氫自由基、氫電漿或其組合。在一些具體例中,電漿亦可包含鈍氣物種,例如氬(Ar)或氦(He)物種。在一些具體例中,電漿可基本上由鈍氣物種組成。在一些實例中,電漿可包含其他物種,例如氮原子、氮自由基、氮電漿或其組合。在一些具體例中,蝕刻製程可包含使基板暴露於包含氧之蝕刻劑,例如O 3。在一些具體例中,基板可在介於約30℃與約500℃之間,較佳介於約100℃與約400℃之間的溫度下暴露於蝕刻劑中。在一些具體例中,蝕刻劑可以一個連續脈衝供應或可以多個較短脈衝供應。如上文所指出,鈍化層移除亦可在循環選擇性沈積及移除中以完全移除鈍化層或以部分移除鈍化層形式自鈍化層上方剝離任何剩餘X材料。
可在前述製程之前、之後或之間進行諸如熱或化學處理的額外處理。舉例而言,處理可改變表面或移除於製程之各個階段暴露的金屬、氧化矽、鈍化及金屬氧化物表面之部分。在一些具體例中,可在選擇性沈積製程之前或在其開始時對基板進行預處理或清潔。在一些具體例中,可在選擇性沈積製程之前或在其開始時使基板經歷電漿清潔製程。在一些具體例中,電漿清潔製程可不包括離子轟擊,或可包括相對少量之離子轟擊。舉例而言,在一些具體例中,可在選擇性沈積製程之前或在其開始時使基板表面暴露於電漿、自由基、受激發物種及/或原子物種中。在一些具體例中,可在選擇性沈積製程之前或在其開始時使基板表面暴露於氫電漿、自由基或原子物種中。在一些具體例中,可在與選擇性沈積製程相同之反應腔室中進行預處理或清潔製程,然而,在一些具體例中,可在另外單獨反應腔室中進行預處理或清潔製程。
在一些具體例中,表面之鈍化在約1天或少於1天、約12小時或少於12小時、約6小時或少於6小時、約2小時或少於2小時、或約1小時或少於1小時、或介於此等值中之任一者之間的任何範圍內執行。 鈍化前驅物
如上文所指出,SAM可能花費較長時間(數天)以完全形成緻密之有效障壁來抑制沈積。大分子可能干擾對待針對後續氣相沈積而失活之表面上之所有反應性位點的接近。
因此,本案揭示內容採用比典型SAM前驅物小之鈍化劑。具有疏水性或非反應性末端之較小試劑包括例如CH 2X 2、CH 3X,其中X為鹵素,及下文所列之其他實施例。較小分子可使相關表面更快速鈍化。
在一些具體例中,鈍化前驅物包含式C nH 2n+1X、C nH 2nX 2、R 1R 2CX或R 1R 2CX之鹵代烷,其中: R 1及R 2可為氫或烷基;及 X可為鹵素,諸如氯(Cl)、氟(F)、溴(Br)或碘(I)。
所描述之前述鹵代烷及其他鈍化前驅物尤其有益於以最小暴露時間緻密鈍化,且為n < 5之小分子。許多此類分子即使在室溫下仍可具有足以用於向待鈍化之表面進行氣相遞送的足夠高之蒸氣壓,以使得鈍化劑來源無需經加熱。諸如起泡器及蒸發器的經加熱之氣相來源可能藉由引起一定量之熱分解而降低系統效率。雖然在一些具體例中亦可採用較長鏈有機分子(例如n ≥ 5),但隨著分子大小增加,更期望進行加熱以獲得足以用於遞送之足夠蒸氣壓,且無針孔(pin-hole free)之緻密鈍化層變得難以達成或必然伴有較長暴露時間。
在一些具體例中,小鈍化劑之分子量可小於或等於330 g/mol、小於或等於250 g/mol、小於或等於170 g/mol、小於或等於120 g/mol、或小於或等於60 g/mol、或為介於此等值中之任一者之間的任何範圍。舉例而言,在一些具體例中,分子量小於或等於250 g/mol之小鈍化劑可為三甲基矽烷基硫醇、三氯錫烷、二氯錫烷、氯錫烷、二甲基矽烷硫醇及甲基矽烷硫醇。在一些具體例中,分子量小於或等於120 g/mol之小鈍化劑的其他實施例包括二氯甲烷(dichloromethane;DCM)及三氟甲基硫醇。在一些具體例中,分子量小於或等於60 g/mol之小鈍化劑的其他實施例包括氯甲烷、甲硫醇、甲腈(methanenitrile)、氰酸甲酯及異甲腈(methanisonitrile)。在一些具體例中,分子量小於或等於330 g/mol之小鈍化劑的其他實施例包括六甲基二錫(hexamethylditin)及氯五甲基二錫(chloropentamethylditin)。在一些具體例中,小鈍化劑在一個小鈍化劑分子中之原子總數目可少於或等於5、少於或等於7、少於或等於10、少於或等於15、少於或等於20、或少於或等於25個原子,或為介於此等值中之任一者之間的任何範圍。
在一些具體例中,小鈍化劑可為有機不飽和烷烴。在一些具體例中,有機烷烴可含有少於或等於5個碳原子、少於或等於4個碳原子、少於或等於3個碳原子、少於或等於2個碳原子、或少於或等於一個碳原子、或介於此等值中之任一者之間的任何範圍。舉例而言,在一些具體例中,含有少於或等於5個碳原子之有機烷烴包括丙二烯、丁二烯及丙烯。在另一個實施例中,在一些具體例中,含有少於或等於5個碳原子之鹵代烷包括二氯甲烷(dichloromethane;DCM)及氯甲烷。
在一些具體例中,鈍化劑包含式SiH 2X 2、SiH 3X、GeH 2X 2或GeH 3X之鹵代矽烷或鹵代鍺烷,或通式GeR aX b、SiR aX b、GeR aH cX b或SiR aH cX b之鹵代矽烷或鹵代鍺烷,其中: R可為氫或烷基; X可為鹵素,諸如Cl、F、Br或I;及 a、b及c為化學計量之整數值,其各自單獨地選自0、1、2、3或4。
在一些具體例中,鈍化劑包含式SnH 3X、SnH 2X 2或SnH 3X之鹵代錫烷、或通式SnR aX b、SnR aH cX b或Sn 2R aH cX b之鹵代錫烷,其中: R可為氫或烷基; X可為鹵素,諸如Cl、F、Br或I;及 a、b及c為化學計量之整數值,其各自單獨地選自0、1、2、3、4、5、6、7或8。
在一些具體例中,鈍化劑包含式RZ、CF 2HZ、CFH 2Z、(CH 3) 3SiZ、CF 3Z、(CH 3) 3CZ、SnH cR aZ或CH cR aZ之化合物,其中: R可為氫或烷基; Z可為官能基。在一些具體例中,Z可為烷基、乙酸酯、腈、異腈、異氰酸酯、胺、硫醇、磺醯氯、醯氯或烷氧基。舉例而言,在一些具體例中,Z可為甲氧基、乙氧基、甲磺醯氯、反丁烯二醯氯、三甲基乙磺醯氯、異丁磺醯氯、三氟甲硫醇、三甲基矽烷基疊氮化物、三甲基矽烷基乙酸酯或甲基;及 a及c為化學計量之整數值,其各自單獨地選自0、1、2、3或4。
在一些具體例中,鈍化劑包含式R 1R 2SiX或R 1R 2R 3SiX之化合物,其中: R 1、R 2及R 3可為氫或烷基; X可為鹵素,諸如Cl、F、Br或I。
前述化合物每分子可包括超過兩個鹵素原子,諸如1,2二氯乙烷,且可具有諸如F或烷氧基之官能基。
在一些具體例中,小鈍化劑可配位至金屬表面上。在一些具體例中,小鈍化劑可與官能化介電性表面反應。在一些具體例中,小鈍化劑包含烷基。在一些具體例中,烷基可含有少於或等於10、7、5、4或3個碳原子、或此等值中之任一者之間的任何範圍。 處理流程
圖4-7提供用於鈍化及選擇性沈積之處理流程的實施例。
最初參看圖4,製程400包含步驟410用小分子鈍化劑使導電性表面鈍化。如上文所指出,小係與習知SAM前驅物相比,該等習知SAM前驅物通常包括提供高度自身有序性以及穩定性之相對較長(> 5)碳鏈。上文提供鈍化劑之適合類別及實施例,其通常包括背向鈍化中之導電性表面的疏水性或在其他情況下非反應性之封端。導電性表面可包含例如反應器的金屬性表面或經部分製造之積體電路上之導體的金屬性表面。鈍化可具有選擇性,例如藉由未能黏附於介電性材料而具有選擇性。
在步驟410鈍化後,步驟420將材料相對於經鈍化之導電性表面選擇性地沈積於介電性表面上。實施例包括表面敏感性氣相沈積製程,諸如CVD及ALD,該等製程可藉由步驟410鈍化來抑制或甚至失活。選擇性可為絕對選擇性,但可為顯著小於絕對選擇性,尤其在將底切及移除鈍化層上方之任何沈積的可能後續鈍化層移除的情況下。介電質可處於在反應器表面鈍化之後裝載至反應器中的基板上,或可處於與同一基板上經鈍化之導體相鄰的介電性表面上。
可能的是,步驟410鈍化可滿足步驟420選擇性沈積之持續時間。然而,可能的是,步驟410鈍化不能承受尤其冗長之沈積製程、尤其具反應性之沈積反應物或尤其嚴苛之沈積條件(例如高溫,諸如大於約420℃,且特定言之高於約450℃)。在此類情形中,可能期望以循環方式步驟430重複步驟410鈍化及步驟420選擇性沈積。
現參看圖5,更特定之實施例製程500包括步驟510最初使金屬性表面鈍化,後接ALD工序520。所繪示之ALD工序520包括步驟525供應金屬前驅物、步驟530自相關表面移除任何過量前驅物及副產物、步驟535供應第二反應物以形成介電性材料、及步驟540自相關表面移除任何過量前驅物及副產物。ALD工序520可將介電性材料,一般每循環少於約一個單層之介電性材料相對於經鈍化之金屬性表面選擇性地沈積於介電性表面上。如關於圖4中之步驟430重複所指出,在許多循環之後,可能的是平均起來,應對鈍化進行更新。此在圖5中由判斷框550指示,其中決定是否期望進一步鈍化。若期望進一步鈍化,則製程可循環(loop)或步驟555重複以使步驟510金屬性表面鈍化開始之製程。若不期望進一步鈍化,則在判斷框560處判定沈積是否完全。若沈積不完全,則可重複ALD工序520。
圖6繪示用於使基板之部分鈍化且選擇性地沈積於該基板之其他部分上之製程600的特定實施例。特定言之,製程600可包括步驟610將基板裝載至製程腔室中。在製程腔室中步驟620使基板之金屬性表面鈍化。隨後,步驟630選擇性沈積相對於經鈍化之金屬性表面,在基板之介電性表面上執行。步驟630選擇性沈積可為表面敏感性製程,諸如CVD或ALD,且可例如將介電性金屬氧化物沈積於介電性表面上而在經鈍化之金屬性表面上沈積最少或無沈積。步驟630選擇性沈積可在與步驟620鈍化相同之腔室中執行,可在使用相同成簇工具(參見下文實驗討論)之不同腔室中執行,或可在不同工具中一起執行。雖然未顯示,但在嚴苛條件磨損鈍化之後,製程可循環地步驟620鈍化及步驟630選擇性沈積以用於提昇選擇性或更新鈍化。
圖7繪示用於使反應器表面鈍化且相對於反應器表面選擇性地沈積於基板上一種製程700的特定實施例。特定言之,製程600包括步驟710使反應器表面鈍化,諸如藉由向反應器表面供應鈍化劑來鈍化。反應器表面可包括其中加工基板之製程腔室的內表面,且亦可包括暴露於加工反應物中之相鄰表面,諸如入口及出口表面。隨後步驟720將基板裝載至反應器之製程腔室中,且步驟730相對於該反應器的經鈍化之金屬性表面,在該基板之至少一些表面上執行選擇性沈積。步驟730選擇性沈積可為表面敏感性製程,諸如CVD或ALD,且可例如將介電性金屬氧化物沈積於基板上×介電性表面上而在反應器的經鈍化之金屬性表面上沈積最少或無沈積。 實驗結果
圖8繪示用小分子鈍化劑使各種材料鈍化之實驗的結果及此後其對介電質之後續ALD的作用。特定言之,在成簇工具之製程腔室中,在420℃下使各種材料(TiN、矽之原生氧化物、ZrO x)暴露於多個脈衝(200或500個)的作為鈍化劑之二氯甲烷(DCM)中。隨後,使基板各自經歷多個循環(25或50個)的用於ZrO x之ALD製程,包括在不破壞真空的情況下,在具有相同成簇工具之ALD製程腔室中,在150℃下使基板交替暴露於ZrDO 4及水中。儘管暴露於500個循環之DCM鈍化劑中,但介電性材料中之每一者皆未針對後續ZrO 2ALD而鈍化。在未任意暴露於鈍化劑中(「無鈍化」)的情況下,ZrO 2容易沈積於TiN上,如由20原子 % Zr所指示,如藉由XPS分析所測量,指示ZrO 2ALD製程將沈積於未經鈍化之TiN上。然而,僅獲得3原子 % Zr的經鈍化之TiN,如藉由XPS分析所測量,即使在50個循環之ZrO 2ALD之後仍如此。因此,DCM成功地使導電性表面針對ZrO 2ALD而鈍化,而不使介電性表面鈍化。吾人預期,鈍化及沈積之進一步循環可獲得甚至更好之選擇性。
圖9顯示以不同形式進行之相同實驗的結果,且繪示200個循環之DCM暴露成功地使TiN基板針對ZrO 2ALD而鈍化,而500個循環之DCM暴露未能使介電性(原生氧化物及ZrO x)基板鈍化。在DCM暴露之前及之後亦測量水接觸角,且發現其對TiN自約25º增加至約90º。
對熟悉本技藝者將顯而易見的是,在不背離本發明之範疇或精神的情況下,可在本發明中進行各種修改及變化。因此,意欲本發明涵蓋本發明之修改及變化,而限制條件為其等在所附申請專利範圍及其等效物範疇內出現。
106:表面 122:SAM/自組裝單層 134:SAM分子 138:ALD前驅物 144:反應性位點 400:製程 410:鈍化步驟 420:選擇性沈積步驟 430:重複步驟 500:製程 510:鈍化步驟 520:ALD工序 525:供應步驟 530:移除步驟 535:供應步驟 540:移除步驟 550:判斷框 555:循環或重複步驟 560:判斷框 600:製程 610:裝載步驟 620:鈍化步驟 630:選擇性沈積步驟 700:製程 710:鈍化步驟 720:裝載步驟 730:選擇性沈積步驟
圖1A及1B繪示暴露於ALD前驅物的上覆有緻密填充之理想自組裝單層(self-assembled monolayer;SAM)的表面。 圖2A及2B繪示暴露於ALD前驅物的上覆自組裝單層具有一些未被佔據之反應性位點的表面。 圖3A為根據第一具體例的具有組成不同之第一表面及第二表面的基板之一部分的示意性橫截面。 圖3B為圖3A之基板在第二表面之選擇性鈍化之後的示意性橫截面。 圖3C為圖3B之基板在於第一表面上選擇性沈積之後的示意性橫截面。 圖3D為圖3C之基板在自第二表面移除鈍化材料之後的示意性橫截面。 圖4之流程圖繪示根據各種具體例的用於鈍化及選擇性沈積之製程。 圖5之流程圖繪示根據一些具體例之鈍化及選擇性ALD。 圖6之流程圖繪示一種用於使基板之一些表面鈍化且在該基板之其他表面上方選擇性沈積的製程。 圖7之流程圖繪示一種用於在反應器製程腔室內使反應器表面針對後續於基板上沈積而鈍化的製程。 圖8之圖顯示在暴露於鈍化劑之後於不同類型之表面上用介電質進行各種數目之原子層沈積循環的實驗結果。 圖9之圖顯示在暴露於鈍化劑之後於不同類型之表面上用介電質進行各種數目之原子層沈積循環的實驗結果。
400:製程
410:鈍化步驟
420:選擇性沈積步驟
430:重複步驟

Claims (19)

  1. 一種用於氣相塗佈之方法,所述方法包含:使第一表面針對氣相沈積而鈍化,其中鈍化包含使所述第一表面暴露於包含鹵素的鈍化劑中以形成經鈍化之第一表面;以及藉由使所述經鈍化之第一表面及第二表面兩者暴露於氣相沈積反應物中而使介電層相對於所述經鈍化之第一表面選擇性地沈積在所述第二表面上,其中所述第二表面具有不同於所述第一表面的組成。
  2. 如請求項1所述的用於氣相塗佈之方法,其中所述介電層包括金屬氧化物。
  3. 如請求項1所述的用於氣相塗佈之方法,其中所述介電層包括選自由氧化鋯、氧化鉿及氧化鈦組成的群組的材料。
  4. 如請求項1所述的用於氣相塗佈之方法,其中所述介電層包括金屬氮化物。
  5. 如請求項1所述的用於氣相塗佈之方法,其中所述第二表面包括氧化物。
  6. 如請求項1所述的用於氣相塗佈之方法,其中所述第一表面包括金屬,且所述第二表面是非導電性表面。
  7. 如請求項1所述的用於氣相塗佈之方法,其中半導體基板包括所述第一表面及所述第二表面。
  8. 如請求項1所述的用於氣相塗佈之方法,其中所述第一表面是反應器表面。
  9. 如請求項1所述的用於氣相塗佈之方法,其中選擇性地沈積包括進行原子層沈積製程。
  10. 如請求項1所述的用於氣相塗佈之方法,其中選擇性地沈積包括供應水、氧、氨或臭氧。
  11. 一種用於氣相塗佈之方法,該方法包含:使第一表面針對氣相沈積而鈍化以形成經鈍化之第一表面,其中鈍化包含使所述第一表面暴露於包含鹵化物的鈍化劑中;以及藉由使所述經鈍化之第一表面及第二表面兩者暴露於氣相沈積反應物中而使介電層相對於所述經鈍化之第一表面選擇性地沈積在所述第二表面上,其中所述第二表面具有不同於所述第一表面的組成,且其中所述介電層包括選自由金屬氮化物、氧化鋯及氧化鉿組成的群組的材料。
  12. 如請求項11所述的用於氣相塗佈之方法,其中所述材料為金屬氮化物。
  13. 如請求項11所述的用於氣相塗佈之方法,其中所述材料為氧化鋯。
  14. 如請求項11所述的用於氣相塗佈之方法,其中所述材料為氧化鉿。
  15. 如請求項11所述的用於氣相塗佈之方法,其中所述經鈍化之第一表面包括疏水性封端或對所述氣相沈積反應物呈惰性的封端。
  16. 如請求項11所述的用於氣相塗佈之方法,其中鈍化在約2小時或少於2小時內執行。
  17. 如請求項11所述的用於氣相塗佈之方法,其中所述第二表面包括氧化物或氮化物表面。
  18. 如請求項11所述的用於氣相塗佈之方法,其中所述第一表面是導電性表面,且所述第二表面包括無機介電質。
  19. 如請求項11所述的用於氣相塗佈之方法,更包括重複所述鈍化及所述選擇性地沈積。
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