TWI796282B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI796282B TWI796282B TW105117129A TW105117129A TWI796282B TW I796282 B TWI796282 B TW I796282B TW 105117129 A TW105117129 A TW 105117129A TW 105117129 A TW105117129 A TW 105117129A TW I796282 B TWI796282 B TW I796282B
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Abstract
本發明提供一種半導體裝置和一種製造半導體裝置的方法。作為非限制實例,本發明的各種態樣提供一種半導體裝置及其製造方法,所述半導體裝置包括形成於加強層上的再分佈結構。
Description
本申請案參考2015年6月23日在韓國智慧財產權局申請的且標題為“半導體裝置”的第10-2015-0089245號韓國專利申請案,主張其優先權且主張其權益,所述專利申請案的內容在此以全文引用的方式併入本文中。
本發明涉及一種半導體裝置和一種製造半導體裝置的方法。
目前的半導體裝置和用於製造半導體裝置的方法不適當,例如,導致成本過量、可靠度降低或封裝大小過大。通過比較常規和傳統方法與如在本申請案的其餘部分中參考圖式闡述的本發明,所屬領域的技術人員將顯而易見此類方法的另外的局限性和缺點。
本發明的各種態樣提供一種半導體裝置和一種製造半導體裝置的方法。作為非限制實例,本發明的各種態樣提供一種半導體裝置及其製造方法,所述半導體裝置包括形成於加強層上的再分佈結構。
100‧‧‧半導體裝置
110‧‧‧插入件
111‧‧‧加強件
111’‧‧‧矽基板
111a‧‧‧溝槽
111b‧‧‧底部表面
111c‧‧‧側表面
112‧‧‧導電通孔
112’‧‧‧矽穿孔
112a‧‧‧絕緣層
112a’‧‧‧絕緣層
112b‧‧‧晶種層
112b’‧‧‧晶種層
112c’‧‧‧凹坑或凸起
113‧‧‧再分佈層
114‧‧‧再分佈圖案
114a‧‧‧再分佈晶種層圖案
115‧‧‧介電層
116‧‧‧微凸塊襯墊
116a‧‧‧襯墊晶種層
117‧‧‧凸塊下金屬
117a‧‧‧金屬晶種層
120‧‧‧半導體晶粒
121‧‧‧微凸塊
122‧‧‧焊料
130‧‧‧底膠
140‧‧‧囊封物
150‧‧‧導電凸塊
200‧‧‧半導體裝置
210‧‧‧電路板
211‧‧‧被動元件
212‧‧‧底膠
220‧‧‧覆蓋薄片
221‧‧‧黏合劑
222‧‧‧黏合劑
230‧‧‧導電球
240‧‧‧外部裝置
311‧‧‧加強件
311a‧‧‧雙溝槽
311b‧‧‧第一溝槽
311c‧‧‧第二溝槽
312‧‧‧導電通孔
312a‧‧‧絕緣層
312b‧‧‧晶種層
313‧‧‧再分佈層
314‧‧‧再分佈圖案
314a‧‧‧再分佈晶種層
315‧‧‧介電層
316‧‧‧微凸塊襯墊
316a‧‧‧襯墊晶種層
317‧‧‧導電柱
318‧‧‧焊料
圖1為根據本發明的實施例的半導體裝置的橫截面圖。
圖2A為說明使用鑲嵌工藝形成於加強件中的導電通孔的放大橫截面圖,且圖2B為說明使用等離子蝕刻工藝形成於基板上的矽穿孔的放大橫截面圖。
圖3為根據本發明的另一實施例的半導體裝置的橫截面圖。
圖4為根據本發明的再一實施例的半導體裝置的橫截面圖。
圖5A至5K為依序說明根據本發明的再一實施例的製造半導體裝置的方法的橫截面圖。
圖6A至6G為依序說明根據本發明的再一實施例的製造半導體裝置的方法的橫截面圖。
以下論述通過提供其實例來呈現本發明的各種態樣。此類實例是非限制性的,並且由此本發明的各種態樣的範圍應不必受所提供的實例的任何特定特徵限制。在以下論述中,短語“舉例來說”、“例如”和“示範性”是非限制性的且通常與“借助於實例而非限制”、“例如且非限制”等等同義。
如本文中所使用,“和/或”意指通過“和/或”聯結的列表中的項目中的任何一個或多個。作為一實例,“x和/或y”意指三元素集合{(x),(y),(x,y)}中的任一元素。換句話說,“x和/或y”意指“x和y中的一個或兩個”。作為另一實例,“x、y和/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任一元素。換句話說,“x、y和/或z”意指“x、y和z中的一個或多個”。
本文中所使用的術語僅出於描述特定實例的目的,且並不意
圖限制本發明。如本文中所使用,除非上下文另外明確指示,否則單數形式也意圖包含複數形式。將進一步理解,術語“包括(comprise、comprising)”、“包含(include、including)”、“具有(has、have、having)”等等當在本說明書中使用時,表示所陳述特徵、整體、步驟、操作、元件和/或構件的存在,但是不排除一或多個其它特徵、整體、步驟、操作、元件、構件和/或其群組的存在或添加。
應理解,儘管本文中可使用術語第一、第二等來描述各種元件,但這些元件不應受這些術語限制。這些術語僅用於將一個元件與另一元件區分開來。因此,例如,在不脫離本發明的教示的情況下,下文論述的第一元件、第一元件或第一部分可被稱為第二元件、第二元件或第二部分。類似地,例如“上部”、“以上”、“下部”、“以下”、“側”等各種空間術語可用於以相對方式將一個元件與另一元件區分開來。然而,應理解,元件可以不同方式定向,例如,在不脫離本發明的教示內容的情況下,半導體裝置可以側向轉動使得其“頂部”表面水準地朝向且其“側”表面垂直地朝向。
在圖式中,為了清楚起見可以放大層、區和/或元件的厚度或尺寸。因此,本發明的範圍應不受此類厚度或大小限制。另外,在圖式中,類似元件符號可在整個論述中指代類似元件。
還應理解,當元件A被提及為“連接到”或“耦合到”元件B時,元件A可以直接連接到元件B或間接連接到元件B(例如,插入元件C(和/或其它元件)可存在於元件A與元件B之間)。
本發明的各種態樣涉及一種半導體裝置及其製造方法。
通常,通過將半導體晶粒安裝在插入件上及將插入件堆疊在另一半導體晶粒或基板(例如,封裝基板等)上製造的半導體裝置在本文中可被稱作2.5D封裝。3D封裝通常通過在不使用插入件的情況下將一個半導體晶粒直接堆疊在另一半導體晶粒或基板上而獲得。
2.5D封裝的插入件可包含多個矽穿孔以允許電信號在上半導體晶粒與下半導體晶粒或基板之間流動。
本發明的各種態樣提供一種半導體裝置及其製造方法,其通過經由在加強件上形成的再分佈層(或結構)加強機械剛度而具有提高的可靠性。
根據本發明的一態樣,提供一種半導體裝置,所述半導體裝置包含:插入件,其包含具有導電通孔的加強件和連接到導電通孔的再分佈層(或結構);以及半導體晶粒,其連接到插入件的再分佈層(或結構)。
如本文中所描述,本發明的一個實施例提供一種半導體裝置,所述半導體裝置通過經由在加強件上形成的再分佈結構(或層)加強機械剛度而具有提高的可靠性。也就是說,根據本發明的各種態樣,再分佈層(或結構)形成於由具有高硬度和/或強度的材料(諸如,矽、玻璃或陶瓷)製成以相較常規插入件加強插入件的機械剛度的加強件上,由此便於在製造半導體裝置的過程中操作插入件以及提高完成的半導體裝置的機械可靠性。特別地,根據本發明的各種態樣,插入件的機械剛度得到加強,從而抑制凸塊下金屬與導電凸塊之間的介面分層。
本發明的另一實施例提供一種半導體裝置,其可通過使用相對較便宜的鑲嵌工藝形成導電通孔而非使用相對較貴的等離子蝕刻或雷射
鑽孔工藝形成矽穿孔來降低插入件的製造成本。也就是說,根據本發明的各種態樣,溝槽形成於加強件中,且導電層隨後填充於溝槽中,接著使用平坦化工藝或研磨工藝去除加強件的區域,由此完成電連接加強件的頂部表面和底部表面的導電通孔。因此,根據本發明的各種態樣,能夠與常規矽穿孔執行相同功能的導電通孔可在不使用相對較貴的等離子蝕刻或雷射鑽孔工藝的情況下以低成本製造。
本發明的再一實施例提供一種半導體裝置,所述半導體裝置通過使用鑲嵌工藝在插入件上形成導電柱包含具有細節距的導電柱。也就是說,根據本發明的各種態樣,溝槽形成於加強件中,且導電層隨後填充於溝槽中,接著使用平坦化或研磨工藝和蝕刻工藝去除加強件的預定區域,由此完成連接加強件的頂部表面和底部表面的導電通孔以及一體形成於導電通孔中的導電柱。因此,根據本發明的各種態樣,可以低成本形成具有細節距的導電柱。
下文中,將參看附圖詳細地描述本發明的實施例的實例使得其可由所屬領域的技術人員容易地製造和使用。
參看圖1,說明根據本發明的實施例的半導體裝置(100)的橫截面圖。
如圖1所示,根據本發明的實施例的半導體裝置100包含插入件110、半導體晶粒120、底膠130、囊封物140和導電凸塊150。
插入件110包含具有導電通孔112的加強件111、包含再分佈圖案114的再分佈層113(或再分佈結構)以及凸塊下金屬117。插入件110准許電信號在半導體晶粒120與電路板(或外部裝置)之間流動。
加強件111具有大體上平坦的頂部表面和與頂部表面相對的大體上平坦的底部表面,且可由選自由矽、玻璃、陶瓷和其等效物組成的群組中的一或多個製成。然而,本發明並不將加強件111的材料限於本文所揭示的那些材料。加強件111大體上提高了插入件110的機械剛度,由此提高半導體裝置100的可靠性。導電通孔112形成於加強件111中,且將形成於加強件111的頂部表面上的再分佈圖案114與形成於加強件111的底部表面上的凸塊下金屬117連接。導電通孔112通常由選自由銅、鋁、金、銀及合金及其等效物組成的群組中的一或多個製成,但本發明的各態樣並不限於此。
再分佈層113(或再分佈結構)通常形成於加強件111的頂部表面上,且包含再分佈圖案114(例如,一或多個導電層)、介電層115以及微凸塊襯墊116。再分佈圖案114電連接到導電通孔112,且必要時可由多個層形成。另外,介電層115覆蓋加強件111和再分佈圖案114,且必要時也可由多個層形成。微凸塊襯墊116連接到最頂部再分佈圖案114,但未由介電層115覆蓋以電連接到半導體晶粒120。此處,再分佈圖案114和微凸塊襯墊116可由選自由銅、鋁、金、銀和合金及其等效物組成的群組中的一或多個製成,但本發明的各態樣並不限於此。另外,介電層115可由選自由氧化矽、氮化矽、聚醯亞胺、苯並環丁烯、聚苯並噁唑及其等效物組成的群組中的一或多個製成,但本發明的各態樣並不限於此。
凸塊下金屬117形成於加強件111的底部表面上,且連接到導電通孔112。凸塊下金屬117可由選自由鉻、鎳、鈀、金、銀和合金及其等效物組成的群組的至少一個中的一或多個製成,但本發明的各態樣並不
限於此。凸塊下金屬117防止金屬間化合物形成於導電通孔112與導電凸塊150之間(例如,在其介面處),由此提高導電凸塊150的可靠性。
半導體晶粒120電連接到再分佈層113(或再分佈結構)。為此目的,半導體晶粒120包含諸如Cu柱或Cu立柱的微凸塊121(例如,晶粒互連結構),且可電連接到通過焊料122設置於再分佈層113(或再分佈結構)的微凸塊襯墊116中。另外,半導體晶粒120可包含(例如)電路,例如數位訊號處理器(digital signal procesor,DSP)、微處理器、網路處理器、功率管理處理器、音訊處理器、RF電路、無線基帶系統單晶片(system-on-chip,SoC)處理器、感測器或特定應用積體電路(application-specific integrated circuit,ASIC)。
底膠130插入半導體晶粒120與插入件110之間,且允許半導體晶粒120以更安全的方式機械連接到插入件110。此處,底膠130包圍微凸塊121和焊料122。特別地,底膠130防止半導體晶粒120與插入件110之間的分層,由此防止其由於半導體晶粒120與插入件110之間的熱膨脹係數的差異而彼此電分離。在一些情況下,可不設置底膠130。
囊封物140將位於插入件110的頂部表面上的半導體晶粒120進行囊封。也就是說,囊封物140包圍底膠130和半導體晶粒120,由此安全地保護底膠130和半導體晶粒120免受外部環境。在一些情況下,囊封物140可能不覆蓋半導體晶粒120的頂部表面,以使半導體晶粒120的頂部表面直接暴露於外部,由此提高半導體晶粒120的散熱效率。在其它實例實施中,囊封物140可覆蓋半導體晶粒120的頂部表面。
同時,當形成囊封物140的無機填充劑的直徑小於半導體晶
粒120與插入件110之間的間隙尺寸時,(例如)可不使用底膠130。舉例來說,當使用小於間隙尺寸的成型底膠(mold underfill,MUF)時,兩個工藝步驟(底部填充和囊封)可減少為一個工藝步驟(囊封)。
導電凸塊150可連接到形成於插入件110的底部表面上的凸塊下金屬117或直接連接到導電通孔112。導電凸塊150可由選自由共晶焊料(Sn37Pb)、高鉛焊料(Sn95Pb)、無鉛焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu或SnAgBi)及其等效物組成的群組中的一個製成,但本實施例的各態樣並不限於此。
如上文所描述,根據本發明的實施例的半導體裝置100提供具有形成於加強件111上的再分佈層113(或再分佈結構)的插入件110,由此提高插入件110的機械剛度。也就是說,根據本發明的半導體裝置100包含具有再分佈層113(或再分佈結構)的插入件110,所述再分佈層(或再分佈結構)形成於由具有高硬度和/或強度的材料(諸如,矽、玻璃或陶瓷等)製成以相較常規插入件加強插入件110的機械剛度的加強件111上,由此便於在製造半導體裝置100的過程中操作插入件110以及提高完成的半導體裝置100的機械可靠性。特別地,根據本發明的各種態樣,插入件110的機械剛度得以加強,由此有效地抑制凸塊下金屬117與導電凸塊150之間的介面分層。
參看圖2A,說明了說明使用鑲嵌工藝形成於加強件(111)中的導電通孔(112)的放大橫截面圖,且參看圖2B,說明了說明使用等離子蝕刻工藝形成於矽基板(111')上的矽穿孔(112')的放大橫截面圖。
如圖2A所說明,使用鑲嵌工藝形成穿過加強件111的頂部
表面和底部表面的導電通孔112,且導電通孔112的橫截面形狀大體為倒置梯形。實際上,導電通孔112(例如,遠離導電凸塊150的導電通孔112的末端)的頂部表面直徑稍大於導電通孔112(例如,朝向導電凸塊150的導電通孔112的末端)的底部表面直徑。另外,面向彼此的導電通孔112的側表面為大體上平坦的傾斜表面。應注意,導電通孔112可(例如)為截錐形。
然而,如圖2B所說明,使用等離子蝕刻工藝形成於矽基板111'(或其它加強件材料)上的矽穿孔112'的橫截面具有大體上矩形形狀。也就是說,矽穿孔112'的頂部表面直徑與矽穿孔112'的底部表面直徑大體上相同。另外,由於工藝特徵,多個凹坑(或凸起特徵)112c'形成於矽穿孔112'的相對側表面上。也就是說,矽穿孔112'的相對側表面可能(例如)不是平坦表面,而可能是具有多個凹坑或凸起112c'的粗糙表面。應注意,導電通孔112'可(例如)為圓柱形。
另外,雖然使用鑲嵌工藝形成於加強件111上的導電通孔112的縱橫比在約1:1至約1:2的範圍內,但使用等離子蝕刻工藝形成於矽基板111'上的矽穿孔112'的縱橫比在約1:10至約1:15的範圍內。因此,根據本發明的導電通孔112的電路徑遠短於常規矽穿孔112'的電路徑。另外,使用鑲嵌工藝形成於加強件111上的導電通孔112的直徑可在約10μm至約20μm的範圍內。然而,使用等離子蝕刻工藝形成於矽基板111'上的矽穿孔112'的直徑遠大於20μm。
另外,絕緣層112a和晶種層112b可進一步插入於加強件111與導電通孔112之間。當加強件111由矽製成時,絕緣層112a可為無機層
(諸如氧化矽層或氮化矽層),但本發明的各態樣並不限於此。同時,當加強件111由玻璃或陶瓷製成時,絕緣層112a可為有機層(諸如聚醯亞胺、苯並環丁烯或聚苯並噁唑),但本發明的各態樣並不限於此。另外,晶種層112b可大體上由選自由鈦/銅、鈦鎢/銅及合金及其等效物組成的群組中的一個製成,但本發明的各態樣並不限於此。
同時,絕緣層112a'和晶種層112b'還可進一步插入在矽基板111'與矽穿孔112'之間。在此情況下,由於工藝特徵,多個凹坑(或凸起特徵)112c'仍可保留在絕緣層112a'和晶種層112b'上。
也就是說,根據本發明,凹坑或凸起由於工藝特徵並未形成於導電通孔112中,而凹坑(或凸起特徵)由於常規工藝特徵仍保留在矽穿孔112'上。
參看圖3,說明根據本發明的另一實施例的半導體裝置200的橫截面圖。如圖3中所說明,根據本發明的另一實施例的半導體裝置200可進一步包含電路板210、覆蓋薄片220以及導電球230。
也就是說,半導體裝置100通過導電凸塊150電連接到電路板210。必要時,各種被動元件211可進一步安裝在電路板210上。此外,底膠212在必要時可插入於半導體裝置100與電路板210之間。另外,覆蓋薄片220覆蓋半導體裝置100和安裝在電路板210上的被動元件211,由此保護半導體裝置100和被動元件211免受外部環境。另外,導電球230電連接到電路板210,且安裝在外部裝置(例如,主機板或主機板)上。此處,覆蓋薄片220可使用黏合劑221黏附到電路板210,及/或可使用黏合劑222(例如,導熱膠等)黏附到半導體裝置100。
參看圖4,說明根據本發明的再一實施例的半導體裝置100的橫截面圖。
如圖4中所說明,根據本發明的再一實施例的半導體裝置100可直接安裝在外部裝置240(諸如主機板或主機板)上,而非電路板210上。
參看圖5A至圖5K,說明了連續說明根據本發明的再一實施例的製造半導體裝置100的方法的橫截面圖。
如圖5中所說明,具有預定深度的溝槽111a形成於加強件111中。由於溝槽111a通常為使用相對較便宜的蝕刻工藝形成,因此溝槽111a的橫截面的形狀大體上為倒置梯形。也就是說,溝槽111a的橫截面具有底部表面111b和相對側表面111c。此處,底部表面111b在大體上水準方向可為平坦的,且相對側表面111c可為大體上垂直的傾斜平坦表面。換句話說,溝槽111a被配置成在其深度增加時具有較小直徑。溝槽111a的橫截面歸因於在蝕刻工藝期間產生的各向異性蝕刻特徵。
如圖5B中所說明,絕緣層112a和晶種層112b連續形成於溝槽111a和溝槽111a的外部區域中。此處,當加強件111由矽製成時,絕緣層112a可為無機層(諸如氧化矽層或氮化矽層),但本發明的各態樣並不限於此。同時,當加強件111由玻璃或陶瓷製成時,絕緣層112a可為有機層(諸如聚醯亞胺、苯並環丁烯或聚苯並噁唑),但本發明的各態樣並不限於此。
在示範性實施例中,諸如氧化矽層或氮化矽層的無機層可通過將氧氣和/或氮氣供應至約900℃或更高的大氣中的矽而形成為具有預定
厚度,但本發明的各態樣並不限於此。
在另一示範性實施例中,諸如聚醯亞胺層的有機層可通過旋塗、噴塗、浸塗或棒塗形成,但本發明的各態樣並不限於此。
同時,晶種層112b可由鈦/銅、鈦鎢/銅等製成,但本發明的範圍並不限於此。晶種層112b可通過(例如)無電極電鍍、電解電鍍和/或濺鍍形成,但本發明的各態樣並不限於此。
如圖5C中所說明,具有預定厚度的導電層1120可形成於具有形成於其中的絕緣層112a和晶種層112b的溝槽111a和溝槽111a的外部區域中。導電層1120可由銅、鋁、金或銀製成,但本發明的各態樣並不限於此。同時,導電層1120可通過(例如)無電電鍍、電解電鍍和/或濺鍍形成,但本發明的各態樣並不限於此。
如圖5D中所說明,形成於溝槽111a和溝槽111a的外部區域中的導電層1120的預定部分可通過(例如)平面化工藝或化學機械拋光(CMP)工藝去除。在示範性實施例中,形成於位於加強件111的上側的溝槽111a的外部區域中的導電層1120得以完全去除,以使得導電層1120可僅保留在溝槽111a內。在下文中,導電層1120將被稱作導電通孔112。
如圖5E中所說明,再分佈圖案114的一層或多層(例如,導電層)和介電層115形成於加強件111上,且微凸塊襯墊116形成於最頂部再分佈圖案114上,由此完成再分佈層113(或再分佈結構)。也就是說,再分佈晶種層圖案114a形成為連接到加強件111的導電通孔112,再分佈圖案114形成於再分佈晶種層圖案114a上,且再分佈圖案114使用介電層115加工。另外,襯墊晶種層116a形成於最頂部再分佈圖案114上,且微
凸塊襯墊116隨後形成於襯墊晶種層116a上。此處,微凸塊襯墊116並未由介電層115覆蓋,但暴露於外部以在後續工藝步驟中電連接到半導體晶粒120。
此處,再分佈晶種層圖案114a和襯墊晶種層116a可使用無電電鍍、電解電鍍或濺鍍的一般工藝由鈦/銅、鈦鎢/銅等製成,但本發明的範圍不限於此類材料和/或此類工藝。另外,再分佈層113(或再分佈結構)和微凸塊襯墊116可使用無電電鍍、電解電鍍或濺鍍和/或光微影由銅、鋁、金或銀製成,但本發明的範圍不限於此類材料和/或此類工藝。另外,介電層115可使用旋塗、噴塗、浸塗或棒塗由聚醯亞胺、苯並環丁烯或聚苯並噁唑製成,但本發明的範圍不限於此類材料和/或此類工藝。
如圖5F中所說明,使用平面化工藝或CMP工藝去除加強件111中的溝槽111a的下部區域,但本發明的範圍不限於此。因此,形成於溝槽111a中的導電通孔112的底部表面暴露於外部。同時,還可去除形成於導電通孔112的底部表面上的絕緣層112a和晶種層112b。也就是說,平面化工藝或CMP工藝可允許導電通孔112(例如,銅的底部表面)直接暴露於較下端。此處,加強件111的底部表面和導電通孔112的底部表面為共面的(或共面定位)。
如圖5G中所說明,凸塊下金屬117形成於通過加強件111的底部表面暴露的導電通孔112中。也就是說,金屬晶種層117a形成於導電通孔112的底部表面上,且凸塊下金屬117隨後形成於金屬晶種層117a上。金屬晶種層117a可使用無電電鍍、電解電鍍或濺鍍的一般工藝由鈦/銅、鈦鎢/銅等製成,但本發明的範圍不限於此類材料和/或此類工藝。另外,
凸塊下金屬117可由選自由鉻、鎳、鈀、金、銀及合金及其等效物組成的群組中的至少一個製成,但本發明的各態樣並不限於此。另外,凸塊下金屬117還可使用無電電鍍、電解電鍍和/或濺鍍的一般工藝形成,但本發明的範圍不限於此。凸塊下金屬117防止金屬間化合物形成於導電通孔112與下文描述的導電凸塊150之間(例如,在其介面處),由此提高導電凸塊150的板層級可靠性。另外,必要時,介電層115可進一步形成於凸塊下金屬117與加強件111之間。在一些情況下,可不提供凸塊下金屬117。
以此方式,完成包含具有導電通孔112的加強件111和包含再分佈圖案114、介電層115、微凸塊襯墊116和凸塊下金屬117的再分佈層113(或再分佈結構)的插入件110。
如圖5H中所說明,至少一個半導體晶粒120電連接到插入件110。在示範性實施例中,半導體晶粒120可通過微凸塊121和焊料122電連接到插入件110的微凸塊襯墊116。在示範性實施例中,揮發性助熔劑被打點(dot)於插入件110的微凸塊襯墊116上,且具有微凸塊121的半導體晶粒120在其上對準。在其之後,如果施加在約150℃至約250℃的範圍內的溫度,那麼當形成於微凸塊121的底端的焊料122熔化時,微凸塊121與微凸塊襯墊116稠合。隨後,所得產物經受冷卻工藝以允許形成於微凸塊121的底端的焊料122固化,由此完成將半導體晶粒120以電子和機械方式連接到插入件110。替代地,將半導體晶粒120連接到插入件110的方法可以各種方式實施。
如圖5I中所說明,底膠130填充於半導體晶粒120與插入件110之間的間隙或空間中。例如,分配器中含有的底膠130分配到半導體
晶粒120與插入件110之間的間隙,隨後進行固化,由此通過底膠130將半導體晶粒120和插入件110以機械方式彼此連接。
在一些情況下,可不執行底膠130的填充。
如圖5J中所說明,形成於插入件110的頂部表面上的半導體晶粒120和底膠130由囊封物140囊封。此處,半導體晶粒120的頂部表面可通過囊封物140暴露於外部。囊封物140可(例如)包圍底膠130(如果形成的話)。又例如,囊封物140的一部分可底部填充半導體晶粒120作為成型底膠。
如圖5K中所說明,導電凸塊150連接到形成於插入件110的底部表面上的凸塊下金屬117。在示範性實施例中,揮發性助熔劑被打點於凸塊下金屬117上,且導電凸塊150臨時定位於其上。在其之後,如果施加在約150℃至約250℃的範圍內的溫度,那麼導電凸塊150熔化且與凸塊下金屬117稠合。隨後,所得產物經受冷卻工藝以允許導電凸塊150固化,由此完成將導電凸塊150以電子和機械方式連接到插入件110。另外,可採用各種方法將半導體晶粒120連接到插入件110。
此處,可以各種方式執行將導電凸塊150連接到插入件110的方法。
另外,可基於單元、面板、條帶、晶粒或矩陣執行前述工藝。當基於面板、條帶、晶粒或矩陣執行所述工藝時,可接著進行鋸割工藝。也就是說,單獨的半導體裝置100通過鋸割或衝壓(punching)工藝從面板、條帶、晶粒或矩陣單體化。
如上文所描述,根據本發明,使用相對較便宜的鑲嵌工藝形
成導電通孔112,而非使用相對較貴的等離子蝕刻工藝或雷射鑽孔藝形成的矽穿孔,由此提供以低成本形成的包含插入件110的半導體裝置100。也就是說,根據本發明,溝槽111a形成於加強件111中,且導電層1120隨後形成於溝槽111a中,接著使用平坦化工藝或研磨工藝去除加強件111的區域,由此完成電連接加強件111的頂部表面和底部表面的導電通孔112。因此,根據本發明,能夠與常規矽穿孔執行相同功能的導電通孔112可在不使用相對較貴的等離子蝕刻或雷射鑽孔工藝的情況下以低成本製造。
參看圖6A至圖6G,說明了連續說明根據本發明的再一實施例的製造半導體裝置的方法的橫截面圖。此處,由於形成於再分佈層(或再分佈結構)上的半導體晶粒、底膠和囊封物與先前實施例的半導體晶粒、底膠和囊封物相同,因此將不給出其重複描述。
如圖6A中所說明,具有預定深度的雙溝槽311a形成於加強件311中。也就是說,相對較深較窄的第一溝槽311b形成於加強件311中,且相對較淺較寬的第二溝槽311c形成於第一溝槽311b中。由於雙溝槽311a通過一般光微影工藝形成,因此雙溝槽311a的橫截面形狀可為兩個倒置梯形。
如圖6B中所說明,絕緣層312a和晶種層312b連續形成於雙溝槽311a和雙溝槽311a的外部區域中。此處,當加強件311由矽製成時,絕緣層312a可為無機層(諸如氧化矽層或氮化矽層),但本發明的範圍不限於此。當加強件311由玻璃或陶瓷製成時,絕緣層312a可為有機層(諸如聚醯亞胺、苯並環丁烯或聚苯並噁唑),但本發明的範圍不限於此。
如圖6C中所說明,具有預定厚度的導電層3120可形成於具
有形成於其中的絕緣層312a和晶種層312b的雙溝槽311a和雙溝槽311a的外部區域中。
如圖6D中所說明,形成於雙溝槽311a和雙溝槽311a的外部區域中的導電層3120的預定厚度的預定部分可通過平面化工藝或化學機械拋光(CMP)工藝去除,但本發明的範圍不限於此。在示範性實施例中,形成於位於加強件311的上側的雙溝槽311a的外部區域中的導電層3120得以完全去除,以使得導電層3120可僅保留在雙溝槽311a內。此處,填充於第一溝槽311b中的導電層3120可在後一工藝中轉變為導電柱317,且填充於第二溝槽311c中的導電層3120可在後一工藝中轉變為導電通孔312。在下文中,導電層3120將被稱作導電柱317和導電通孔312。
如圖6E中所說明,再分佈圖案314的一層或多層(例如,導電層)和介電層315可形成於加強件311上,且微凸塊襯墊316形成於最頂部再分佈圖案314上,由此完成再分佈層313(或再分佈結構)。也就是說,再分佈晶種層314a形成為連接到加強件311的導電通孔312,再分佈圖案314形成於再分佈晶種層314a上,且再分佈圖案314由介電層315覆蓋。另外,襯墊晶種層316a形成於最頂部再分佈圖案314上,且微凸塊襯墊316隨後形成於襯墊晶種層316a上。
如圖6F中所說明,形成於加強件311中的第一溝槽311b的下部區域可通過平面化工藝或化學機械拋光(CMP)工藝去除。另外,形成於加強件311中的第一溝槽311b的外部區域(即,導電柱317的外部區域)得以去除,由此提供配置成自導電通孔312向下延伸一預定長度的導電柱317。例如,在加強件311由矽製成的實例實施中,矽蝕刻工藝可用於
減小加強件311的厚度,以使得導電柱317(例如,整個柱317或其一部分)自加強件311的底側突出。應注意,導電通孔312的底側此時可與加強件311共面,此時可自加強件311突出,或此時可由加強件311覆蓋。在實例實施例中,導電通孔312被配置成定位於加強件311內,且導電柱317被配置成自加強件311向下延伸一預定長度。
如圖6G中所說明,位於導電柱317的底部表面上的絕緣層312a被去除,由此將焊料318電連接到導電柱317的底部表面。位於導電柱317的底部表面上的晶種層312b必要時可保留或可去除。
另外,可在將半導體晶粒附接到插入件310及將底膠和囊封物應用於所得產物後形成焊料318。另外,由於半導體晶粒、底膠和囊封物與先前實施例的半導體晶粒、底膠和囊封物相同,因此將不給出形成工藝步驟和其配置的重複描述。
如上文所描述,根據本發明,可通過使用鑲嵌工藝在插入件310上形成導電柱317來形成具有細節距的導電柱317。也就是說,雙溝槽311a形成於加強件311中,導電層3120填充於雙溝槽311a中,且加強件311的預定區域通過平面化或研磨工藝和蝕刻工藝來去除,由此實現連接加強件311的頂部表面和底部表面的導電通孔312以及一體形成於導電通孔312中的導電柱317。因此,根據本發明,可以低成本形成具有細節距的導電柱317。
本文中的論述包含展示電子裝置組合件的各個部分及其製造方法的眾多說明性圖。為了清楚地示意,這些圖並未示出每個實例組合件的所有方面。本文中提供的任何實例組合件和/或方法可以與本文中提供
的任何或全部其它組合件和/或方法共用任何或全部特徵。
綜上所述,本發明的各種態樣提供一種半導體裝置和一種製造半導體裝置的方法。作為非限制實例,本發明的各種態樣提供一種半導體裝置及其製造方法,所述半導體裝置包括形成於加強層上的再分佈結構。雖然已經參考某些態樣和實例描述了以上內容,但是所屬領域的技術人員應理解,在不脫離本發明的範圍的情況下,可以進行各種修改並可以替代等效物。另外,在不脫離本發明的範圍的情況下,可以進行許多修改以使特定情況或材料適應本發明的教示。因此,希望本發明不限於所公開的特定實例,而是本發明將包含落入所附申請專利範圍的範疇內的所有實例。
100‧‧‧半導體裝置
110‧‧‧插入件
111‧‧‧加強件
112‧‧‧導電通孔
113‧‧‧再分佈層
114‧‧‧再分佈圖案
115‧‧‧介電層
116‧‧‧微凸塊襯墊
117‧‧‧凸塊下金屬
120‧‧‧半導體晶粒
121‧‧‧微凸塊
122‧‧‧焊料
130‧‧‧底膠
140‧‧‧囊封物
150‧‧‧導電凸塊
Claims (18)
- 一種半導體裝置,其包括:插入件,其包括:加強件層,其包括頂部加強件表面、底部加強件表面和導電通孔,所述導電通孔從所述頂部加強件表面延伸到所述底部加強件表面,其中所述導電通孔包括頂部通孔表面以及非垂直且非水平的傾斜側壁,所述頂部通孔表面與所述頂部加強件表面共面;及再分佈結構,其包括:頂部再分佈結構側;以及底部再分佈結構側,所述底部再分佈結構側包括:最下再分佈結構介電層,其包括附接至所述頂部加強件表面的最下底部表面;以及最下再分佈結構導電層,其包括附接至所述頂部通孔表面附接的底部表面;以及半導體晶粒,其連接到所述頂部再分佈結構側,其中所述導電通孔的所述頂部通孔表面具有比所述導電通孔的底部通孔表面還大的直徑。
- 根據申請專利範圍第1項所述的半導體裝置,其中所述加強件層包括玻璃層和/或陶瓷層。
- 根據申請專利範圍第1項所述的半導體裝置,其中:所述加強件層包括矽;以及所述再分佈結構包括直接接觸所述頂部加強件表面之有機介電層。
- 根據申請專利範圍第1項所述的半導體裝置,其進一步包括在所述 加強件層和所述導電通孔之間的絕緣層。
- 根據申請專利範圍第1項所述的半導體裝置,其包括在所述導電通孔與所述加強件層之間的晶種層和絕緣層。
- 根據申請專利範圍第1項所述的半導體裝置,其進一步包括耦合到所述導電通孔的底部通孔端的導電凸塊。
- 根據申請專利範圍第6項所述的半導體裝置,其進一步包括在所述導電通孔與所述導電凸塊之間的凸塊下金屬。
- 根據申請專利範圍第1項所述的半導體裝置,其進一步包括:第二半導體晶粒,其連接至所述頂部再分佈結構側;以及囊封物材料,其覆蓋所述半導體晶粒的橫向側和所述第二半導體晶粒的橫向側,但是不覆蓋所述半導體晶粒的頂側和所述第二半導體晶粒的頂側。
- 根據申請專利範圍第1項所述的半導體裝置,其中所述導電通孔具有倒置梯形的橫截面,並且所述頂部通孔表面是在所述倒置梯形的橫截面的頂端。
- 一種半導體裝置,其包括:插入件,其包括:加強件層,其包括頂部加強件表面、底部加強件表面和導電通孔,所述導電通孔從所述頂部加強件表面延伸到所述底部加強件表面;再分佈結構,其包括頂部再分佈結構表面和附接到所述頂部加強件表面的最下底部再分佈結構表面;以及絕緣層,其中: 所述絕緣層橫向包圍所述導電通孔且藉由所述加強件層橫向包圍;以及所述絕緣層的頂部表面與所述頂部加強件表面共面;以及半導體晶粒,其連接到所述頂部再分佈結構表面。
- 根據申請專利範圍第10項所述的半導體裝置,其中:所述導電通孔的最小寬度是在所述導電通孔的最下端處;以及所述導電通孔包括非垂直且非水平的傾斜側壁。
- 根據申請專利範圍第11項所述的半導體裝置,其中所述導電通孔具有倒置梯形的橫截面,其中頂部通孔端比底部通孔端更寬。
- 根據申請專利範圍第12項所述的半導體裝置,其中所述導電通孔具有與所述頂部加強件表面共面的頂部通孔端以及與所述底部加強件表面共面的底部通孔端。
- 根據申請專利範圍第10項所述的半導體裝置,其中所述導電通孔的側面包括凹坑。
- 根據申請專利範圍第10項所述的半導體裝置,其包括耦合到所述導電通孔的底部通孔端的導電凸塊。
- 根據申請專利範圍第10項所述的半導體裝置,其中所述導電通孔包括晶種層,其中:所述晶種層藉由所述絕緣層橫向包圍在所述導電通孔與所述加強件層之間;以及所述晶種層的頂部表面和所述頂部加強件表面共面。
- 一種製造半導體裝置的方法,所述方法包括: 提供插入件,所述插入件包括:加強件層,其包括頂部加強件表面、底部加強件表面和導電通孔,所述導電通孔從所述頂部加強件表面延伸到所述底部加強件表面,其中所述導電通孔包括頂部通孔表面以及非垂直且非水平的傾斜側壁,所述頂部通孔表面與所述頂部加強件表面共面;及再分佈結構,其包括頂部再分佈結構側和底部再分佈結構側,所述底部再分佈結構側包括:最下再分佈結構介電層,其包括附接至所述頂部加強件表面的最下底部表面;以及最下再分佈結構導電層,其包括附接至所述頂部通孔表面的底部表面;以及將半導體晶粒連接到所述頂部再分佈結構側,其中所述導電通孔的所述頂部通孔表面具有比所述導電通孔的底部通孔表面還大的直徑。
- 根據申請專利範圍第17項所述的方法,其進一步包括絕緣層,其中:所述絕緣層橫向包圍所述導電通孔且藉由所述加強件層橫向包圍;以及所述絕緣層的頂部表面和所述頂部加強件表面共面。
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CN206040615U (zh) | 2017-03-22 |
CN106298684B (zh) | 2022-03-29 |
KR101672640B1 (ko) | 2016-11-03 |
CN106298684A (zh) | 2017-01-04 |
CN114823544A (zh) | 2022-07-29 |
US20160379915A1 (en) | 2016-12-29 |
TW202324643A (zh) | 2023-06-16 |
TW201701431A (zh) | 2017-01-01 |
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