CN106298684A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
半导体装置。本发明提供一种半导体装置和一种制造半导体装置的方法。作为非限制实例,本发明的各种方面提供一种半导体装置及其制造方法,所述半导体装置包括形成于加强层上的再分布结构。
Description
相关申请案的交叉参考/通过引用方式并入
本申请案参考2015年6月23日在韩国知识产权局申请的且标题为“SEMICONDUCTORDEVICE”的第10-2015-0089245号韩国专利申请案,主张其优先权且主张其权益,所述专利申请案的内容在此以全文引用的方式并入本文中。
技术领域
本发明涉及一种半导体装置和一种制造半导体装置的方法。
背景技术
目前的半导体装置和用于制造半导体装置的方法不适当,例如,导致成本过量、可靠度降低或封装大小过大。通过比较常规和传统方法与在本申请案的其余部分中参考图式阐述的本发明,所属领域的技术人员将显而易见此类方法的另外的局限性和缺点。
发明内容
本发明的各种方面提供一种半导体装置和一种制造半导体装置的方法。作为非限制实例,本发明的各种方面提供一种半导体装置及其制造方法,所述半导体装置包括形成于加强层上的再分布结构。
附图说明
图1为根据本发明的实施例的半导体装置的横截面图。
图2A为说明使用镶嵌工艺形成于加强件中的导电通孔的放大横截面图,且图2B为说明使用等离子蚀刻工艺形成于衬底上的硅穿孔的放大横截面图。
图3为根据本发明的另一实施例的半导体装置的横截面图。
图4为根据本发明的再一实施例的半导体装置的横截面图。
图5A至5K为依序说明根据本发明的再一实施例的制造半导体装置的方法的横截面图。
图6A至6G为依序说明根据本发明的再一实施例的制造半导体装置的方法的横截面图。
具体实施方式
以下论述通过提供其实例来呈现本发明的各种方面。此类实例是非限制性的,并且由此本发明的各种方面的范围应不必受所提供的实例的任何特定特征限制。在以下论述中,短语“举例来说”、“例如”和“示范性”是非限制性的且通常与“借助于实例而非限制”、“例如且非限制”等等同义。
如本文中所使用,“和/或”意指通过“和/或”联结的列表中的项目中的任何一个或多个。作为一实例,“x和/或y”意指三元素集合{(x),(y),(x,y)}中的任一元素。换句话说,“x和/或y”意指“x和y中的一个或两个”。作为另一实例,“x、y和/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任一元素。换句话说,“x、y和/或z”意指“x、y和z中的一个或多个”。
本文中所使用的术语仅出于描述特定实例的目的,且并不意图限制本发明。如本文中所使用,除非上下文另外明确指示,否则单数形式也意图包含复数形式。将进一步理解,术语“包括(comprise、comprising)”、“包含(include、including)”、“具有(has、have、having)”等等当在本说明书中使用时,表示所陈述特征、整体、步骤、操作、元件和/或组件的存在,但是不排除一或多个其它特征、整体、步骤、操作、元件、组件和/或其群组的存在或添加。
应理解,尽管本文中可使用术语第一、第二等来描述各种元件,但这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件区分开来。因此,例如,在不脱离本发明的教示的情况下,下文论述的第一元件、第一组件或第一部分可被称为第二元件、第二组件或第二部分。类似地,例如“上部”、“以上”、“下部”、“以下”、“侧”等各种空间术语可用于以相对方式将一个元件与另一元件区分开来。然而,应理解,组件可以不同方式定向,例如,在不脱离本发明的教示内容的情况下,半导体装置可以侧向转动使得其“顶部”表面水平地朝向且其“侧”表面垂直地朝向。
在图式中,为了清楚起见可以放大层、区和/或组件的厚度或尺寸。因此,本发明的范围应不受此类厚度或大小限制。另外,在图式中,类似参考标号可在整个论述中指代类似元件。
还应理解,当元件A被提及为“连接到”或“耦合到”元件B时,元件A可以直接连接到元件B或间接连接到元件B(例如,插入元件C(和/或其它元件)可存在于元件A与元件B之间)。
本发明的各种方面涉及一种半导体装置及其制造方法。
通常,通过将半导体裸片安装在插入件上及将插入件堆叠在另一半导体裸片或衬底(例如,封装衬底等)上制造的半导体装置在本文中可被称作2.5D封装。3D封装通常通过在不使用插入件的情况下将一个半导体裸片直接堆叠在另一半导体裸片或衬底上而获得。
2.5D封装的插入件可包含多个硅穿孔以允许电信号在上半导体裸片与下半导体裸片或衬底之间流动。
本发明的各种方面提供一种半导体装置及其制造方法,其通过经由在加强件上形成的再分布层(或结构)加强机械刚度而具有提高的可靠性。
根据本发明的一方面,提供一种半导体装置,所述半导体装置包含:插入件,其包含具有导电通孔的加强件和连接到导电通孔的再分布层(或结构);以及半导体裸片,其连接到插入件的再分布层(或结构)。
如本文中所描述,本发明的一个实施例提供一种半导体装置,所述半导体装置通过经由在加强件上形成的再分布结构(或层)加强机械刚度而具有提高的可靠性。也就是说,根据本发明的各种方面,再分布层(或结构)形成于由具有高硬度和/或强度的材料(诸如,硅、玻璃或陶瓷)制成以相较常规插入件加强插入件的机械刚度的加强件上,由此便于在制造半导体装置的过程中操作插入件以及提高完成的半导体装置的机械可靠性。特别地,根据本发明的各种方面,插入件的机械刚度得到加强,从而抑制凸块下金属与导电凸块之间的界面分层。
本发明的另一实施例提供一种半导体装置,其可通过使用相对较便宜的镶嵌工艺形成导电通孔而非使用相对较贵的等离子蚀刻或激光钻孔工艺形成硅穿孔来降低插入件的制造成本。也就是说,根据本发明的各种方面,沟槽形成于加强件中,且导电层随后填充于沟槽中,接着使用平坦化工艺或研磨工艺去除加强件的区域,由此完成电连接加强件的顶部表面和底部表面的导电通孔。因此,根据本发明的各种方面,能够与常规硅穿孔执行相同功能的导电通孔可在不使用相对较贵的等离子蚀刻或激光钻孔工艺的情况下以低成本制造。
本发明的再一实施例提供一种半导体装置,所述半导体装置通过使用镶嵌工艺在插入件上形成导电柱包含具有细节距的导电柱。也就是说,根据本发明的各种方面,沟槽形成于加强件中,且导电层随后填充于沟槽中,接着使用平坦化或研磨工艺和蚀刻工艺去除加强件的预定区域,由此完成连接加强件的顶部表面和底部表面的导电通孔以及一体形成于导电通孔中的导电柱。因此,根据本发明的各种方面,可以低成本形成具有细节距的导电柱。
下文中,将参看附图详细地描述本发明的实施例的实例使得其可由所属领域的技术人员容易地制造和使用。
参看图1,说明根据本发明的实施例的半导体装置(100)的横截面图。
如图1所示,根据本发明的实施例的半导体装置100包含插入件110、半导体裸片120、底胶130、包封物140和导电凸块150。
插入件110包含具有导电通孔112的加强件111、包含再分布图案114的再分布层113(或再分布结构)以及凸块下金属117。插入件110准许电信号在半导体裸片120与电路板(或外部装置)之间流动。
加强件111具有大体上平坦的顶部表面和与顶部表面相对的大体上平坦的底部表面,且可由选自由硅、玻璃、陶瓷和其等效物组成的群组中的一或多个制成。然而,本发明并不将加强件111的材料限于本文所揭示的那些材料。加强件111大体上提高了插入件110的机械刚度,由此提高半导体装置100的可靠性。导电通孔112形成于加强件111中,且将形成于加强件111的顶部表面上的再分布图案114与形成于加强件111的底部表面上的凸块下金属117连接。导电通孔112通常由选自由铜、铝、金、银及合金及其等效物组成的群组中的一或多个制成,但本发明的各方面并不限于此。
再分布层113(或再分布结构)通常形成于加强件111的顶部表面上,且包含再分布图案114(例如,一或多个导电层)、介电层115以及微凸块衬垫116。再分布图案114电连接到导电通孔112,且必要时可由多个层形成。另外,介电层115覆盖加强件111和再分布图案114,且必要时也可由多个层形成。微凸块衬垫116连接到最顶部再分布图案114,但未由介电层115覆盖以电连接到半导体裸片120。此处,再分布图案114和微凸块衬垫116可由选自由铜、铝、金、银和合金及其等效物组成的群组中的一或多个制成,但本发明的各方面并不限于此。另外,介电层115可由选自由氧化硅、氮化硅、聚酰亚胺、苯并环丁烯、聚苯并噁唑及其等效物组成的群组中的一或多个制成,但本发明的各方面并不限于此。
凸块下金属117形成于加强件111的底部表面上,且连接到导电通孔112。凸块下金属117可由选自由铬、镍、钯、金、银和合金及其等效物组成的群组的至少一个中的一或多个制成,但本发明的各方面并不限于此。凸块下金属117防止金属间化合物形成于导电通孔112与导电凸块150之间(例如,在其界面处),由此提高导电凸块150的可靠性。
半导体裸片120电连接到再分布层113(或再分布结构)。为此目的,半导体裸片120包含诸如Cu柱或Cu立柱的微凸块121(例如,裸片互连结构),且可电连接到通过焊料122设置于再分布层113(或再分布结构)的微凸块衬垫116中。另外,半导体裸片120可包含(例如)电路,例如数字信号处理器(DSP)、微处理器、网络处理器、功率管理处理器、音频处理器、RF电路、无线基带片上系统(SoC)处理器、传感器或专用集成电路(ASIC)。
底胶130插入半导体裸片120与插入件110之间,且允许半导体裸片120以更安全的方式机械连接到插入件110。此处,底胶130包围微凸块121和焊料122。特别地,底胶130防止半导体裸片120与插入件110之间的分层,由此防止其由于半导体裸片120与插入件110之间的热膨胀系数的差异而彼此电分离。在一些情况下,可不设置底胶130。
包封物140将位于插入件110的顶部表面上的半导体裸片120进行包封。也就是说,包封物140包围底胶130和半导体裸片120,由此安全地保护底胶130和半导体裸片120免受外部环境影响。在一些情况下,包封物140可能不覆盖半导体裸片120的顶部表面,以使半导体裸片120的顶部表面直接暴露于外部,由此提高半导体裸片120的散热效率。在其它实例实施中,包封物140可覆盖半导体裸片120的顶部表面。
同时,当形成包封物140的无机填充剂的直径小于半导体裸片120与插入件110之间的间隙尺寸时,(例如)可不使用底胶130。举例来说,当使用小于间隙尺寸的成型底胶(MUF)时,两个工艺步骤(底部填充和包封)可减少为一个工艺步骤(包封)。
导电凸块150可连接到形成于插入件110的底部表面上的凸块下金属117或直接连接到导电通孔112。导电凸块150可由选自由共晶焊料(Sn37Pb)、高铅焊料(Sn95Pb)、无铅焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu或SnAgBi)及其等效物组成的群组中的一个制成,但本实施例的各方面并不限于此。
如上文所描述,根据本发明的实施例的半导体装置100提供具有形成于加强件111上的再分布层113(或再分布结构)的插入件110,由此提高插入件110的机械刚度。也就是说,根据本发明的半导体装置100包含具有再分布层113(或再分布结构)的插入件110,所述再分布层(或再分布结构)形成于由具有高硬度和/或强度的材料(诸如,硅、玻璃或陶瓷等)制成以相较常规插入件加强插入件110的机械刚度的加强件111上,由此便于在制造半导体装置100的过程中操作插入件110以及提高完成的半导体装置100的机械可靠性。特别地,根据本发明的各种方面,插入件110的机械刚度得以加强,由此有效地抑制凸块下金属117与导电凸块150之间的界面分层。
参看图2A,说明了说明使用镶嵌工艺形成于加强件(111)中的导电通孔(112)的放大横截面图,且参看图2B,说明了说明使用等离子蚀刻工艺形成于硅衬底(111')上的硅穿孔(112')的放大横截面图。
如图2A所说明,使用镶嵌工艺形成穿过加强件111的顶部表面和底部表面的导电通孔112,且导电通孔112的横截面形状大体为倒置梯形。实际上,导电通孔112(例如,远离导电凸块150的导电通孔112的末端)的顶部表面直径稍大于导电通孔112(例如,朝向导电凸块150的导电通孔112的末端)的底部表面直径。另外,面向彼此的导电通孔112的侧表面为大体上平坦的倾斜表面。应注意,导电通孔112可(例如)为截锥形。
然而,如图2B所说明,使用等离子蚀刻工艺形成于硅衬底111'(或其它加强件材料)上的硅穿孔112'的横截面具有大体上矩形形状。也就是说,硅穿孔112'的顶部表面直径与硅穿孔112'的底部表面直径大体上相同。另外,由于工艺特征,多个凹坑(或凸起特征)112c'形成于硅穿孔112'的相对侧表面上。也就是说,硅穿孔112'的相对侧表面可能(例如)不是平坦表面,而可能是具有多个凹坑或凸起112c'的粗糙表面。应注意,导电通孔112'可(例如)为圆柱形。
另外,虽然使用镶嵌工艺形成于加强件111上的导电通孔112的纵横比在约1:1至约1:2的范围内,但使用等离子蚀刻工艺形成于硅衬底111'上的硅穿孔112'的纵横比在约1:10至约1:15的范围内。因此,根据本发明的导电通孔112的电路径远短于常规硅穿孔112'的电路径。另外,使用镶嵌工艺形成于加强件111上的导电通孔112的直径可在约10μm至约20μm的范围内。然而,使用等离子蚀刻工艺形成于硅衬底111'上的硅穿孔112'的直径远大于20μm。
另外,绝缘层112a和晶种层112b可进一步插入于加强件111与导电通孔112之间。当加强件111由硅制成时,绝缘层112a可为无机层(诸如氧化硅层或氮化硅层),但本发明的各方面并不限于此。同时,当加强件111由玻璃或陶瓷制成时,绝缘层112a可为有机层(诸如聚酰亚胺、苯并环丁烯或聚苯并噁唑),但本发明的各方面并不限于此。另外,晶种层112b可大体上由选自由钛/铜、钛钨/铜及合金及其等效物组成的群组中的一个制成,但本发明的各方面并不限于此。
同时,绝缘层112a'和晶种层112b'还可进一步插入在硅衬底111'与硅穿孔112'之间。在此情况下,由于工艺特征,多个凹坑(或凸起特征)112c'仍可保留在绝缘层112a'和晶种层112b'上。
也就是说,根据本发明,凹坑或凸起由于工艺特征并未形成于导电通孔112中,而凹坑(或凸起特征)由于常规工艺特征仍保留在硅穿孔112'上。
参看图3,说明根据本发明的另一实施例的半导体装置200的横截面图。如图3中所说明,根据本发明的另一实施例的半导体装置200可进一步包含电路板210、覆盖薄片220以及导电球230。
也就是说,半导体装置100通过导电凸块150电连接到电路板210。必要时,各种无源元件211可进一步安装在电路板210上。此外,底胶212在必要时可插入于半导体装置100与电路板210之间。另外,覆盖薄片220覆盖半导体装置100和安装在电路板210上的无源元件211,由此保护半导体装置100和无源元件211免受外部环境影响。另外,导电球230电连接到电路板210,且安装在外部装置(例如,主板或母板)上。此处,覆盖薄片220可使用粘合剂221粘附到电路板210,及/或可使用粘合剂222(例如,导热胶等)粘附到半导体装置100。
参看图4,说明根据本发明的再一实施例的半导体装置100的横截面图。
如图4中所说明,根据本发明的再一实施例的半导体装置100可直接安装在外部装置240(诸如主板或母板)上,而非电路板210上。
参看图5A至图5K,说明了连续说明根据本发明的再一实施例的制造半导体装置100的方法的横截面图。
如图5中所说明,具有预定深度的沟槽111a形成于加强件111中。由于沟槽111a通常为使用相对较便宜的蚀刻工艺形成,因此沟槽111a的横截面的形状大体上为倒置梯形。也就是说,沟槽111a的横截面具有底部表面111b和相对侧表面111c。此处,底部表面111b在大体上水平方向可为平坦的,且相对侧表面111c可为大体上垂直的倾斜平坦表面。换句话说,沟槽111a被配置成在其深度增加时具有较小直径。沟槽111a的横截面归因于在蚀刻工艺期间产生的各向异性蚀刻特征。
如图5B中所说明,绝缘层112a和晶种层112b连续形成于沟槽111a和沟槽111a的外部区域中。此处,当加强件111由硅制成时,绝缘层112a可为无机层(诸如氧化硅层或氮化硅层),但本发明的各方面并不限于此。同时,当加强件111由玻璃或陶瓷制成时,绝缘层112a可为有机层(诸如聚酰亚胺、苯并环丁烯或聚苯并噁唑),但本发明的各方面并不限于此。
在示范性实施例中,诸如氧化硅层或氮化硅层的无机层可通过将氧气和/或氮气供应至约900℃或更高的大气中的硅而形成为具有预定厚度,但本发明的各方面并不限于此。
在另一示范性实施例中,诸如聚酰亚胺层的有机层可通过旋涂、喷涂、浸涂或棒涂形成,但本发明的各方面并不限于此。
同时,晶种层112b可由钛/铜、钛钨/铜等制成,但本发明的范围并不限于此。晶种层112b可通过(例如)无电极电镀、电解电镀和/或溅镀形成,但本发明的各方面并不限于此。
如图5C中所说明,具有预定厚度的导电层1120可形成于具有形成于其中的绝缘层112a和晶种层112b的沟槽111a和沟槽111a的外部区域中。导电层1120可由铜、铝、金或银制成,但本发明的各方面并不限于此。同时,导电层1120可通过(例如)无电极电镀、电解电镀和/或溅镀形成,但本发明的各方面并不限于此。
如图5D中所说明,形成于沟槽111a和沟槽111a的外部区域中的导电层1120的预定部分可通过(例如)平面化工艺或化学机械抛光(CMP)工艺去除。在示范性实施例中,形成于位于加强件111的上侧的沟槽111a的外部区域中的导电层1120得以完全去除,以使得导电层1120可仅保留在沟槽111a内。在下文中,导电层1120将被称作导电通孔112。
如图5E中所说明,再分布图案114的一层或多层(例如,导电层)和介电层115形成于加强件111上,且微凸块衬垫116形成于最顶部再分布图案114上,由此完成再分布层113(或再分布结构)。也就是说,再分布晶种层图案114a形成为连接到加强件111的导电通孔112,再分布图案114形成于再分布晶种层图案114a上,且再分布图案114使用介电层115加工。另外,衬垫晶种层116a形成于最顶部再分布图案114上,且微凸块衬垫116随后形成于衬垫晶种层116a上。此处,微凸块衬垫116并未由介电层115覆盖,但暴露于外部以在后续工艺步骤中电连接到半导体裸片120。
此处,再分布晶种层图案114a和衬垫晶种层116a可使用无电极电镀、电解电镀或溅镀的一般工艺由钛/铜、钛钨/铜等制成,但本发明的范围不限于此类材料和/或此类工艺。另外,再分布层113(或再分布结构)和微凸块衬垫116可使用无电极电镀、电解电镀或溅镀和/或光刻由铜、铝、金或银制成,但本发明的范围不限于此类材料和/或此类工艺。另外,介电层115可使用旋涂、喷涂、浸涂或棒涂由聚酰亚胺、苯并环丁烯或聚苯并噁唑制成,但本发明的范围不限于此类材料和/或此类工艺。
如图5F中所说明,使用平面化工艺或CMP工艺去除加强件111中的沟槽111a的下部区域,但本发明的范围不限于此。因此,形成于沟槽111a中的导电通孔112的底部表面暴露于外部。同时,还可去除形成于导电通孔112的底部表面上的绝缘层112a和晶种层112b。也就是说,平面化工艺或CMP工艺可允许导电通孔112(例如,铜的底部表面)直接暴露于较下端。此处,加强件111的底部表面和导电通孔112的底部表面为共面的(或共面定位)。
如图5G中所说明,凸块下金属117形成于通过加强件111的底部表面暴露的导电通孔112中。也就是说,金属晶种层117a形成于导电通孔112的底部表面上,且凸块下金属117随后形成于金属晶种层117a上。金属晶种层117a可使用无电极电镀、电解电镀或溅镀的一般工艺由钛/铜、钛钨/铜等制成,但本发明的范围不限于此类材料和/或此类工艺。另外,凸块下金属117可由选自由铬、镍、钯、金、银及合金及其等效物组成的群组中的至少一个制成,但本发明的各方面并不限于此。另外,凸块下金属117还可使用无电极电镀、电解电镀和/或溅镀的一般工艺形成,但本发明的范围不限于此。凸块下金属117防止金属间化合物形成于导电通孔112与下文描述的导电凸块150之间(例如,在其界面处),由此提高导电凸块150的板层级可靠性。另外,必要时,介电层115可进一步形成于凸块下金属117与加强件111之间。在一些情况下,可不提供凸块下金属117。
以此方式,完成包含具有导电通孔112的加强件111和包含再分布图案114、介电层115、微凸块衬垫116和凸块下金属117的再分布层113(或再分布结构)的插入件110。
如图5H中所说明,至少一个半导体裸片120电连接到插入件110。在示范性实施例中,半导体裸片120可通过微凸块121和焊料122电连接到插入件110的微凸块衬垫116。在示范性实施例中,挥发性助熔剂布于插入件110的微凸块衬垫116上,且具有微凸块121的半导体裸片120在其上对准。在其之后,如果施加在约150℃至约250℃的范围内的温度,那么当形成于微凸块121的底端的焊料122熔化时,微凸块121与微凸块衬垫116稠合。随后,所得产物经受冷却工艺以允许形成于微凸块121的底端的焊料122固化,由此完成将半导体裸片120以电子和机械方式连接到插入件110。替代地,将半导体裸片120连接到插入件110的方法可以各种方式实施。
如图5I中所说明,底胶130填充于半导体裸片120与插入件110之间的间隙或空间中。例如,分配器中含有的底胶130分配到半导体裸片120与插入件110之间的间隙,随后进行固化,由此通过底胶130将半导体裸片120和插入件110以机械方式彼此连接。
在一些情况下,可不执行底胶130的填充。
如图5J中所说明,形成于插入件110的顶部表面上的半导体裸片120和底胶130由包封物140包封。此处,半导体裸片120的顶部表面可通过包封物140暴露于外部。包封物140可(例如)包围底胶130(如果形成的话)。又例如,包封物140的一部分可底部填充半导体裸片120作为成型底胶。
如图5K中所说明,导电凸块150连接到形成于插入件110的底部表面上的凸块下金属117。在示范性实施例中,挥发性助熔剂布于凸块下金属117上,且导电凸块150临时定位于其上。在其之后,如果施加在约150℃至约250℃的范围内的温度,那么导电凸块150熔化且与凸块下金属117稠合。随后,所得产物经受冷却工艺以允许导电凸块150固化,由此完成将导电凸块150以电子和机械方式连接到插入件110。另外,可采用各种方法将半导体裸片120连接到插入件110。
此处,可以各种方式执行将导电凸块150连接到插入件110的方法。
另外,可基于单元、面板、条带、裸片或矩阵执行前述工艺。当基于面板、条带、裸片或矩阵执行所述工艺时,可接着进行锯割工艺。也就是说,单独的半导体装置100通过锯割或冲压工艺从面板、条带、裸片或矩阵单体化。
如上文所描述,根据本发明,使用相对较便宜的镶嵌工艺形成导电通孔112,而非使用相对较贵的等离子蚀刻工艺或激光钻孔艺形成的硅穿孔,由此提供以低成本形成的包含插入件110的半导体装置100。也就是说,根据本发明,沟槽111a形成于加强件111中,且导电层1120随后形成于沟槽111a中,接着使用平坦化工艺或研磨工艺去除加强件111的区域,由此完成电连接加强件111的顶部表面和底部表面的导电通孔112。因此,根据本发明,能够与常规硅穿孔执行相同功能的导电通孔112可在不使用相对较贵的等离子蚀刻或激光钻孔工艺的情况下以低成本制造。
参看图6A至图6G,说明了连续说明根据本发明的再一实施例的制造半导体装置的方法的横截面图。此处,由于形成于再分布层(或再分布结构)上的半导体裸片、底胶和包封物与先前实施例的半导体裸片、底胶和包封物相同,因此将不给出其重复描述。
如图6中所说明,具有预定深度的双沟槽311a形成于加强件311中。也就是说,相对较深较窄的第一沟槽311b形成于加强件311中,且相对较浅较宽的第二沟槽311c形成于第一沟槽311b中。由于双沟槽311a通过一般光刻工艺形成,因此双沟槽311a的横截面形状可为两个倒置梯形。
如图6B中所说明,绝缘层312a和晶种层312b连续形成于双沟槽311a和双沟槽311a的外部区域中。此处,当加强件311由硅制成时,绝缘层312a可为无机层(诸如氧化硅层或氮化硅层),但本发明的范围不限于此。当加强件311由玻璃或陶瓷制成时,绝缘层312a可为有机层(诸如聚酰亚胺、苯并环丁烯或聚苯并噁唑),但本发明的范围不限于此。
如图6C中所说明,具有预定厚度的导电层3120可形成于具有形成于其中的绝缘层312a和晶种层312b的双沟槽311a和双沟槽311a的外部区域中。
如图6D中所说明,形成于双沟槽311a和双沟槽311a的外部区域中的导电层3120的预定厚度的预定部分可通过平面化工艺或化学机械抛光(CMP)工艺去除,但本发明的范围不限于此。在示范性实施例中,形成于位于加强件311的上侧的双沟槽311a的外部区域中的导电层3120得以完全去除,以使得导电层3120可仅保留在双沟槽311a内。此处,填充于第一沟槽311b中的导电层3120可在后一工艺中转变为导电柱317,且填充于第二沟槽311c中的导电层3120可在后一工艺中转变为导电通孔312。在下文中,导电层3120将被称作导电柱317和导电通孔312。
如图6E中所说明,再分布图案314的一层或多层(例如,导电层)和介电层315可形成于加强件311上,且微凸块衬垫316形成于最顶部再分布图案314上,由此完成再分布层313(或再分布结构)。也就是说,再分布晶种层314a形成为连接到加强件311的导电通孔312,再分布图案314形成于再分布晶种层314a上,且再分布图案314由介电层315覆盖。另外,衬垫晶种层316a形成于最顶部再分布图案314上,且微凸块衬垫316随后形成于衬垫晶种层316a上。
如图6F中所说明,形成于加强件311中的第一沟槽311b的下部区域可通过平面化工艺或化学机械抛光(CMP)工艺去除。另外,形成于加强件311中的第一沟槽311b的外部区域(即,导电柱317的外部区域)得以去除,由此提供配置成自导电通孔312向下延伸一预定长度的导电柱317。例如,在加强件311由硅制成的实例实施中,硅蚀刻工艺可用于减小加强件311的厚度,以使得导电柱317(例如,整个柱317或其一部分)自加强件311的底侧突出。应注意,导电通孔312的底侧此时可与加强件311共面,此时可自加强件311突出,或此时可由加强件311覆盖。在实例实施例中,导电通孔312被配置成定位于加强件311内,且导电柱317被配置成自加强件311向下延伸一预定长度。
如图6G中所说明,位于导电柱317的底部表面上的绝缘层312a被去除,由此将焊料318电连接到导电柱317的底部表面。位于导电柱317的底部表面上的晶种层312b必要时可保留或可去除。
另外,可在将半导体裸片附接到插入件310及将底胶和包封物应用于所得产物后形成焊料318。另外,由于半导体裸片、底胶和包封物与先前实施例的半导体裸片、底胶和包封物相同,因此将不给出形成工艺步骤和其配置的重复描述。
如上文所描述,根据本发明,可通过使用镶嵌工艺在插入件310上形成导电柱317来形成具有细节距的导电柱317。也就是说,双沟槽311a形成于加强件311中,导电层3120填充于双沟槽311a中,且加强件311的预定区域通过平面化或研磨工艺和蚀刻工艺来去除,由此实现连接加强件311的顶部表面和底部表面的导电通孔312以及一体形成于导电通孔312中的导电柱317。因此,根据本发明,可以低成本形成具有细节距的导电柱317。
本文中的论述包含展示电子装置组合件的各个部分及其制造方法的众多说明性图。为了清楚地示意,这些图并未示出每个实例组合件的所有方面。本文中提供的任何实例组合件和/或方法可以与本文中提供的任何或全部其它组合件和/或方法共享任何或全部特征。
综上所述,本发明的各种方面提供一种半导体装置和一种制造半导体装置的方法。作为非限制实例,本发明的各种方面提供一种半导体装置及其制造方法,所述半导体装置包括形成于加强层上的再分布结构。虽然已经参考某些方面和实例描述了以上内容,但是所属领域的技术人员应理解,在不脱离本发明的范围的情况下,可以进行各种修改并可以替代等效物。另外,在不脱离本发明的范围的情况下,可以进行许多修改以使特定情况或材料适应本发明的教示。因此,希望本发明不限于所公开的特定实例,而是本发明将包含落入所附权利要求书的范围内的所有实例。
Claims (20)
1.一种半导体装置,其包括:
插入件,其包括:
加强件层,其包括顶部加强件表面、底部加强件表面和导电通孔,所述导电通孔从所述顶部加强件表面延伸到所述底部加强件表面;及
再分布结构,其包括顶部再分布结构表面和耦合到所述顶部加强件表面的底部再分布结构表面;以及
半导体裸片,其连接到所述顶部再分布结构表面。
2.根据权利要求1所述的半导体装置,其中所述加强件层包括硅层、玻璃层和/或陶瓷层。
3.根据权利要求1所述的半导体装置,其中所述导电通孔具有形状呈倒置梯形的横截面,其中所述顶部加强件表面处的顶部通孔端比所述底部加强件表面处的底部通孔端更宽。
4.根据权利要求1所述的半导体装置,其中所述导电通孔的顶部通孔表面具有较所述导电通孔的底部通孔表面更大的直径。
5.根据权利要求1所述的半导体装置,其包括在所述导电通孔与所述加强件之间的晶种层和绝缘层。
6.根据权利要求1所述的半导体装置,其进一步包括耦合到所述导电通孔的底部通孔端的导电凸块。
7.根据权利要求6所述的半导体装置,其进一步包括在所述导电通孔与所述导电凸块之间的凸块下金属。
8.根据权利要求1所述的半导体装置,其中所述导电通孔的侧面包括凹坑。
9.根据权利要求1所述的半导体装置,其包括所述导电通孔的侧面周围的绝缘层,其中所述绝缘层包括凹坑。
10.一种半导体装置,其包括:
插入件,其包括:
加强件层,其包括顶部加强件表面、底部加强件表面和导电通孔,所述导电通孔从所述顶部加强件表面延伸到所述底部加强件表面;
再分布结构,其包括顶部再分布结构表面和耦合到所述顶部加强件表面的底部再分布结构表面;以及
导电柱,其自所述导电通孔的底部通孔表面延伸;以及
半导体裸片,其连接到所述顶部再分布结构表面。
11.根据权利要求10所述的半导体装置,其中整个所述导电柱具有较所述导电通孔的宽度更小的宽度。
12.根据权利要求11所述的半导体装置,其中所述导电柱具有形状呈倒置梯形的横截面,其中顶部柱端比底部柱端更宽。
13.根据权利要求12所述的半导体装置,其中所述导电通孔具有形状呈倒置梯形的横截面,其中顶部通孔端比底部通孔端更宽。
14.根据权利要求10所述的半导体装置,其中所述底部导电柱自所述底部加强件表面延伸。
15.根据权利要求10所述的半导体装置,其包括耦合到所述导电柱的底部柱端的导电凸块。
16.根据权利要求10所述的半导体装置,其中所述导电通孔与所述导电柱彼此一体地形成。
17.根据权利要求10所述的半导体装置,其包括晶种层和绝缘层,其中:
所述晶种层的第一部分和所述绝缘层的第一部分在所述导电通孔与所述加强件之间;以及
所述晶种层的第二部分和所述绝缘层的第二部分在所述导电柱与所述加强件之间。
18.根据权利要求10所述的半导体装置,其中整个所述导电柱自所述底部加强件表面延伸。
19.一种制造半导体装置的方法,所述方法包括:
提供插入件,所述插入件包括:
加强件层,其包括顶部加强件表面、底部加强件表面和导电通孔,所述导电通孔从所述顶部加强件表面延伸到所述底部加强件表面;及
再分布结构,其包括顶部再分布结构表面和耦合到所述顶部加强件表面的底部再分布结构表面;以及
将半导体裸片附接到所述顶部再分布结构表面。
20.根据权利要求19所述的方法,其中所述插入件包括自所述导电通孔的底部通孔表面延伸的导电柱。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101672640B1 (ko) * | 2015-06-23 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
TWI733690B (zh) * | 2015-08-14 | 2021-07-21 | 新加坡商Pep創新私人有限公司 | 半導體加工方法 |
US9859222B1 (en) * | 2016-06-08 | 2018-01-02 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US9899305B1 (en) * | 2017-04-28 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure |
JP7335036B2 (ja) * | 2019-03-29 | 2023-08-29 | ラピスセミコンダクタ株式会社 | 半導体パッケージの製造方法 |
KR102615198B1 (ko) | 2019-10-15 | 2023-12-18 | 삼성전자주식회사 | 반도체 패키지 |
TWI768294B (zh) * | 2019-12-31 | 2022-06-21 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
KR20220025545A (ko) | 2020-08-24 | 2022-03-03 | 삼성전자주식회사 | 신뢰성을 향상시킬 수 있는 반도체 패키지 |
KR20220026308A (ko) | 2020-08-25 | 2022-03-04 | 삼성전자주식회사 | 반도체 패키지 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
CN102867783A (zh) * | 2011-07-05 | 2013-01-09 | 台湾积体电路制造股份有限公司 | 用于切割插入组件的装置和方法 |
CN103346120A (zh) * | 2013-07-01 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | 一种利用化学刻蚀露出tsv头部的方法及相应器件 |
US20140103527A1 (en) * | 2012-03-23 | 2014-04-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units |
CN103943600A (zh) * | 2013-06-07 | 2014-07-23 | 珠海越亚封装基板技术股份有限公司 | 在芯片和基板之间的新型端接和连接 |
CN104009019A (zh) * | 2013-02-27 | 2014-08-27 | 台湾积体电路制造股份有限公司 | 层叠封装件的外围电连接 |
US20140355931A1 (en) * | 2013-05-28 | 2014-12-04 | Georgia Tech Research Corporation | Glass-Polymer Optical Interposer |
US20150130070A1 (en) * | 2013-11-11 | 2015-05-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package and manufacturing method thereof |
CN206040615U (zh) * | 2015-06-23 | 2017-03-22 | 艾马克科技公司 | 半导体装置 |
Family Cites Families (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63245952A (ja) * | 1987-04-01 | 1988-10-13 | Hitachi Ltd | マルチチップモジュ−ル構造体 |
JP2716336B2 (ja) * | 1993-03-10 | 1998-02-18 | 日本電気株式会社 | 集積回路装置 |
TW512467B (en) * | 1999-10-12 | 2002-12-01 | North Kk | Wiring circuit substrate and manufacturing method therefor |
US6586684B2 (en) * | 2001-06-29 | 2003-07-01 | Intel Corporation | Circuit housing clamp and method of manufacture therefor |
US6780673B2 (en) * | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
US7462936B2 (en) * | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
WO2005065207A2 (en) * | 2003-12-30 | 2005-07-21 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP2006049804A (ja) * | 2004-07-07 | 2006-02-16 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
US7317249B2 (en) * | 2004-12-23 | 2008-01-08 | Tessera, Inc. | Microelectronic package having stacked semiconductor devices and a process for its fabrication |
US7388296B2 (en) * | 2005-06-09 | 2008-06-17 | Ngk Spark Plug Co., Ltd. | Wiring substrate and bonding pad composition |
US7667473B1 (en) * | 2005-09-28 | 2010-02-23 | Xilinx, Inc | Flip-chip package having thermal expansion posts |
US7911805B2 (en) * | 2007-06-29 | 2011-03-22 | Tessera, Inc. | Multilayer wiring element having pin interface |
US20090071707A1 (en) * | 2007-08-15 | 2009-03-19 | Tessera, Inc. | Multilayer substrate with interconnection vias and method of manufacturing the same |
WO2009023283A2 (en) * | 2007-08-15 | 2009-02-19 | Tessera, Inc. | Interconnection element with posts formed by plating |
JP5629580B2 (ja) * | 2007-09-28 | 2014-11-19 | テッセラ,インコーポレイテッド | 二重ポスト付きフリップチップ相互接続 |
EP2213148A4 (en) * | 2007-10-10 | 2011-09-07 | Tessera Inc | ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED |
TWI389290B (zh) * | 2007-11-08 | 2013-03-11 | Ind Tech Res Inst | 晶片結構及其製程、晶片堆疊結構及其製程 |
JP2009158593A (ja) * | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | バンプ構造およびその製造方法 |
KR100961310B1 (ko) * | 2008-02-25 | 2010-06-04 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
JP5290017B2 (ja) * | 2008-03-28 | 2013-09-18 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
US20100044860A1 (en) * | 2008-08-21 | 2010-02-25 | Tessera Interconnect Materials, Inc. | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer |
US7915080B2 (en) * | 2008-12-19 | 2011-03-29 | Texas Instruments Incorporated | Bonding IC die to TSV wafers |
US8115310B2 (en) * | 2009-06-11 | 2012-02-14 | Texas Instruments Incorporated | Copper pillar bonding for fine pitch flip chip devices |
KR20110000960A (ko) * | 2009-06-29 | 2011-01-06 | 삼성전자주식회사 | 반도체 칩, 스택 모듈, 메모리 카드 및 그 제조 방법 |
US20110186960A1 (en) * | 2010-02-03 | 2011-08-04 | Albert Wu | Techniques and configurations for recessed semiconductor substrates |
US20110207323A1 (en) * | 2010-02-25 | 2011-08-25 | Robert Ditizio | Method of forming and patterning conformal insulation layer in vias and etched structures |
JP5711472B2 (ja) * | 2010-06-09 | 2015-04-30 | 新光電気工業株式会社 | 配線基板及びその製造方法並びに半導体装置 |
US8471577B2 (en) * | 2010-06-11 | 2013-06-25 | Texas Instruments Incorporated | Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate |
US8330272B2 (en) * | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) * | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US9224647B2 (en) * | 2010-09-24 | 2015-12-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer |
US8338945B2 (en) * | 2010-10-26 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molded chip interposer structure and methods |
US8487425B2 (en) * | 2011-06-23 | 2013-07-16 | International Business Machines Corporation | Optimized annular copper TSV |
US8952540B2 (en) * | 2011-06-30 | 2015-02-10 | Intel Corporation | In situ-built pin-grid arrays for coreless substrates, and methods of making same |
US8691691B2 (en) * | 2011-07-29 | 2014-04-08 | International Business Machines Corporation | TSV pillar as an interconnecting structure |
US9177832B2 (en) * | 2011-09-16 | 2015-11-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect |
US8957518B2 (en) * | 2012-01-04 | 2015-02-17 | Mediatek Inc. | Molded interposer package and method for fabricating the same |
US8770462B2 (en) * | 2012-03-14 | 2014-07-08 | Raytheon Company | Solder paste transfer process |
US10049964B2 (en) * | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US9030010B2 (en) * | 2012-09-20 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging devices and methods |
KR101411813B1 (ko) * | 2012-11-09 | 2014-06-27 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
KR101419601B1 (ko) * | 2012-11-20 | 2014-07-16 | 앰코 테크놀로지 코리아 주식회사 | Emc 웨이퍼 서포트 시스템을 이용한 반도체 디바이스 및 이의 제조방법 |
IL223414A (en) * | 2012-12-04 | 2017-07-31 | Elta Systems Ltd | Integrated electronic device and method for creating it |
US9768048B2 (en) * | 2013-03-15 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on-package structure |
US9305890B2 (en) * | 2014-01-15 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package having substrate with embedded metal trace overlapped by landing pad |
US9165793B1 (en) * | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
US9355983B1 (en) * | 2014-06-27 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer structure and method of manufacture thereof |
TWI533771B (zh) * | 2014-07-17 | 2016-05-11 | 矽品精密工業股份有限公司 | 無核心層封裝基板及其製法 |
US9373564B2 (en) * | 2014-08-07 | 2016-06-21 | Industrial Technology Research Institute | Semiconductor device, manufacturing method and stacking structure thereof |
US9733304B2 (en) * | 2014-09-24 | 2017-08-15 | Micron Technology, Inc. | Semiconductor device test apparatuses |
US20160111380A1 (en) * | 2014-10-21 | 2016-04-21 | Georgia Tech Research Corporation | New structure of microelectronic packages with edge protection by coating |
US9761534B2 (en) * | 2015-09-21 | 2017-09-12 | Mediatek Inc. | Semiconductor package, semiconductor device using the same and manufacturing method thereof |
US9673148B2 (en) * | 2015-11-03 | 2017-06-06 | Dyi-chung Hu | System in package |
-
2015
- 2015-06-23 KR KR1020150089245A patent/KR101672640B1/ko active Search and Examination
-
2016
- 2016-05-08 US US15/149,158 patent/US20160379915A1/en not_active Abandoned
- 2016-06-01 TW TW112106769A patent/TW202324643A/zh unknown
- 2016-06-01 TW TW105117129A patent/TWI796282B/zh active
- 2016-06-23 CN CN201610461558.9A patent/CN106298684B/zh active Active
- 2016-06-23 CN CN202210284462.5A patent/CN114823544A/zh active Pending
- 2016-06-23 CN CN201620629791.9U patent/CN206040615U/zh active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
CN102867783A (zh) * | 2011-07-05 | 2013-01-09 | 台湾积体电路制造股份有限公司 | 用于切割插入组件的装置和方法 |
US20140103527A1 (en) * | 2012-03-23 | 2014-04-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units |
CN104009019A (zh) * | 2013-02-27 | 2014-08-27 | 台湾积体电路制造股份有限公司 | 层叠封装件的外围电连接 |
US20140355931A1 (en) * | 2013-05-28 | 2014-12-04 | Georgia Tech Research Corporation | Glass-Polymer Optical Interposer |
CN103943600A (zh) * | 2013-06-07 | 2014-07-23 | 珠海越亚封装基板技术股份有限公司 | 在芯片和基板之间的新型端接和连接 |
CN103346120A (zh) * | 2013-07-01 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | 一种利用化学刻蚀露出tsv头部的方法及相应器件 |
US20150130070A1 (en) * | 2013-11-11 | 2015-05-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package and manufacturing method thereof |
CN206040615U (zh) * | 2015-06-23 | 2017-03-22 | 艾马克科技公司 | 半导体装置 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110875299A (zh) * | 2018-08-29 | 2020-03-10 | 三星电子株式会社 | 半导体封装件 |
CN110875299B (zh) * | 2018-08-29 | 2023-10-31 | 三星电子株式会社 | 半导体封装件 |
CN111584422A (zh) * | 2019-02-18 | 2020-08-25 | 英飞凌科技股份有限公司 | 半导体装置及其制造方法 |
US11688712B2 (en) | 2019-02-18 | 2023-06-27 | Infineon Technologies Ag | Semiconductor arrangement and method for producing the same |
CN111584422B (zh) * | 2019-02-18 | 2023-10-24 | 英飞凌科技股份有限公司 | 半导体装置及其制造方法 |
US11955450B2 (en) | 2019-02-18 | 2024-04-09 | Infineon Technologies Ag | Method for producing a semiconductor arrangement |
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CN206040615U (zh) | 2017-03-22 |
KR101672640B1 (ko) | 2016-11-03 |
TWI796282B (zh) | 2023-03-21 |
TW202324643A (zh) | 2023-06-16 |
CN114823544A (zh) | 2022-07-29 |
CN106298684B (zh) | 2022-03-29 |
TW201701431A (zh) | 2017-01-01 |
US20160379915A1 (en) | 2016-12-29 |
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