CN102867783A - 用于切割插入组件的装置和方法 - Google Patents

用于切割插入组件的装置和方法 Download PDF

Info

Publication number
CN102867783A
CN102867783A CN2011103448514A CN201110344851A CN102867783A CN 102867783 A CN102867783 A CN 102867783A CN 2011103448514 A CN2011103448514 A CN 2011103448514A CN 201110344851 A CN201110344851 A CN 201110344851A CN 102867783 A CN102867783 A CN 102867783A
Authority
CN
China
Prior art keywords
integrated circuit
adhesive tape
substrate
package
plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103448514A
Other languages
English (en)
Other versions
CN102867783B (zh
Inventor
王忠裕
叶宫辰
吴志伟
卢思维
林俊成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102867783A publication Critical patent/CN102867783A/zh
Application granted granted Critical
Publication of CN102867783B publication Critical patent/CN102867783B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Dicing (AREA)

Abstract

本发明公开了用于在晶圆插入件上实施切割管芯的方法和装置。公开了方法，包括：接收包括一个或多个集成电路管芯的插入组件，该一个或多个集成电路管芯被安装在插入衬底的管芯侧面上，并且具有限定在集成电路管芯之间的空间中的划线区域，该插入件具有用于接收外部连接件的相对侧面；将插入组件的管芯侧面安装在胶带组件上，胶带组件包括胶带和预成形隔离件，该预成形隔离件位于集成电路管芯之间并且填充集成电路管芯之间的间隙；通过在划线区域中切割插入件的相对侧面切割插入组件，从而使切口穿过插入件，这些切口将插入件分离为位于晶圆组件上的一个或多个管芯。公开了该方法使用的装置。

Description

用于切割插入组件的装置和方法
技术领域
本申请涉及半导体领域，更具体地，涉及用于切割插入组件的装置和方法。
背景技术
当前的集成电路制造和封装的共同要求是使用接收多个集成电路管芯的插入件。穿透通孔或者穿透硅通孔(“TSV”)的使用日益增加。这些穿透通孔允许在安装在插入件的一个侧面上的集成电路管芯和元件，和安装在插入件的相对侧面上的诸如焊料球的端子之间的电连接。此外，通过硅插入衬底的TSV技术的使用能够进行插入组件的晶圆级加工(“WLP”)。用于安装多个集成电路(IC)管芯的外型尺寸用于晶圆衬底，例如，具有穿透晶圆连接的TSV的半导体晶圆。可以将IC安装在硅晶圆的一个侧面上，并且可以将至少某些IC端子连接至插入件中的TSV。可以在插入件的相对侧面上形成诸如焊料球、凸块、或者柱形物的板级连接，并且使用TSV将该板级连接连接至IC。现在，可以使用焊料回流技术和焊料凸块或者焊球将该组件安装在电路板上。TSV穿透晶圆连接的使用还允许组件的垂直堆叠能力，使厂商提高了集成电路元件密度和系统性能，而没有增大电路板面积。例如，这种技术越来越多地应用于提高的存储或存储器件密度，而没有增加电路板面积。当诸如智能手机和平板计算机的手持和便携装置的需要增加时，板面积和板尺寸限制也增加，并且插入组件和TSV的使用可以满足这些要求。在可以实施穿透通孔连接、用于连接元件的导体图案化、以及元件安装的情况下，将这些技术应用于诸如硅晶圆的半导体晶圆，但是还可以应用于其他插入材料，例如，BT树脂和其他插入材料。
在将管芯安装在插入晶圆上的工艺期间，可以将该工艺称作“晶圆上管芯”(“DOW”)装配，实施晶圆切割步骤，从而将独立集成电路管芯元件分离为隔离的组件单元，其中，每个独立集成电路管芯元件可以包括：几个IC，被安装在插入件的一个侧面上；一组电路板连接，例如焊料柱、焊料凸块、或者焊料球，被安装在相对侧面上。可以将该工艺称作“分离”。在晶圆切割期间，将湿刀片用于在IC之间的间隙(“划片槽”)中的划线区域中切割晶圆。传统的切割或“切割(dicing)”技术用于半导体晶圆。称作切割胶带的胶带通常用于在切割期间保护晶圆并且保持该晶圆固定。在切割期间，湿切割操作沿着划片槽切割晶圆。然而，DOW晶圆组件具有：集成电路管芯，被安装在一个侧面上；和焊料球或焊料凸块，位于另一侧面上。DOW组件的两侧都不会不安装物体。DOW组件的两侧都不提供用于安装到传统切割胶带的简单平面。因为在切割工艺中的切割操作为使用高速旋转刀片和喷射水的机械操作，所以产生振动。在尝试使用传统方法切割组件期间，已经注意到以晶圆剥离的形式损害插入件，损害IC(包括IC崩角)，以及损害焊料球。当切割时，注意到导致管芯飞出或管芯倾斜的水渗透。注意到在切割操作期间通过插入件的任一侧面上的非平面所导致的在胶带和硅插入件之间的胶带剥离。这些问题中的任一个导致故障，该故障可能导致在切割阶段的已知良好管芯(“KGD”)较大损耗，从而大幅提高了电路组件的成本并且降低了电路组件的成品率。
因此，不断需要有效实施用于插入组件的切割的方法和系统，而没有损害插入件、安装的IC、或者连接端子。需要进行改进，从而提高了制造成品率，并且降低了如今当使用现有方法时所遇到的对成品器件的损害问题。
发明内容
为解决上述问题，本发明提供了一种方法，包括：接收包括一个或多个集成电路管芯的插入组件，一个或多个集成电路管芯被安装在插入衬底的管芯侧上，并且在集成电路管芯之间的空间中限定有划线区域；将插入组件的管芯侧安装在胶带组件上，胶带组件包括：胶带和隔离件，位于集成电路管芯之间并且填充集成电路管芯之间的间隙；以及通过切割划线区域切割插入组件。
其中，插入组件包括：焊料凸块连接件，位于插入组件的相对侧面上。
该方法，进一步包括：在切割以后，使胶带组件暴露在UV能量源之下。
其中，插入衬底为硅晶圆。
其中，插入衬底包括：一个或多个衬底通孔TSV，延伸通过插入衬底。
其中，将插入衬底去薄至小于200微米的厚度。
其中，将插入组件的管芯侧安装至胶带组件上的步骤进一步包括：以与位于插入衬底的管芯侧上的集成电路管芯之间的间隙相对应的图案将隔离件安装在胶带上；以及将胶带和隔离件安装在插入衬底的管芯侧上，隔离件填充集成电路管芯之间的间隙。
其中，将插入组件的管芯侧安装在胶带组件上的步骤进一步包括：将胶带安装在插入衬底的管芯侧上，胶带延伸进入集成电路管芯之间的间隙中；以及将预成形的隔离件安装在管芯之间的胶带上。
该方法进一步包括：在切割步骤以后，从插入组件释放胶带。
此外，还提供了一种方法，包括：接收插入组件，插入组件包括：衬底；多个衬底通孔，形成在衬底中；以及多个集成电路管芯，安装在衬底上，其中，在集成电路管芯之间的空间中形成划线区域；将胶带组件安装在插入组件上，胶带组件包括：胶带层和隔离件，位于集成电路管芯之间的间隙中；以及经由划线区域切割插入组件。
其中，将多个集成电路管芯分组为多个电路，多个电路中的每一个均包括彼此连接的至少两个集成电路管芯。
其中，至少两个集成电路管芯具有不同厚度。
其中，至少两个集成电路管芯具有不同功能。
其中，胶带组件具有与插入组件的衬底相对应的尺寸。
其中，隔离件中的至少一个的厚度小于或等于集成电路管芯的最大厚度。
其中，将胶带组件安装在插入组件上的步骤包括：将胶带层安装在集成电路管芯上方，胶带层延伸到集成电路管芯之间的间隙；以及将隔离件安装在集成电路管芯之间的间隙中的胶带层上方。
此外，还提供了一种装置，包括：多个集成电路管芯，安装在插入件的管芯侧面上，集成电路管芯之间具有间隙；外部连接件，安装在插入件的相对侧上；以及隔离件，位于插入件的管芯侧上的集成电路管芯之间的间隙中。
该装置进一步包括：胶带层，位于隔离件和插入件之间。
其中，插入件选自由硅衬底和玻璃衬底所组成的组中。
其中，插入件包括：一个或多个衬底通孔，延伸通过插入件。
附图说明
为了更好地理解本实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1示出了通过实施例所使用的中间工艺的示例性组件的横截面图；
图2示出了在附加工艺以后的图1的组件的横截面图；
图3示出了在附加工艺以后的图2的组件的横截面图；
图4示出了在附加工艺以后的图3的组件的横截面图；
图5示出了晶圆载具(wafer carrier)的实施例的平面图；
图6示出了图5的实施例的一部分的横截面图；
图7示出了通过位于晶圆组件上的示例性管芯使用的晶圆载具的实施例的横截面图；
图8示出了方法实施例的流程图；
图9示出了晶圆载具的备选方法的平面图；
图10示出了通过图9的实施例使用的固定件的一部分的横截面图；
图11示出了通过位于晶圆组件上的示例性管芯使用的图9的晶圆载具的备选实施例的横截面图；以及
图12示出了方法的备选实施例的流程图。
附图、原理图、以及示意图为示例性的并且不是为了限定，而是本发明的实施例的实例，为了说明，简化了这些附图、原理图、以及示意图，并且没有按照比例进行绘制。
具体实施方式
下面，详细讨论本实施例的制造和使用。然而，应该理解，本实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出制造和使用实施例的具体方式，而不用于限制实施例或权利要求的范围。
现在，详细描述了本申请的实施例，本申请的实施例提供了用于有效通过提供支撑机制并且在切割操作期间保护位于插入组件上的管芯的保护方法制造位于插入组件上的管芯的新型方法和装置。通过提供保护安装方法和切割装置，可以实施切割操作，而插入件没有崩角，剥离或损害安装在插入件上的IC，并且没有损害安装在晶圆上的诸如焊料球的端子。降低或消除了在切割操作中KGD IC器件的损失，提高了成品率，并且因此，降低了单元成本。在实施例中，使用在切割操作以后，允许容易拾取和放置操作的材料，进一步提高了效率和成品率。
为了示出实施例及其操作，首先描述了示例性组件加工步骤。简化了这些步骤并且仅为示例性的，并且不是为了限定实施例或者权利要求的范围，并且为了说明和理解实施例，介绍了这些实例。
图1示出了插入组件11的横截面图。在图1中，描述了衬底13。该衬底可以为硅晶圆、半导体衬底、玻璃、陶瓷、BT树脂、环氧树脂、或者用于插入件的其他衬底材料。
示出了垂直延伸到衬底13中的衬底通孔(“TSV”)15。使用光刻、显影、图案化、蚀刻、以及电镀步骤将这些通孔形成为“盲孔(blind vias)”。例如，可以使用电镀为通孔的铜或者另一导体材料完成TSV。可以使用势垒层和种子层。覆盖TSV 15的焊盘21可以将TSV彼此连接，或者将该焊盘用于连接在稍后步骤中安装的集成电路(未示出)。
在衬底13的上方形成钝化层23。形成微凸块连接。在凸块下金属层(“UBM”)19的上方形成凸块17。凸块17可以由包括铅基焊料或无铅焊料的焊料形成，通常诸如SnAg(SA)或者SnAgCu(“SAC”)的共晶材料可以用于无铅应用。如本领域中已知的，这些材料形成具有熔点的化合物，该具有熔点的化合物与焊料回流步骤兼容。在一些实施例中，凸块17为微凸块。
图2示出了在安装集成电路管芯24和25以后的插入组件11的横截面图。注意，这些IC可以为不同类型，并且因此，可以具有如图所示的不同厚度。然而，这仅为一个实例，并且IC管芯24和25可以为相同类型，并且还具有相同厚度。例如，IC管芯24和25可以具有高达600微米的厚度。在焊料回流操作期间安装IC管芯以后，施加底部填充27，该焊料回流操作使凸块融化，从而形成与衬底13的物理和电连接。底部填充在加工期间保护凸块，并且在热应力期间保护系统。可以将IC管芯24和25彼此电连接至，从而形成系统，但是在使用实施例的情况下，没有必要在所有应用中进行这种连接。
图3示出了在附加工艺步骤以后的插入组件11的另一横截面图。衬底13经受衬底薄化操作，对于半导体晶圆衬底，通过背部研磨操作实施该薄化。如图3所示，通过物理研磨和/或化学蚀刻继续进行薄化，直到在衬底13的底面上暴露TSV的底端。在背部研磨操作以后，衬底13可以薄至小于200微米的厚度，例如，作为非限定实例，在100-200微米之间。
在图3中，线28示出了划片槽区域。该线示出了在切割操作中切割衬底，从而将插入组件划分为独立组件的位置。
图4示出了在附加工艺步骤以后的插入组件11的另一横截面图。现在，示出了焊料球33，该焊料球被设置在衬底13的焊料球侧面(这里，底面)上，其中，衬底电路管芯25和24被设置在衬底13的管芯侧面(这里，顶面)上。将焊料球33连接至TSV 15中的至少一些，并且在覆盖TSV的焊盘31上形成该焊料球。衬底13的底面可以具有形成连接的重新分布层(“RDL”)，该再分布层垂直延伸，并且将焊料球映射到不同TSV，从而提供了焊料球定位的灵活性。焊料球33可以为铅基焊料、或无铅焊料，并且该焊料球适用于焊料回流工艺，稍后将该焊料回流工艺用于将插入组件安装至目标系统中的母版、系统板等。在一些实施例中，通过金属柱替换焊料球33。金属柱可以由铜、铜合金、或者任何适当材料形成。焊盘31可以具有各种电镀处理，从而提高粘着力，提供了扩散势垒区，防止氧化，并且提高了可焊性，该金属柱包括：镍、金、铂、钯、铜、以及其合金，并且包括无电镀镍浸金(“ENIG”)、无电镀镍无电镀钯浸金(“ENEPIG”)等的这些处理。
图4中示出了在背部研磨和焊料球安装以后的插入组件11。现在，插入组件11为切割操作作准备；在该实例中，在划片槽28处。在切割阶段处的切割刀片沿该划片槽切割衬底13，并且将该组件划分为两部分。这两部分可以为相同组件，虽然在图4的该简单例证中仅示出了两部分，但是可以使用WLP组件在硅晶圆上形成多个部分，从而提高成品率。IC管芯24和25配对在一起，并且在晶圆上重复该管芯对，通过包括划片槽区域的管芯到管芯间隙来分离这些管芯对。
现在，衬底13非常薄。因此，很容易损害在背部研磨以后的衬底13。如果尝试传统切割方法，则通过焊料球33向下安装该组件，或者集成电路管芯面对下部。例如，可以将具有粘合剂的胶带设置在焊料球上。然而，由于在胶带和衬底之间形成的垂直空间，安装在切割胶带上的焊料球在切割期间不能防止衬底13的振动。在这种布置中，已经意识到在切割期间的问题，均意识到包括剥离IC、管芯容易飞出、插入件崩角和损害插入件、以及剥离焊料球的问题。如果将诸如背部研磨胶带的不同胶带用于焊球下部，则可以将焊球内嵌在粘合剂中。背部研磨胶带使用更软的粘合剂材料，当使用这种胶带时，发现严重的插入件背部崩角，并且随后的拾取和放置操作在切割以后从胶带去除组件可能去除焊料球，或者相反，很难去除焊料球。如果相反，将插入组件11管芯侧面向下置于切割或者背部研磨胶带上，则在管芯24、25中的厚度偏差可能导致额外的振动损害，并且此外，在管芯之间没有支撑衬底13，因此，可能产生崩角。此外，衬底13的边缘没有任何管芯或焊球，并且在任何情况下，不支撑这些区域，在切割期间导致额外的振动和损害。
图5示出了可以通过实施例使用的晶圆载具组件51。确定晶圆载具组件51的尺寸并且将该晶圆载具组件图案化，从而对应于衬底13，并且该晶圆载具组件51具有对应于衬底上的管芯24和25的区域。对于非限定实例来说，如果衬底13为300毫米晶圆，则晶圆载具组件51也为300毫米直径。线6-6′示出了在图6中示出的晶圆载具51的横截面。如下文中进一步描述的，在“管芯向下”布置中使用晶圆载具组件51，从而在切割期间保护插入组件11。
在图6中，示出了沿图5的线6-6′的横截面图。通过位于该图案化固定件顶部的预成形胶带图案化和制造固定件55，然后，将具有管芯的插入晶圆置于具有预成型胶带的以上固定件中。然后，实施层压步骤，从而在结合的插入件和固定件上层压切割胶带53。例如，该胶带可以为具有粘合剂的切割胶带。在备选实施例中，切割胶带可以为UV去除胶带(具有粘合剂最初非常强，但是UV曝光时失去强度，从而使得通过在切割以后的UV曝光，胶带失去粘合强度，在切割以后容易释放)。在晶圆载具组件51上将固定件55图案化，从而填充位于衬底13上的管芯24和25之间的间隙(在图6中以59示出)，并且该固定件足够厚，从而填充在管芯24和25之间的区域中的空间，该空间形成在胶带53和衬底13之间。还示出了设置在晶圆载具组件51的边缘处的固定件55，当通过管芯“向下”并且面对胶带将该胶带安装至衬底13时，该固定件对应于没有集成电路管芯的衬底13的边缘。可以作为固定件55的一部分提供预成形胶带层57，从而确保该胶带层到达衬底13，并且在随后切割时，用作切割胶带和支撑件。固定件55可以为适用于晶圆加工的有机或无机材料，例如，不锈钢、硅、陶瓷、聚合物、胶带、膜、或者其他材料。预成形胶带57可以为传统切割胶带、双面胶带或者UV固化胶带、或者其他材料。
图7示出了通过插入组件使用的晶圆载具组件51的横截面图，该插入组件包括衬底13、具有安装在衬底13的管芯侧面上的集成电路管芯24、25(现在，作为底面绘制)、并且具有位于衬底13的相对侧面上的焊料球33。示出了与在管芯24、25之间的空间对准的切割刀片43。注意，具有预成形胶带57的固定件55填充在晶圆载具组件51的胶带53和衬底13之间的垂直间隙。该厚度对应于管芯厚度并且例如，该厚度可以为用于600微米厚度的管芯的500微米-600微米。其他厚度可以用于填充其他管芯厚度的垂直空间。在通过部分59填充的管芯之间的间隙可以为1-2微米或者更大，通常在1-20微米的范围内，但是间隙尺寸不仅限于本实施例，无论使用什么空间，将具有预成形胶带57的固定件55图案化，从而填充管芯之间的水平空间。
在图7中，在横截面图中示出了载具框14，如在晶圆加工领域中已知的，可以将晶圆载具组件51安装至载具框，从而提供易处理。切割刀片43在湿切割操作中在划片槽区域中切割衬底13，该划片槽区域位于焊料球33之间和对应于管芯24和25之间的间隙，并且晶圆载具组件51在切割期间共同保护多部分，防止在切割期间损害衬底13、焊料球33、以及集成电路管芯24、25。晶圆载具组件51还提供了远离切割台传输器件的简单方法。在实施例中，晶圆载具组件51包括：UV去除切割胶带，并且在切割以后使用UV能量，从而将粘合剂强度改变为非常低的强度，从而使得将衬底13的现在分离部分，相应管芯24、25，以及相应焊料球33划分为独立组件。可以拾取和放置装置用于在切割以后，将完成的组件与晶圆载具组件51物理分离。
图8示出了使用如上所述的晶圆载具组件的方法实施例的流程图。在步骤61中，提供了具有相对于插入件的管芯位置的图案的胶带。在步骤63中，将固定件设置在胶带上方。在步骤65中，通过管芯侧面向下将插入组件安装在晶圆载具组件上。在步骤67中，实施切割操作，并且通过在位于衬底的焊料凸块侧面上的划片槽区域中切割衬底进行该切割。在步骤69中，独立插入组件与晶圆载具组件分离。在备选实施例中，该步骤可以包括：施加给胶带的UV能量(如果该胶带为UV去除胶)，从而降低了粘着强度，在拾取和放置或者其他传递操作以前，从晶圆载具去除独立组件。
图9示出了晶圆载具71的另一实施例。在该实施例中，例如，晶圆载具可以为切割胶带、背部研磨胶带、或者用在晶圆加工中的其他胶带。晶圆载具71具有对应于衬底13的尺寸，例如，如果衬底13为300微米(12英寸)半导体晶圆，则晶圆载具为相应尺寸。然而，通过任何衬底尺寸或者其他衬底尺寸使用实施例，该任何衬底尺寸包括3英寸、8英寸、或者半导体晶圆的其他尺寸。
图10示出了通过图9的实施例使用的固定件73的横截面图。如下文中详细描述的，在图9的晶圆载具具有安装至该晶圆载具的插入组件以后，使用固定件73，并且固定件73位于晶圆载具71的侧面上，该侧面与粘附至插入组件的管芯侧面的侧面相对。在该选择中，然后，在将插入组件安装至晶圆载具71以后，施加固定件73。
图11示出了晶圆载具71和配置在管芯侧面向下位置中并且安装在晶圆载具71上的衬底13、集成电路管芯24、25、以及焊料球33的横截面图。晶圆载具71粘附至集成电路管芯24和25的暴露侧面，和位于管芯之间的间隙中，或者在没有集成电路管芯的情况下，位于衬底13的边缘区域；晶圆载具71与衬底13接触。然后，固定件73具有多部分，该多部分配合集成电路管芯24、25之间的间隙，和在没有安装集成电路的情况下，还填充衬底13的边缘处的空间。
在图11中，示出了为切割刀片的刀片43，该刀片位于衬底13的焊料球侧面上。在切割操作期间，刀片旋转湿切割刀片，该刀片在划片槽区域中切割衬底13，将插入组件划分为如上所述的独立元件。固定件73在切割操作期间支撑插入组件，预防了与使用传统方法进行切割的相关问题。
图12示出了使用在图9和图10的载具和固定件实施例的方法实施例的流程图。在步骤81中，提供了晶圆载具，该晶圆载具由诸如切割胶带或背部研磨胶带的图案化胶带形成。在步骤83中，将胶带粘附至插入组件的晶圆侧面，该胶带在集成电路管芯之间延伸至衬底，并且覆盖集成电路管芯的暴露侧面。在步骤85中，将固定件73安装在集成电路管芯之间的胶带的相对侧面上，并且填充在衬底的边缘处的空间，从而制造平面并且在晶圆之间和在边缘处支撑薄化晶圆衬底。在步骤87中，实施切割操作，从而在划片槽区域中切割衬底。在步骤89中，独立组件与晶圆载具分离。如果所使用的胶带为UV去除的，则可以首先进行UV曝光从而减小粘着强度，然后可以去除子组件(sub-assembly)。
在实施例中，方法包括：接收包括一个或多个集成电路管芯的插入组件，该一个或多个集成电路管芯被安装在插入衬底的管芯侧面上，并且具有限定在集成电路管芯之间的空间中的划线区域；将插入组件的管芯侧面安装在胶带组件上，该胶带组件包括胶带和间隔件，该间隔件位于集成电路管芯之间并且填充集成电路管芯之间的间隙；以及通过切割划线区域切割插入组件。在另一实施例中，实施以上方法，其中，插入组件包括位于插入组件的相对侧面上的焊料凸块连接。在又一实施例中，实施以上方法，并且该方法进一步包括：在切割以后，胶带组件暴露在UV能量源之下。在又一实施例中，实施以上方法，其中，插入衬底为硅晶圆。在又一实施例中，在以上方法中，插入衬底包括：通过插入衬底延伸的一个或多个衬底通孔(TSV)。在又一实施例中，插入衬底薄至小于200微米的厚度。
在又一实施例中，实施以上方法，其中，将插入组件的管芯侧面安装至胶带组件进一步包括：以与位于插入衬底的管芯侧面上方的集成电路管芯的之间的间隙相对应的图案将隔离件安装至胶带；以及将胶带和隔离件安装在插入衬底的管芯侧面上，该隔离件填充集成电路管芯之间的间隙。
在另一实施例中，实施以上方法中的任何一种，其中，将插入组件的管芯侧面安装至胶带组件进一步包括：将胶带安装在插入衬底的管芯侧面的上方，该胶带延伸到在集成电路管芯之间的间隙中；以及将预成形隔离件安装在管芯之间的胶带的上方。在又一实施例中，实施以上方法中的任何一种，并且以上方法进一步包括：在切割步骤以后，从插入组件释放胶带。
在又一备选实施例中，方法包括接收插入组件，插入组件包括：衬底；形成在衬底中的多个衬底通孔；以及安装在衬底上的多个集成电路管芯，其中，在集成电路管芯之间的空间中形成划线区域；将胶带组件安装在插入组件上，胶带组件包括胶带层和隔离件，该隔离件被设置在集成电路管芯之间的间隙中；以及通过划线区域切割插入组件。在另一实施例中，实施以上方法，其中，将多个集成电路管芯分组为多个电路，该多个电路均包括彼此连接的至少两个集成电路管芯。在又一实施例中，实施以上方法，其中，至少两个集成电路管芯具有不同厚度。在又一实施例中，实施以上方法，其中，至少两个集成电路管芯具有不同功能。在又一实施例中，实施以上方法，其中，胶带组件具有与插入组件的衬底相对应的尺寸。在又一实施例中，实施以上方法中的任何一种，其中，隔离件中的至少一个具有小于等于集成电路管芯的最大厚度的厚度。在又一实施例中，实施以上方法，其中，将胶带组件安装至插入组件包括：将胶带层安装在集成电路管芯上，该胶带层延伸到在集成电路管芯之间的间隙；以及将隔离件安装在集成电路管芯之间的间隙中的胶带层的上方。
在另一实施例中，装置包括：多个集成电路管芯，被安装在插入件的管芯侧面上，集成电路管芯具有位于集成电路管芯之间的间隙；外部连接件，被安装在插入件的相对侧面上；以及隔离件，位于插入件的相对侧面上方的集成电路管芯之间的间隙中。在又一实施例中，以上装置进一步包括：胶带层，位于隔离件和插入件之间。在又一实施例中，提供了以上装置，其中，插入件为选自由硅衬底和玻璃衬底所组成的组中的一个。在另一实施例中，以上任何装置通过插入件延伸，其中，该插入件包括：一个或多个衬底通孔。
本申请的范围并不仅限于本说明书中描述的结构、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明的公开，现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺或步骤的范围内。

Claims (10)

1.一种方法，包括：
接收包括一个或多个集成电路管芯的插入组件，所述一个或多个集成电路管芯被安装在插入衬底的管芯侧上，并且在所述集成电路管芯之间的空间中限定有划线区域；
将所述插入组件的管芯侧安装在胶带组件上，所述胶带组件包括：胶带和隔离件，位于所述集成电路管芯之间并且填充所述集成电路管芯之间的间隙；以及
通过切割所述划线区域切割所述插入组件。
2.根据权利要求1所述的方法，其中，所述插入组件包括：焊料凸块连接件，位于所述插入组件的相对侧面上。
3.根据权利要求1所述的方法，进一步包括：
在所述切割以后，使所述胶带组件暴露在UV能量源之下。
4.根据权利要求1所述的方法，其中，所述插入衬底为硅晶圆。
5.根据权利要求1所述的方法，其中，所述插入衬底包括：一个或多个衬底通孔TSV，延伸通过所述插入衬底。
6.根据权利要求1所述的方法，其中，将所述插入衬底去薄至小于200微米的厚度。
7.根据权利要求1所述的方法，其中，将所述插入组件的管芯侧安装至胶带组件上的步骤进一步包括：
以与位于所述插入衬底的管芯侧上的所述集成电路管芯之间的间隙相对应的图案将隔离件安装在胶带上；以及
将所述胶带和所述隔离件安装在所述插入衬底的管芯侧上，所述隔离件填充所述集成电路管芯之间的间隙。
8.根据权利要求1所述的方法，其中，将所述插入组件的管芯侧安装在胶带组件上的步骤进一步包括：
将胶带安装在所述插入衬底的管芯侧上，所述胶带延伸进入所述集成电路管芯之间的间隙中；以及
将预成形的隔离件安装在所述管芯之间的所述胶带上。
9.一种方法，包括：
接收插入组件，所述插入组件包括：衬底；多个衬底通孔，形成在所述衬底中；以及多个集成电路管芯，安装在所述衬底上，其中，在所述集成电路管芯之间的空间中形成划线区域；
将胶带组件安装在所述插入组件上，所述胶带组件包括：胶带层和隔离件，位于所述集成电路管芯之间的间隙中；以及
经由所述划线区域切割所述插入组件。
10.一种装置，包括：
多个集成电路管芯，安装在插入件的管芯侧面上，所述集成电路管芯之间具有间隙；
外部连接件，安装在所述插入件的相对侧上；以及
隔离件，位于所述插入件的管芯侧上的所述集成电路管芯之间的间隙中。
CN201110344851.4A 2011-07-05 2011-11-03 用于切割插入组件的装置和方法 Active CN102867783B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/176,606 US8501590B2 (en) 2011-07-05 2011-07-05 Apparatus and methods for dicing interposer assembly
US13/176,606 2011-07-05

Publications (2)

Publication Number Publication Date
CN102867783A true CN102867783A (zh) 2013-01-09
CN102867783B CN102867783B (zh) 2014-11-12

Family

ID=47438168

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110344851.4A Active CN102867783B (zh) 2011-07-05 2011-11-03 用于切割插入组件的装置和方法

Country Status (2)

Country Link
US (3) US8501590B2 (zh)
CN (1) CN102867783B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298684A (zh) * 2015-06-23 2017-01-04 艾马克科技公司 半导体装置及其制造方法
CN108231602A (zh) * 2016-12-12 2018-06-29 台湾积体电路制造股份有限公司 具有填充单元的半导体装置的布局方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8580683B2 (en) 2011-09-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for molding die on wafer interposers
US8501590B2 (en) 2011-07-05 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for dicing interposer assembly
US8841752B1 (en) * 2011-09-27 2014-09-23 Xilinx, Inc. Semiconductor structure and method for interconnection of integrated circuits
US8828848B2 (en) * 2011-12-16 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Die structure and method of fabrication thereof
US9006908B2 (en) * 2012-08-01 2015-04-14 Marvell Israel (M.I.S.L) Ltd. Integrated circuit interposer and method of manufacturing the same
JP5835195B2 (ja) * 2012-11-29 2015-12-24 東京エレクトロン株式会社 乾燥処理用の高圧容器の製造方法及び基板処理装置の製造方法
KR101622453B1 (ko) * 2014-01-22 2016-05-31 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9837278B2 (en) * 2014-02-27 2017-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Wafer level chip scale package and method of manufacturing the same
US10090236B2 (en) * 2016-01-13 2018-10-02 Advanced Micro Devices, Inc. Interposer having a pattern of sites for mounting chiplets
WO2019054338A1 (ja) * 2017-09-12 2019-03-21 日本碍子株式会社 チップ部品の製造方法
CN110265336B (zh) * 2019-06-28 2024-05-24 日月新半导体(昆山)有限公司 集成电路装置
US11764672B1 (en) * 2022-06-28 2023-09-19 Diodes Incorporated Signal boosting in serial interfaces

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135785A (ja) * 1999-11-08 2001-05-18 Seiko Epson Corp 半導体チップ、マルチチップパッケージ、半導体装置、および電子機器、並びにこれらの製造方法
WO2005004216A1 (ja) * 2003-07-08 2005-01-13 Lintec Corporation ダイシング・ダイボンド用粘接着シートおよび半導体装置の製造方法
US20050194674A1 (en) * 2004-03-02 2005-09-08 Jochen Thomas Integrated circuit with re-route layer and stacked die assembly
US20060211220A1 (en) * 2003-05-12 2006-09-21 Tokyo Seimitsu Co., Ltd. Method and device or dividing plate-like member
CN101101884A (zh) * 2006-07-07 2008-01-09 奇梦达股份公司 具有堆叠芯片的半导体器件以及制造该器件的方法
CN102015943A (zh) * 2008-03-07 2011-04-13 3M创新有限公司 具有图案化背衬的切割带和晶粒附连粘合剂

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
EP1491927B1 (en) 2002-04-01 2013-02-27 Ibiden Co., Ltd. Ic chip mounting substrate, and ic chip mounting substrate manufacturing method
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JP4689375B2 (ja) 2005-07-07 2011-05-25 富士通株式会社 積層基板および該積層基板を有する電子機器
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7859098B2 (en) * 2006-04-19 2010-12-28 Stats Chippac Ltd. Embedded integrated circuit package system
US7999383B2 (en) 2006-07-21 2011-08-16 Bae Systems Information And Electronic Systems Integration Inc. High speed, high density, low power die interconnect system
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US7763965B2 (en) 2007-09-25 2010-07-27 International Business Machines Corporation Stress relief structures for silicon interposers
US20090321861A1 (en) * 2008-06-26 2009-12-31 Micron Technology, Inc. Microelectronic imagers with stacked lens assemblies and processes for wafer-level packaging of microelectronic imagers
US8866301B2 (en) 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US8338945B2 (en) 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US8580683B2 (en) * 2011-09-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for molding die on wafer interposers
US8501590B2 (en) * 2011-07-05 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for dicing interposer assembly
US8617935B2 (en) 2011-08-30 2013-12-31 Freescale Semiconductor, Inc. Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135785A (ja) * 1999-11-08 2001-05-18 Seiko Epson Corp 半導体チップ、マルチチップパッケージ、半導体装置、および電子機器、並びにこれらの製造方法
US20060211220A1 (en) * 2003-05-12 2006-09-21 Tokyo Seimitsu Co., Ltd. Method and device or dividing plate-like member
WO2005004216A1 (ja) * 2003-07-08 2005-01-13 Lintec Corporation ダイシング・ダイボンド用粘接着シートおよび半導体装置の製造方法
US20050194674A1 (en) * 2004-03-02 2005-09-08 Jochen Thomas Integrated circuit with re-route layer and stacked die assembly
CN101101884A (zh) * 2006-07-07 2008-01-09 奇梦达股份公司 具有堆叠芯片的半导体器件以及制造该器件的方法
CN102015943A (zh) * 2008-03-07 2011-04-13 3M创新有限公司 具有图案化背衬的切割带和晶粒附连粘合剂

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298684A (zh) * 2015-06-23 2017-01-04 艾马克科技公司 半导体装置及其制造方法
CN108231602A (zh) * 2016-12-12 2018-06-29 台湾积体电路制造股份有限公司 具有填充单元的半导体装置的布局方法
CN108231602B (zh) * 2016-12-12 2021-05-14 台湾积体电路制造股份有限公司 半导体装置的布局方法及用以执行该方法的可读取媒体

Also Published As

Publication number Publication date
US8501590B2 (en) 2013-08-06
US20130009316A1 (en) 2013-01-10
CN102867783B (zh) 2014-11-12
US10269731B2 (en) 2019-04-23
US8946893B2 (en) 2015-02-03
US20150145133A1 (en) 2015-05-28
US20130285241A1 (en) 2013-10-31

Similar Documents

Publication Publication Date Title
CN102867783B (zh) 用于切割插入组件的装置和方法
US8580683B2 (en) Apparatus and methods for molding die on wafer interposers
CN109003961B (zh) 一种3d系统集成结构及其制造方法
EP2015359B1 (en) Process for manufacturing a semiconductor package and circuit board substrate
KR20160030861A (ko) 반도체 장치의 제조 방법
KR20060132450A (ko) 반도체 장치의 제조 방법, 반도체 장치, 회로 기판 및 전자기기
WO2015109157A1 (en) Fine pitch bva using reconstituted wafer for area array at the top for testing
CN103165531B (zh) 管芯结构及其制造方法
CN115206900B (zh) 以增加的良率制造半导体装置模块的方法
TWI822369B (zh) 製造堆疊封裝式半導體封裝的方法
US20130241057A1 (en) Methods and Apparatus for Direct Connections to Through Vias
US9478472B2 (en) Substrate components for packaging IC chips and electronic device packages of the same
US8470641B2 (en) Exposed mold
US8652939B2 (en) Method and apparatus for die assembly
KR20160135688A (ko) 박형 샌드위치 임베디드 패키지
KR102078848B1 (ko) 멀티 칩 적층 패키지들을 제조하는 방법
CN106531638B (zh) 包括堆叠的半导体裸芯块的半导体装置及其制造方法
JP4334397B2 (ja) 半導体装置及びその製造方法
US20090014874A1 (en) Semiconductor apparatus and manufacturing method of semiconductor apparatus
CN107342269A (zh) 一种半导体封装方法及封装结构
CN103378015B (zh) 半导体芯片与封装结构以及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant