TWI761342B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI761342B
TWI761342B TW106115615A TW106115615A TWI761342B TW I761342 B TWI761342 B TW I761342B TW 106115615 A TW106115615 A TW 106115615A TW 106115615 A TW106115615 A TW 106115615A TW I761342 B TWI761342 B TW I761342B
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Taiwan
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substrate
substrate portion
trench
encapsulation
forming
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TW106115615A
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TW201834163A (zh
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金何松
古永炳
康德本
李宰金
金俊東
金東尙
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美商艾馬克科技公司
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Abstract

本發明揭示一種具有EMI屏蔽功能的半導體封裝以及其製造方法。在一實施例中，半導體封裝的製造方法包括：形成基板；將半導體裝置附接至基板的頂部；使用囊封物囊封半導體裝置；在囊封物中形成溝槽；以及在囊封物的表面上形成屏蔽層。

Description

半導體封裝及其製造方法
本揭示的某些實施例涉及半導體封裝，並且更特別地涉及形成包括多個半導體晶粒的半導體封裝。
各種電子設備可包括具有各種結構的半導體裝置以及電子裝置以用於交換各種訊號，其中半導體裝置和電子裝置在操作期間會發射電磁波。
電磁波會干擾半導體裝置和電子裝置的操作，因為這些裝置會非常靠近地一起安裝在主機板上。據此，屏蔽電磁波的結構和/或方法是有需要的。
通過比較此些系統與如在本申請案中參照附圖的其餘部分闡述的本揭示的某些態樣，對於在該領域中習知此技術者而言，常規和傳統方法的進一步限制和缺點將變得顯而易見。
本發明的半導體封裝以及其製造方法大致上示於附圖的至少一者中和/或結合附圖的至少一者來描述，並在申請專利範圍中進行更完整的闡述。
本揭示的各種優點、態樣和新穎性特徵，以及其實施例所例 示的細節，將從下面的描述和附圖而更充分地理解。
10‧‧‧支撐層
10’‧‧‧支撐層
20‧‧‧第一載體
100‧‧‧半導體封裝
110‧‧‧基板
110’‧‧‧基板
111‧‧‧第一基板部分
111’‧‧‧第一基板部分
112‧‧‧第一多層傳導結構
112a‧‧‧第一傳導層
112b‧‧‧第二傳導層
112c‧‧‧第三傳導層
113‧‧‧第一多層介電結構
113a‧‧‧第一介電層
113b‧‧‧第二介電層
113c‧‧‧第三介電層
115‧‧‧第二基板部分
116‧‧‧第二多層傳導結構
117‧‧‧第二多層介電結構
121‧‧‧電子裝置
122‧‧‧半導體晶粒
123‧‧‧傳導凸塊
124‧‧‧底部填充物
125‧‧‧電子裝置
126‧‧‧第三半導體裝置
130‧‧‧囊封物
131‧‧‧溝槽
140‧‧‧屏蔽層
150‧‧‧傳導凸塊
200‧‧‧半導體封裝
210‧‧‧基板
210’‧‧‧基板
211‧‧‧絕緣層
212‧‧‧第一電路圖案
213‧‧‧第二電路圖案
214‧‧‧第一介電層
215‧‧‧第二介電層
216‧‧‧導電通孔
230‧‧‧囊封物
231‧‧‧溝槽
240‧‧‧屏蔽層
圖1A至圖1J是根據本揭示的實施例依序地例示半導體封裝的製造方法的製程步驟的截面圖。
圖2A至圖2H是根據本揭示的另一實施例依序地例示半導體封裝的製造方法的製程步驟的截面圖。
圖3A至圖3G是根據本揭示的又另一實施例依序地例示半導體封裝的製造方法的製程步驟的截面圖。
本發明的實施例不應被解釋為限於本文所闡述的描述。相反地，這些實施例被提供作示例(諸如(但不限於)，一形狀所投影的表面的變化、投影到此表面上的入射角的變化、所投影的元件的性質和結構的變化…等等)，以使本發明更為詳盡和完整，並且將向本領域技術人員充分地表達本發明的範圍。所附申請專利範圍說明本揭示的一些實施例。
在以下討論中，「舉例而言」、「例如」、「範例性」等詞是非限制性的，並且一般而言與「舉例來說而無限制」、「舉例而言且無限制」和類似者同義。
如在此所用，「和/或」意謂由「和/或」結合所列的項目當中任一或更多者。舉例來說，「x和/或y」意謂三元素組{(x)、(y)、(x，y)}當中的任一元素。換言之，「x和/或y」意謂「x和y當中一或二者」。舉另一例來說，「x、y和/或z」意謂七元素組{(x)、(y)、(z)、(x，y)、(x，z)、(y，z)、(x，y，z)}當中的任一元素。換言之，「x、y和/或z」意謂「x、y和z當中 一或更多者」。
在此所用的辭彙只是為了描述特殊的範例，並且不打算限制本揭示。如在此所用，單數形式打算也包括複數形式，除非上下文明確另有所指。將進一步了解「包括」、「包含」、「含有」、「具有」、「擁有」、「有」和類似的詞當用於本說明書時指定存在了所述的特色、事物、步驟、操作、元素和/或元件，但不排除存在或添加了一或更多個其他的特色、事物、步驟、操作、元素、元件和/或其群組。
將了解雖然第一、第二…等詞可以在此用於描述各種元件，但是這些元件不應該受限於這些詞。這些詞只是用來區分某一元件與另一元件。因此，舉例而言，第一元件、第一構件或第一區段或可稱為第二元件、第二元件或第二區段，而不偏離本揭示的教導。類似而言，各種空間用語(譬如「上」、「上面」、「下」、「下面」、「側」、「橫向」、「水平」、「垂直」和類似者)可以用於以相對方式來區分某一元件與另一元件。然而，應該了解元件可以採取不同的方式來指向；舉例而言電子裝置可以轉向側邊，如此則其「頂面」面向水平方向並且其「側面」面向垂直方向，而不偏離本揭示的教導。
亦應該瞭解，「耦接」、「連接」、「附接」…等等的術語包括直接和間接的(例如，具有中間元件)「耦接」、「連接」、「附接」…等等，除非另有明確說明。舉例而言，如果元件A被稱為耦合到元件B，則元件A可以通過中間結構間接耦合到元件B、元件A也可以直接耦合到元件B…等等。
在附圖中，為了清楚起見，裝置、結構、層、區域…等等的 尺寸(例如，絕對和/或相對尺寸)可能被誇大。雖然這樣的尺寸通常是用來代表示例性實作，但它們不是限制性的。舉例而言，如果結構A被例示為大於結構B，則這通常是用來代表示例性實作，但是結構A通常不需要大於結構B，除非另有說明。另外，在附圖中，相同的附圖標記可以在整個討論中指代相同的元件。
在整個說明書中，相同的附圖標記表示相同的元件。包括本文所使用的描述性或技術性術語的所有術語應被解釋為具有對於該領域中習知此技術者而言是顯而易見的含義。當術語由於語言、先例或新技術的演變而具有含糊的含義時，本揭示中使用的術語的含義應該首先通過本揭示中的用法和/或定義來澄清。那麼，該術語應該會因為該領域中習知此技術者在閱讀本揭示時理解該術語而被闡明。
當部件“包括”或“包含”元件時，除非有與之相反的特定描述，否則該部件還可以包括其它元件。在本揭示的實施例中的術語“單位(unit)”意指執行特定功能的軟體構件或硬體構件。由“單元”提供的功能可以分為附加的構件和“單元”。舉例而言，硬體構件可包括現場可程式化邏輯陣列(FPGA)或特殊應用積體電路(ASIC)。
現在將詳細參考實施例，而實施例的示例會在附圖中例示。就此而言，本發明的實施例可以具有不同的形式，並且不應被解釋為限於本文所闡述的描述。
在下面的描述中，已知的功能或結構未被詳細描述，以防不必要的細節模糊了本發明的實施例。
在附圖中，為了容易和清楚的目的，在本公開的描述中各層 的厚度或尺寸可能會被誇大，並且相同的附圖標記將在本文中被使用來表示相同或相似的元件。
根據本揭示的態樣，提供一種製造半導體封裝的方法，其包括：形成基板；將第一半導體裝置附接至基板的頂部；使用囊封物囊封第一半導體裝置；在囊封物中形成溝槽；以及在囊封物的表面上形成屏蔽層。
根據本揭示的另態樣，提供一種製造半導體封裝的方法，其包括：在(舉例而言)諸如晶圓的支撐層上形成第一基板；將半導體裝置附接至第一基板的頂部；使用囊封物囊封半導體裝置；在囊封物中形成溝槽；在囊封物的表面上形成屏蔽層；以及在第一基板上形成第二基板。
根據本揭示的又另一態樣，提供一種半導體封裝，其包括：基板；半導體裝置，其被附接至基板；囊封物，其囊封基板上的半導體裝置；以及屏蔽層，其被形成在囊封物的表面上。
如上面所述，在根據本揭示的實施例的半導體封裝和其製造方法中，在形成半導體裝置和囊封物於基板上之後，溝槽被形成在囊封物上，並且屏蔽層被形成在囊封物的表面上，以屏蔽半導體封裝的五個表面。據此，可防止在囊封物中的半導體裝置的至少一者所產生的電磁波發射到外部。此外，可防止外部產生的電磁波穿透進入囊封物中的半導體裝置的至少一者。
因為在形成溝槽時不使用黏合膠帶來保持多個半導體裝置，所以在形成溝槽時沒有要切割的黏合膠帶。因此，不會有膠帶毛邊(tape burr)也不會有膠帶剝離以暴露基板和載體之間的間隙。
當(舉例而言)新的黏合膠帶被放置在具有膠帶毛邊的現有 的膠帶上方時，膠帶毛邊可能是有問題的。膠帶毛邊會防礙新的膠帶適當地黏合至現有的膠帶。因此，當新的膠帶被移除時，可能會有一些現有膠帶無法被移除。這被稱為殘留現象。
暴露間隙的被剝離的膠帶亦可以是有問題的，因為在屏蔽層被形成時一些屏蔽材料會進入該間隙。這被稱為逆溢料(backspill)現象。
然而，依據本揭示的各種實施例，因為在形成溝槽時不存在現有的黏合膠帶的切割，所以不會有黏合膠帶剝離也不會形成膠帶毛邊。因此，當形成屏蔽層時，由於沒有間隙穿透屏蔽材料，所以不會有任何逆溢料現象。此外，當(舉例而言)黏合膠帶被施加在傳導凸塊周圍並且稍後移除時，黏合膠帶將由於沒有膠帶毛邊而被適當地移除而不留下膠帶殘留。因此，半導體封裝的可靠度由於缺少逆溢料現象和殘留現象的緣故而被改善。
現在將詳細參考本揭示的各種示例性實施例。
圖1A至圖1J是根據本揭示的實施例依序地例示半導體封裝的製造方法的製程步驟的截面圖。
根據本揭示的實施例的半導體封裝的製造方法包括以下製程步驟：形成基板110；將電子裝置121、125附接到基板110；利用囊封物130囊封在基板110上的電子裝置121、125；在囊封物130周圍形成屏蔽層140；以及在基板110的底部上形成傳導凸塊150。儘管第一電子裝置121通常被例示和討論為半導體裝置(例如，積體電路、處理器、記憶體、特殊應用積體電路、離散邏輯裝置、可程式化邏輯裝置…等等)，並且第二電子裝置125通常被例示和討論為被動裝置(例如，電阻器、電容器、電感 器…等等)，但是本揭示的範圍不受到此些範例裝置的限制。舉例而言，第一電子裝置121和第二電子裝置125可各自包括任何類型的裝置，無論是主動裝置或被動裝置。
基板110包括形成在支撐層10上的第一基板部分111和形成在第一基板部分111上的第二基板部分115。第一基板部分111也可以被稱為第一基板，並且第二基板部分115也可以被稱為第二基板。舉例而言，支撐層10可以是晶圓、面板、載體、支撐結構...等等。
如圖1A中所示，第一基板部分111包括第一多層傳導結構112以及覆蓋第一多層傳導結構112的部分的第一多層介電結構113。經組合的第一多層傳導結構112和第一多層介電結構113也可以被稱為多層信號分佈結構、多層信號再分佈結構、多級(multi-level)再分佈層…等等。
圖1B(其是圖1A的部分“A”的放大圖)示出第一基板部分的第一傳導層112a形成在支撐層10上。第一傳導層112a的部分被第一傳導層113a所覆蓋。接著，第二傳導層112b被形成以電性連接第一傳導層112a。第二傳導層112b的部分被第二介電層113b所覆蓋。接著，第三傳導層112c被形成以電性連接第二傳導層112b。第三傳導層112c的部分被第三介電層113c所覆蓋。儘管第一多層傳導結構112在圖1B被例示為具有三層，但是第一多層傳導結構112可以具有任何數量的層(例如，1、2、3、4…等等)。支撐層10可以由一種或多種合適的材料(例如，玻璃、金屬、塑料、諸如(舉例而言)矽(Si)的半導體材料...等等)所製成。然而，本揭示的態樣不限於此，並且支撐層10可以由本文未提到的其它合適材料所製成。
第一多層傳導結構112的傳導層112a、112b、112c可以由通過無電解電鍍、電解電鍍和/或濺鍍所產生的導體(舉例而言，諸如銅、鋁、金、銀、鈀和/或其等效物)所製成，但是本揭示的態樣不限於此。此外，第一多層傳導結構112的圖案化或繞線可以利用共同的光阻通過光刻製程進行，但是本揭示的態樣不限於此。注意到，不同的傳導層可以由相同的傳導材料或不同的傳導材料所製成。
第一多層介電結構113可以由絕緣材料所製成，舉例而言，諸如有機介電材料(例如聚合物，聚酰亞胺，苯並環丁烯，聚苯並噁唑…等等)及其等效物、無機介電材料(例如，氧化物、氮化物…等等)及其等效物、其任何組合…等等，但是本揭示的態樣不限於此。此外，第一多層介電結構113可以通過(舉例而言)旋塗、噴塗、浸塗、棒塗及其等效物所形成，但是本揭示的態樣不限於此。注意到，不同介電層可以由相同的介電材料或不同的介電材料所製成。
接下來，第一載體20可被附接到第一基板部分111的頂部(或頂側)，然後支撐層10可被移除。第一載體20可以由矽(Si)、玻璃、金屬…等等所製成，但是本揭示的態樣不限於此。第一載體20可用各種方式(例如，黏合劑層、雙面膠帶…等等)的任何一種被附接到第一基板部分111。大部分的支撐層10可被移除，而留下剩餘的支撐層10’，如圖1C所示。大部分的支撐層10可通過(舉例而言)背部研磨支撐層10的底表面被機械式地移除。這裡，背面研磨可使用(舉例而言)金剛石研磨器或其等效物進行，但是本揭示的態樣不限於此。如果合適的話，支撐層10也可以使用包括(舉例而言)雷射、流體噴流、化學手段…等等的其它方法來 移除。
如圖1D所示，可以通過(舉例而言)化學蝕刻移除剩餘的支撐層10’。如果合適的話，剩餘的支撐層10’也可以使用包括(舉例而言)雷射、流體噴流、化學手段…等等的其它方法來移除。
如圖1E所示，第二基板部分115被形成在第一基板部分111上，舉例而言在先前被支撐層10所覆蓋的第一基板部分111的一側上。對於此製程，第一載體20和第一基板部分111被倒置，使得第一基板部111在頂部。接著，第二基板部分115被形成在第一基板部分111上。第二基板部分115和/或其之形成可以與第一基板部分111和/或其之形成共用任何或全部特性。舉例而言，第二基板部分115可以包括第二多層傳導結構116，其可以與第一多層導電結構112共用任何或所有特性，以及覆蓋第二多層傳導結構112的第二多層介電結構117，其可以與第一多層介電結構113共用任何或所有特性。基板110可用這種方式完成。
如上面所述，可以通過從晶圓製造製程接收支撐層10並在封裝製程期間在支撐層10的表面上形成第一基板部分111來完成基板110。類似地，第二基板部分115也可以在封裝製程期間形成在第一基板部分111上。據此，可以在基板110上實現小的線寬(舉例而言，小於100μm)和細間距的互連(舉例而言，小於100μm)，藉此提供高密度的互連技術。以這種方式配置的基板110可以通過SWIFT(矽晶圓整合扇出技術(Silicon Wafer Integrated Fan-out Technology))製程形成。或者，也可以通過在晶圓製造製程期間在支撐層10上形成第一基板部分111並在封裝製程期間形成第二基板部分115來完成基板110。以這種方式配置的基板110可以通過SLIM (無矽整合模組(Silicon-Less Integrated Module))製程形成。據此，可以在基板110上實現小的線寬(舉例而言，小於100μm)和細間距的互連(舉例而言，小於100μm)，藉此提供高密度的互連技術。
圖1F例示了將電子裝置121和125附接到基板110的頂部(或側面)。第一和第二電子裝置121和125可電性連接到第二基板部分115的第二多層傳導結構116。在示例方法中，第一和第二電子裝置121和125可以通過質量回焊方法、熱壓接合方法、雷射接合方法或任何其它合適的方法電性連接到第二多層傳導結構116。
作為示例，第一電子裝置121(例如，半導體裝置)可以包括半導體晶粒122和多個傳導凸塊123，並且第二電子裝置125可以是被動裝置或主動裝置。這裡，半導體晶粒122可以包括電路，(舉例而言)諸如數位信號處理器(DSP)、微處理器、網路處理器、電源管理處理器、音頻處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器或特殊應用積體電路(ASIC)。半導體晶粒122也可以包括(舉例而言)記憶體，其可以包括揮發性和/或非揮發性記憶體。
第一電子裝置121可通過將多個傳導凸塊123電性連接到第二多層傳導結構116，然後將底部填充物124注入到半導體晶粒122和第二基板部分151之間的區域中，被穩固地附接到第二基板部分115。底部填充物124可以改善第一電子裝置121和第二基板部分115之間的機械結合強度，同時保護多個傳導凸塊123。舉例而言，多個傳導凸塊123可以包括(但不限於)焊料凸塊、導電支柱(例如，銅支柱)、導電柱(例如，銅柱)、具有焊料的導電支柱、具有焊料的導電柱以及等效物，但是本揭示的態樣 不限於此。此外，底部填充物124可以由(舉例而言)環氧樹脂、熱硬化性材料、熱固化性材料、聚酰亞胺、聚氨酯、聚合材料、填充環氧樹脂、填充熱硬化性材料、填充的熱固化性材料、填充聚酰亞胺、填充聚氨酯、填充聚合物材料、助焊劑底部填充物(fluxed underfill)以及其等效物，但是本揭示的態樣不限於此。第二電子裝置125可用類似方式被附接和/或底部填充。注意到，在本文所討論的囊封步驟期間，也可以通過模製的底部填充物進行此種底部填充。
如圖1G所示，基板110的頂部(或側邊)被囊封物130封裝(或覆蓋)。更特別地，被安裝在基板110上的電子裝置121和125被囊封物130囊封。囊封物130可以囊封電子裝置121和125，從而減輕外部影響或環境條件對電子設備121和125的損壞。某些實施例可以完全囊封，然而其他實施例可以部分囊封。因此，除非另有說明，否則“囊封”可以是完全囊封或部分囊封。舉例而言，囊封物130可以是用於一般轉印模製的環氧樹脂模製化合物、用於點膠(dispensing)可在室溫下固化的灌封物(glop top)(或塗封物(glob top))、旋塗囊封物及其等效物，但是本揭示的態樣不限於此。
為了形成屏蔽層140(或傳導層)，溝槽131被形成在囊封物130中，並且屏蔽層140被形成在囊封物130的表面上，包括在溝槽131的內壁(例如，側壁、底表面…等等)上。如圖1H所示，溝槽131被形成在囊封物130中。溝槽131被形成為穿過基板130和囊封物110直到第一載體20。因此，基板110可說是已被切割成幾個局部的基板110’。據此，局部的基板110’上的每組電子裝置121和125被實質上分成個別的半導體封 裝。然而，因為第一載體20位於囊封物130下面，所以局部的基板110’保持在第一載體20上。
接下來，屏蔽層140被形成在囊封物130的上表面和側表面、溝槽131的壁(例如，包括側壁、底表面…等等)和局部的基板110’的側表面上。溝槽131的壁也可以被視為是囊封物130的側表面。局部的基板110’的側表面和/或溝槽131的壁可以是實質上垂直的。然而，側表面和/或壁可具有其它形狀和/或指向，(舉例而言)例如傾斜的、階梯狀的、彎曲狀的…等等。
屏蔽層140可以舉例而言經由連接到接地的第一多層傳導結構112電性連接到被連接到接地的基板110的部分。因此，屏蔽層140可以屏蔽囊封物130，以防止從囊封物130中的電子裝置121和125中的至少一個產生的電磁波被發射到外部。此外，屏蔽層140也可以屏蔽囊封物中的電子裝置121和125，以免暴露於外部產生的電磁波。
屏蔽層140可以(舉例而言)通過噴塗、濺鍍、浸塗、旋塗…等等的方式在囊封物130的表面上塗覆混合有傳導金屬粉末的導電膏(或液體或其它類型的材料)的塗層來形成，但是本揭示的態樣不限於此。屏蔽層140可以由各種傳導材料(例如，金屬、傳導液體或膏狀物…等等)的任何一種來形成。注意到，可以在屏蔽層140上形成一個或多個其它層(例如，一個或多個傳導層和/或一個或多個介電層)。
如圖1H所示，屏蔽層140也可以在溝槽131的底部。在這種情況下，可能需要移除溝槽131底部的屏蔽層140的部分，以允許由溝槽131分離的相鄰封裝的分離。移除可能在任何時間而直到相鄰的封裝需要分 離的時間點發生，並且可以使用任何合適的方法，包括那些用於移除材料已經描述的方法。此種移除可(舉例而言)通過機械切割或研磨、化學蝕刻、雷射燒蝕…等等進行。
一些實施例可能不會在溝槽131的底部處形成屏蔽層140，因此不需要移除屏蔽層140的那部分。其他實施例可以具有溝槽131而延伸到第一載體20中，而不是如圖1H所示在第一載體20處停止。據此，即使溝槽131的底部具有屏蔽層，當第一載體20被移除時，也將移除溝槽131底部處的屏蔽層的部分。
在形成傳導凸塊150時，第一載體20被移除，並且傳導凸塊150被形成在局部的基板110’上。
首先，如圖11所示，第二載體30被附接到囊封物130的頂部上的屏蔽層140。定位在基板110下方的第一載體20接著利用一或多個在文中所描述的合適方法(例如，研磨和/或蝕刻、施加黏合劑脫膠溫度或其它能量、剝離、剪切…等等)移除。據此，第一基板部分111暴露到外部。傳導凸塊150被形成在第一基板部分111的第一多層傳導結構112上，以電性連接第一多層導電結構112。
因為第二載體30被附接到由溝槽131所分離的局部的基板110’的屏蔽層140，所以隨後的(多個)處理製程可以處理在它們局部的基板110’上的多組電子裝置121和125。
在一些實施例中，第三半導體裝置126可以在形成傳導凸塊150之前、期間和/或之後附接到第一基板部分111。在這裡，舉例而言，第三半導體裝置126被形成為具有比傳導凸塊150更小的高度。因此，根據本 揭示，局部的基板110’的頂表面和底表面可以具有附接到其上的電子裝置。
傳導凸塊150可以用(舉例而言)球柵陣列、平面柵格陣列、接腳格柵陣列或其他合適的傳導互連的形式來提供。此外，傳導凸塊150可以由(舉例而言)共晶焊料(Sn37Pb)、高鉛焊料(Sn95Pb)、無鉛焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu、SnAgBi…等等)及其等效物來形成，但是本揭示的態樣不限於此。舉例而言，傳導凸塊150可以是(但不限於)銅支柱或銅柱、銅芯焊料球…等等。
如圖1J所示，在形成傳導凸塊150之後，第二載體30被移除，從而完成個別的半導體封裝100。第二載體30可用各種方式(例如，研磨和/或蝕刻、施加黏合劑脫膠溫度或其它能量、剝離、剪切…等等)的任何一種移除。
通過上述製造方法所形成的半導體封裝100包括：局部的基板110’；電子裝置121和125，其附接到局部的基板110’的頂部；囊封物130，其囊封局部的基板110’上的電子裝置121和125；屏蔽層140，其形成在囊封物130的表面上和局部的基板110’的橫向的側表面上；以及傳導凸塊150，其附接到局部的基板110’的頂部。
如上面所述，根據本揭示的實施例的半導體封裝的製造方法包括：在支撐層10上形成基板110、電子裝置121和125以及囊封物130。接著，溝槽131被形成在囊封物130中(以及在各種實施例中的基板110中)，並且屏蔽層140被形成在囊封物130的表面上以屏蔽半導體封裝100的五個表面(四個側表面和頂表面)。因此，根據本揭示，屏蔽層140屏蔽 囊封物130，以防止從囊封物130中的電子裝置121和125中的至少一者產生的電磁波被發射到外部。此外，屏蔽層140也可以屏蔽囊封物中的電子裝置121和125，以免於暴露於外部產生的電磁波。據此，可以加以改善半導體封裝100的可靠性。
此外，根據本揭示，在形成通過囊封物130和基板110的溝槽131之後，屏蔽層140被形成在囊封物130上。然而，因為在被切割作為形成溝槽131的部分時沒有可能會剝離的黏合膠帶，所以沒有形成屏蔽層140的材料會穿透到基板110和第一載體20之間的區域中的逆溢料現象。這也可加以改善半導體封裝100的可靠性。
此外，根據本揭示，屏蔽層140可被形成，然後傳導凸塊150可被形成，然後新的黏合膠帶可被施加在傳導凸塊150周圍。由於新的黏合膠帶不會被放置在先前放置的黏合膠帶上，所以在形成溝槽131時不用擔心由於切割先前放置的黏合膠帶而可能形成的膠帶毛邊。據此，從傳導凸塊150周圍移除新的黏合膠帶將不會導致殘留現象。沒有這種殘留現象也可加以改善半導體封裝100的可靠性。
圖2A至圖2H是根據本揭示的另一實施例依序地例示半導體封裝的製造方法的製程步驟的截面圖。圖2A至圖2H所示的示例方法(或製程)或其方法步驟可以與圖1A至圖1J及在文中所討論的示例方法(或製程)或其方法步驟共用任何或所有特性。舉例而言，本文討論的各種示例方法中大致上類似的步驟可以共用材料和/或方法。
根據本揭示的另一實施例的半導體封裝的製造方法包括：在支撐層10上形成第一基板部分111；將電子裝置121、125附接到第一基板 部分111；利用囊封物130囊封在第一基板部分111上的電子裝置121、125；在囊封物130上形成屏蔽層140；在第一基板部分111上形成第二基板部分115；以及在第二基板部分210上形成傳導凸塊150。
圖2A至圖2H所示的製造方法與圖1A至圖1J所示的實質上相同，並且以下描述將集中在它們之間的差異。
如圖2A所示，第一基板部分111被形成在支撐層10上。第一基板部分111包括第一多層傳導結構112以及覆蓋被形成在支撐層10上的第一多層傳導結構112的第一多層介電結構113。圖2A所示的第一基板部分111(舉例而言)可以與圖1B所示的相同。舉例而言，第一基板部分111可以通過在支撐層10上形成第一傳導層112a並用第一介電層113a覆蓋第一傳導層112a的部分來完成。然後，第二傳導層112b可被形成以電性連接第一傳導層112a，並且第二傳導層112b的部分可被第二介電層113b覆蓋。此外，第三傳導層112c可被形成以電性連接第二傳導層112b，並且第三傳導層112c的部分可被第三介電層113c覆蓋。儘管第一多層傳導結構112在圖2A中被例示為具有三層，但是第一多層傳導結構112可以具有任何數量的層(例如，1、2、3、4…等等)。支撐層10可以由矽(Si)、玻璃和/或金屬所製成，但是本揭示的態樣不限於此。
如圖2B所示，電子裝置121和125被附接到第一基板部分111的頂部，並且電性連接到第一基板部分111的第一多層傳導結構112。作為示例，第一和第二電子裝置121和125可以通過質量回焊方法、熱壓接合方法、雷射接合方法或任何其它合適的方法電性連接到第一多層傳導結構112。
作為示例，第一電子裝置121(例如，半導體裝置)可以包括半導體晶粒122和多個傳導凸塊123，並且第二電子裝置125可以是被動裝置或主動裝置。這裡，半導體晶粒122可以包括電路，(舉例而言)例如數位信號處理器(DSP)、微處理器、網路處理器、電源管理處理器、音頻處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器或特殊應用積體電路(ASIC)。半導體晶粒122也可以包括(舉例而言)記憶體，其可以包括揮發性和/或非揮發性記憶體。
第一電子裝置121可通過將多個傳導凸塊123電性連接到第一多層傳導結構112，然後將底部填充物124注入到半導體晶粒122和第一基板部分111之間的區域中，被穩固地附接到第一基板部分111。底部填充物124可以改善第一電子裝置121和第一基板部分111之間的機械結合強度，同時保護多個傳導凸塊123。舉例而言，多個傳導凸塊123可以包括(但不限於)焊料凸塊、導電支柱(例如，銅支柱)、導電柱(例如，銅柱)、具有焊料的導電支柱，具有焊料的導電柱以及其等效物，但是本揭示的態樣不限於此。此外，底部填充物124可以由(舉例而言)環氧樹脂、熱硬化性材料、熱固化性材料、聚酰亞胺、聚氨酯、聚合材料、填充的環氧樹脂、填充的熱硬化性材料、填充的熱固化性材料、填充的聚酰亞胺、填充的聚氨酯、填充聚合物材料、助焊劑底部填充物以及其等效物，但是本揭示的態樣不限於此。第二電子裝置125可用類似方式被附接和/或底部填充。注意到，在本文所討論的囊封步驟期間，也可以通過模製的底部填充物進行此種底部填充。
如圖2C所示，第一基板部分111的頂部(或側邊)被囊封 物130囊封(或覆蓋)。更特別地，被安裝在第一基板部分111上的電子裝置121和125被囊封物130囊封。囊封物130囊封電子裝置121和125，從而減輕外部影響或環境條件對電子設備121和125的損壞。如本文中關於圖1G所討論的，某些實施例可以完全囊封，然而其他實施例可以部分囊封。因此，除非另有說明，否則“囊封”可以是完全囊封或部分囊封。舉例而言，囊封物130可以是用於一般轉印模製的環氧樹脂模製化合物、用於點膠可在室溫下固化的灌封物(或塗封物)、旋塗囊封物及其等效物，但是本揭示的態樣不限於此。
為了形成屏蔽層140(或傳導層)，溝槽131被形成在囊封物130中，並且屏蔽層140被形成在囊封物130的表面上，包括在溝槽131的內壁(例如，側壁、底表面…等等)上。如圖2D所示，溝槽131被形成在囊封物130中。溝槽131被形成為穿過囊封物130和第一基板部分111，並且進一步進入支撐層10中。因此，第一基板部分111可說是已被切割成幾個局部的第一基板部分111’。據此，局部的第一基板部分111’上的每組電子裝置121和125被實質上分成個別的半導體封裝。然而，因為支撐層10位於囊封物130下面，所以局部的基板部分111’被保持在支撐層10上。
接下來，屏蔽層140被形成在囊封物130的上表面和側表面、溝槽131的壁(例如，包括側壁、底表面…等等)和局部的第一基板部分111’的側表面上。溝槽131的壁也可以被視為是囊封物130的側表面。局部的第一基板部分111’的側表面和/或溝槽131的壁可以是實質上垂直的。然而，側表面和/或壁可具有其它形狀和/或指向，(舉例而言)例如傾斜的、階梯狀的、彎曲狀的…等等
屏蔽層140可以舉例而言經由連接到接地的第一多層傳導結構112的傳導跡線電性連接到被連接到接地的局部的第一基板部分111’的部分。因此，屏蔽層140可以屏蔽囊封物130，以防止從囊封物130中的電子裝置121和125中的至少一個產生的電磁波被發射到外部。此外，屏蔽層140也可以屏蔽囊封物中的電子裝置121和125，以免於暴露於外部產生的電磁波。
屏蔽層140可以(舉例而言)通過噴塗、濺鍍、浸塗、旋塗…等等的方式在囊封物130的表面上塗覆混合有傳導金屬粉末的導電膏(或液體或其它類型的材料)的塗層來形成，但是本揭示的態樣不限於此。
在形成第二基板部分115時，支撐層10被移除，並且第二基板部分115被形成在第一基板部分111上。屏蔽層140可以由任何傳導材料(例如，金屬、傳導液體或膏狀物…等等)的任何一種來形成。注意到，可以在屏蔽層140上形成一個或多個其它層(例如，一個或多個傳導層和/或一個或多個介電層)。
首先，舉例而言，第一載體20被附接到形成在囊封物130的頂部(或側邊)上的屏蔽層140，然後移除支撐層10。第一載體20可用各種方式(例如，黏合劑層，雙面膠帶…等等)的任何一種附接到屏蔽層140(或中間層)。如本文關於圖1C至圖1D所討論的，支撐層10可用多個步驟移除，或者也可以在單一步驟中移除。舉例而言，如圖2E所示，支撐層10的部分通過背面研磨支撐層10的底表面而將支撐層10的部分機械式地移除，留下剩餘的支撐層10’。這裡，背面研磨可使用(舉例而言)鑽石研磨器或其等效物進行，但是本揭示的態樣不限於此。也可使用前面描 述的任何各種其他方法。接下來，如圖2F所示，剩餘的支撐層10’可通過化學蝕刻移除，從而移除支撐層10。如本文所討論的，剩餘的支撐層10’也可以通過其它合適的方法移除。基板110可以由矽(Si)、玻璃和/或金屬所製成，但是本揭示的態樣不限於此。
接著，第二基板部分115被形成在局部的第一基板部分111’上。舉例而言，這樣的形成可以與關於圖1E所討論的第二基板部分115的形成共用任何或所有特性。具體地，如圖2G所示，局部的第一基板部分111’被翻轉以面向上，並且通過將光阻40(或介電材料或其它合適的材料)注入溝槽131來填充溝槽131。光阻40可(舉例而言)被注入到溝槽131中，以有助於後續的處理製程。接著，第二基板部分115被形成在局部的第一基板部分111’上以完成基板110。這裡，第二基板部分115包括第二多層傳導結構116和覆蓋第二多層傳導結構116的第二多層介電結構117，舉例而言用與第一基板部分111的第一多層傳導結構116和第一多層介電結構113相似(或相同)的方式。注意到，第二基板部分115可用在局部的第一基板部分111’上(包括在溝槽131中的光阻40和屏蔽層140上)形成整個連續的第二基板部分115的方式來形成，並且形成在光阻40和屏蔽層140上的部分可以接著被移除，以便在相對的局部的第一基板部分111’上產生相對的局部第二基板部分。或者，第二基板部分115可以是原本就僅形成在第一基板部分111’上，而不在光阻40和溝槽131的屏蔽層140之上。
接著，傳導凸塊150被形成在基板110上。如圖2G所示，傳導凸塊150被形成在第二基板部分115的第二多層傳導結構116上，以電 性連接第二多層導電結構116。傳導凸塊150可以用(舉例而言)球柵陣列，平面柵格陣列、接腳格柵陣列或其他合適的傳導互連的形式來提供。此外，傳導凸塊150可以由例如共晶焊料(Sn37Pb)、高鉛焊料(Sn95Pb)、無鉛焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu、SnAgBi…等等)及其等效物來形成，但是本揭示的態樣不限於此。舉例而言，傳導凸塊150可以是(但不限於)銅支柱或銅柱、銅芯焊料球…等等。
在一些實施例中，第三半導體裝置126可以在形成傳導凸塊150之前、期間和/或之後附接到第二基板部分115。在這裡，舉例而言，第三半導體裝置126被形成為具有比傳導凸塊150更小的高度。因此，根據本揭示，基板110的頂表面和底表面可以具有附接到其上的電子裝置。
接下來，如圖2H所示，在形成傳導凸塊時，第一載體20和光阻40被移除，從而完成個別的半導體封裝100。第一載體20可用各種方式(例如，研磨和/或蝕刻、施加黏合劑脫膠溫度或其它能量、剝離、剪切…等等)的任何一種移除。
通過上述製造方法所形成的半導體封裝100包括：基板110；電子裝置121和125，其附接到局部的基板110的頂部；囊封物130，其囊封基板上的電子裝置121和125；屏蔽層140，其形成在囊封物130的表面上和局部的基板110’的橫向的側表面上；以及傳導凸塊150，其附接到基板110的底部。舉例而言，如同圖1A至圖1J所示的示例方法以及在此討論的，可以使用圖2A至圖2H所示的示例方法來製造半導體封裝100。
圖3A至圖3G是根據本揭示的又另一實施例依序地例示半導體封裝的製造方法的製程步驟的截面圖。圖3A至圖3G所示的示例方法 (或製程)或其方法步驟可以與圖2A至圖2H所示的及/或圖1A至圖1J中所示的及在文中所討論的示例方法或其方法步驟共用任何或所有特性。舉例而言，本文討論的各種示例方法的大致上類似的步驟可以共用材料和/或方法。
根據本揭示的又另一實施例的半導體封裝的製造方法包括：形成基板210；將電子裝置121、125附接到基板210；利用囊封物230囊封基板210上的電子裝置121、125；在基板210上形成傳導凸塊150；以及在囊封物230上形成屏蔽層240。
在形成基板時，如圖3A所示，基板210被加以製備，基板210包括：平面絕緣層(核心層)211；形成在絕緣層211的頂表面上的第一電路圖案212；形成在絕緣層211的底表面上的第二電路圖案213；電性連接第一電路圖案212和第二電路圖案213的導電通孔216；以及分別保護第一和第二電路圖案212和213的第一和第二介電層(或鈍化層)214和215。如所示的，第一介電層214和第二介電層215可以分別覆蓋第一電路圖案212和第二電路圖案213的橫向側邊。第一介電層214和第二介電層215也可以(舉例而言)分別覆蓋第一電路圖案212和第二電路圖案213的頂側的部分(例如，包括暴露接合焊墊的孔隙)，也就是說，基板210可以形成為具有核心的印刷電路板(PCB)。儘管圖3A中例示了具有單層的基板210，但是也可以形成為多層PCB。注意到，這裡所討論的基板210可以與這裡所討論的基板110(或其部件)共用任何或全部特性。
如圖3A所示，第一電子裝置121和第二電子裝置125被附接到基板210的頂部。第一和第二電子裝置121和125被附接到基板210的 第一電路圖案212。在示例中，第一和第二電子裝置121和125可以通過質量回焊方法、熱壓接合方法、雷射接合方法或任何其它合適的方法電性連接到第一電路圖案212。
作為示例，第一電子裝置121(例如，半導體裝置)可以包括半導體晶粒122和多個傳導凸塊123，並且第二電子裝置125可以是被動裝置或主動裝置。這裡，半導體晶粒122可以包括電路，(舉例而言)例如數位信號處理器(DSP)、微處理器、網路處理器、電源管理處理器、音頻處理器、RF電路、無線基頻系統單晶片上(SoC)處理器、感測器或特殊應用積體電路(ASIC)。半導體晶粒122也可以包括(舉例而言)記憶體，其可以包括揮發性和/或非揮發性記憶體。
如圖3A所示，安裝在基板210上的電子裝置121和125使用囊封物230囊封。囊封物230囊封電子裝置121和125，從而減輕外部影響或環境條件對電子設備121和125的損壞。舉例而言，囊封物230可以是用於一般轉印模製的環氧樹脂模製化合物、用於點膠可在室溫下固化的灌封物及其等效物，但是本揭示的態樣不限於此。這裡所討論的囊封物230和/或其之形成可以與這裡所討論的囊封物130和/或其之形成共用任何或全部特性。
如圖3A所示，傳導凸塊150可以形成在第二電路圖案213上，以電性連接到第二電路圖案213。舉例而言，傳導凸塊150可以用(舉例而言)球柵陣列、平面柵格陣列、接腳格柵陣列…等等的形式來提供。此外，傳導凸塊150可以由例如共晶焊料(Sn37Pb)、高鉛焊料(Sn95Pb)、無鉛焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu、SnAgBi…等等) 及其等效物來形成，但是本揭示的態樣不限於此。舉例而言，傳導凸塊150可以是(但不限於)銅支柱或銅柱、銅芯焊料球…等等。
如圖3B所示，第一載體20可以附接到囊封物230的頂部(或側邊)，並且基板210可被翻轉以允許傳導凸塊150被定位成向上。第一載體20可用各種方式(例如，黏合劑層，雙面膠帶…等等)的任何一種附接到囊封物230(或中間層)。舉例而言，基板210可以被定位成允許傳導凸塊150被定位成向上，而第一載體20附接到囊封物230。
接下來，如圖3C所示，溝槽231被形成在囊封物230中。溝槽231被形成為穿過基板210和囊封物230直到第一載體20。注意到，這裡所討論的溝槽231和/或其之形成可以與這裡所討論的溝槽131和/或其之形成共用任何或全部特性。此外，雖然未示出，但是溝槽231也可被形成為在穿過基板210和囊封物230的同時穿過第一載體20的頂部。因此，基板210可說是已被切割成幾個局部的基板210’。據此，局部的基板210’上的每組電子裝置121和125被實質上分成個別的半導體封裝。然而，由於第一載體20位於囊封物230下面，所以局部的基板210’保持在第一載體20上。
接下來，如圖3D所示，黏合構件50被附接到其上形成有傳導凸塊150的局部的基板210’的底表面。黏合構件50可以形成為環氧樹脂類型黏合膠帶、黏合劑層…等等。因此，傳導凸塊150(其被定位在局部的基板210’的底表面上)現在是由黏合構件50所包圍。接下來，如圖3E所示，第一載體20被移除。這裡，因為即使在移除第一載體20之後，黏合構件50仍附接到局部的基板210’的底部，所以局部的基板210’不會 分離(例如它們的空間配置被維持)。
接下來，如圖3F所示，在形成屏蔽層時，屏蔽層240形成在囊封物230的上表面和側表面、溝槽231的壁(例如，包括側壁、底面…等等)和局部的基板210’的側表面上。溝槽231的壁也可以被視為囊封物230的側表面。局部的基板210’的側表面和/或溝槽231的壁可以是實質上垂直的。然而，側表面和/或壁可具有其它形狀和/或指向，(舉例而言)例如傾斜的、階梯狀的、彎曲狀的…等等。這裡所討論的屏蔽層240和/或其之形成可以與這裡所討論的屏蔽層140和/或其之形成共用任何或全部特性。
這裡，屏蔽層240可電性連接被連接到局部的基板210’的接地的第一和/或第二電路圖案212和213的部分。因此，屏蔽層240可以屏蔽囊封物230，以防止從囊封物230中的電子裝置121和125中的至少一個產生的電磁波被發射到外部。此外，屏蔽層240可以屏蔽囊封物230，以免暴露於外部產生的電磁波。最後，如圖3G所示，黏合構件50被移除，從而完成個別的半導體封裝200。黏合構件50可用任何各種方式(例如，剝離、化學溶解、熱脫膠…等等)移除。
通過上述製造方法形成的半導體封裝200包括：局部的基板210’；電子裝置121和125，其附接到局部的基板210’的頂部；囊封物230，其囊封電子裝置121和125；屏蔽層240，其形成在囊封物230的表面上和局部的基板210’的橫向的側表面上；以及傳導凸塊150，其附接到局部的基板210’的頂部。
已經描述了兩個電子裝置121和125被安裝在用於半導體封 裝100或200的基板上的各種實施例。然而，實施例不必如此限制。舉例而言，可以有用於半導體封裝所安裝的一個半導體裝置(或其他電子裝置)或用於半導體封裝所安裝的多個半導體裝置(或其他電子裝置)。
雖然已經將各種實施例描述為包括多級或多層裝置，但是實施例可以包括單層裝置。舉例而言，實施例可以包括任何數量的單層電介質結構、單層傳導結構…等等。
如上所述，雖然已經針對本揭示的各種實施例描述了半導體封裝及其製造方法，但是本領域技術人員將會理解，可以進行修改和改變，因此所描述的實施例應當在所有方面都被認為只是說明性而不是限制性的。本揭示的範圍應由所附申請專利範圍而不是通過本揭示的描述來限定，並且在不脫離本揭示的範圍的情況下可以進行所有可能的改變和修改。
100‧‧‧半導體封裝
110’‧‧‧基板
111‧‧‧第一基板部分
115‧‧‧第二基板部分
121‧‧‧電子裝置
122‧‧‧半導體晶粒
123‧‧‧傳導凸塊
124‧‧‧底部填充物
125‧‧‧電子裝置
126‧‧‧第三半導體裝置
130‧‧‧囊封物
140‧‧‧屏蔽層
150‧‧‧傳導凸塊

Claims (23)

  1. 一種製造半導體封裝的方法，其包括：形成基板；將第一半導體裝置附接至所述基板的頂部；使用囊封物囊封所述第一半導體裝置；在所述囊封物中形成溝槽，使得所述溝槽包括溝槽側壁和溝槽底部；以及在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形成屏蔽層。
  2. 一種製造半導體封裝的方法，其包括：形成基板，其中前述形成所述基板包括：在支撐層上形成第一基板部分，所述第一基板部分包括第一傳導結構和第一介電結構；將第一載體附接至所述第一基板部分的頂部；移除所述支撐層；以及在所述第一基板部分上形成第二基板部分，所述第二基板部分包括第二傳導結構和第二介電結構；將第一半導體裝置附接至所述基板的頂部；使用囊封物囊封所述第一半導體裝置；在所述囊封物中形成溝槽使得所述溝槽包括溝槽側壁和溝槽底部；以及在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形 成屏蔽層。
  3. 如申請專利範圍第2項所述的方法，其包括：在形成所述屏蔽層之後，將第二載體附接至形成在所述囊封物的頂側上的所述屏蔽層；移除所述第一載體；以及在所述第一基板部分上形成傳導凸塊。
  4. 如申請專利範圍第3項所述的方法，其包括：將第二半導體裝置附接至所述第一基板部分，所述第二半導體裝置的高度小於所述傳導凸塊。
  5. 如申請專利範圍第1項所述的方法，其中所述溝槽被形成以穿過所述囊封物和所述基板。
  6. 如申請專利範圍第1項所述的方法，其中所述屏蔽層被形成在所述基板的側表面上。
  7. 如申請專利範圍第1項所述的方法，其中所述屏蔽層被電性連接至所述基板的接地。
  8. 如申請專利範圍第1項所述的方法，其中所述基板是具有核心的印刷電路板。
  9. 如申請專利範圍第1項所述的方法，其包括：在所述囊封之後，在所述基板上形成傳導凸塊。
  10. 一種製造半導體封裝的方法，其包括：形成基板；將第一半導體裝置附接至所述基板的頂部；使用囊封物囊封所述第一半導體裝置； 在所述囊封之後，在所述基板上形成傳導凸塊；在所述囊封物中形成溝槽使得所述溝槽穿過所述基板及所述囊封物並且包括溝槽側壁和溝槽底部；在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形成屏蔽層；將載體附接至所述囊封物的頂部。
  11. 如申請專利範圍第10項所述的方法，其在形成所述屏蔽層之前包括：將黏合構件附接至所述基板，以包圍所述傳導凸塊；以及移除所述載體。
  12. 一種製造半導體封裝的方法，其包括：在支撐層上形成第一基板部分；將半導體裝置附接至所述第一基板部分的頂側；使用囊封物囊封所述半導體裝置；在所述囊封物中形成溝槽，使得所述溝槽包括溝槽側壁和溝槽底部；在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形成屏蔽層；以及在所述第一基板部分上形成第二基板部分。
  13. 如申請專利範圍第12項所述的方法，其中形成所述第一基板部分包括形成含有傳導結構和介電結構的所述第一基板部分。
  14. 一種製造半導體封裝的方法，其包括：在支撐層上形成第一基板部分； 將半導體裝置附接至所述第一基板部分的頂側；使用囊封物囊封所述半導體裝置；在所述囊封物中形成溝槽，其中形成所述溝槽包括形成所述溝槽使得所述溝槽包括溝槽側壁和溝槽底部，其中所述溝槽側壁穿過所述囊封物、所述第一基板部分以及所述支撐層的部分；在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形成屏蔽層；以及在所述第一基板部分上形成第二基板部分。
  15. 一種製造半導體封裝的方法，其包括：在支撐層上形成第一基板部分；將半導體裝置附接至所述第一基板部分的頂側；使用囊封物囊封所述半導體裝置；在所述囊封物中形成溝槽使得所述溝槽包括溝槽側壁和溝槽底部；在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形成屏蔽層；以及在所述第一基板部分上形成第二基板部分，其中形成所述第二基板部分包括：將載體附接至形成在所述囊封物的頂側上的所述屏蔽層上；移除所述支撐層；以及在所述第一基板部分上形成第二基板部分，其中所述第二基板部分包括傳導結構和介電結構。
  16. 一種製造半導體封裝的方法，其包括： 在支撐層上形成第一基板部分；將半導體裝置附接至所述第一基板部分的頂側；使用囊封物囊封所述半導體裝置；在所述囊封物中形成溝槽使得所述溝槽包括溝槽側壁和溝槽底部；在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上形成屏蔽層；將光阻材料注入到所述溝槽中以及所述屏蔽層上方；在所述第一基板部分上形成第二基板部分。
  17. 如申請專利範圍第12項所述的方法，其包括：在形成所述第二基板部分之後，在所述第二基板部分上形成傳導凸塊。
  18. 一種半導體裝置，其包括：基板，其包括頂部基板部分和底部基板部分；半導體裝置，其被附接至所述頂部基板部分的頂表面；囊封物，其囊封在所述基板上的所述半導體裝置；溝槽，其在所述囊封物中，其中所述溝槽包括溝槽側壁和溝槽底部；以及屏蔽層，其被形成在所述囊封物的表面上、在所述溝槽側壁上以及在所述溝槽底部上。
  19. 如申請專利範圍第18項所述的半導體裝置，其中所述屏蔽層被形成在所述囊封物的頂表面、所述囊封物的側表面以及所述基板的側表面上。
  20. 如申請專利範圍第18項所述的半導體裝置，其中所述屏蔽層被電性連接至所述基板的接地。
  21. 如申請專利範圍第18項所述的半導體裝置，其中所述頂部基板部分包括多層信號分佈結構。
  22. 如申請專利範圍第18項所述的半導體裝置，其進一步包括附接到所述底部基板部分的底部側的另外的半導體裝置。
  23. 如申請專利範圍第18項所述的半導體裝置，其中：所述頂部基板部分的底部側在所述底部基板部分的頂部側上；所述頂部基板部分包括在第一介電層頂部側上的第一介電層和第一傳導層；所述第一傳導層延伸穿過在所述第一介電層中的開口到第一介電層底部側；所述底部基板部分包括在第二介電層底部側上的第二介電層和第二傳導層；並且所述第二傳導層延伸穿過在所述第二介電層中的開口到第二介電層底部側。
TW106115615A 2017-03-02 2017-05-11 半導體封裝及其製造方法 TWI761342B (zh)

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