TWI745359B - 半導體封裝件及半導體封裝件之製造方法 - Google Patents

半導體封裝件及半導體封裝件之製造方法 Download PDF

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TWI745359B
TWI745359B TW106107950A TW106107950A TWI745359B TW I745359 B TWI745359 B TW I745359B TW 106107950 A TW106107950 A TW 106107950A TW 106107950 A TW106107950 A TW 106107950A TW I745359 B TWI745359 B TW I745359B
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semiconductor device
semiconductor package
recess
opening
resin insulating
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TW106107950A
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Chinese (zh)
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TW201803036A (zh
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竹原靖之
北野一彥
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日商安靠科技日本公司
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    • H—ELECTRICITY
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    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
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    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
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    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/6875—Shapes or dispositions thereof being on a metallic substrate, e.g. insulated metal substrates [IMS]
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    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
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    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/134—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being in grooves in the semiconductor body
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    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
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    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
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    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
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    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Led Device Packages (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
TW106107950A 2016-04-28 2017-03-10 半導體封裝件及半導體封裝件之製造方法 TWI745359B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016090189A JP6678506B2 (ja) 2016-04-28 2016-04-28 半導体パッケージ及び半導体パッケージの製造方法
JP2016-090189 2016-04-28

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TW201803036A TW201803036A (zh) 2018-01-16
TWI745359B true TWI745359B (zh) 2021-11-11

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TW110137066A TWI784738B (zh) 2016-04-28 2017-03-10 半導體封裝件及半導體封裝件之製造方法

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US (1) US10553456B2 (cg-RX-API-DMAC7.html)
JP (1) JP6678506B2 (cg-RX-API-DMAC7.html)
KR (1) KR20170123238A (cg-RX-API-DMAC7.html)
CN (2) CN107424980B (cg-RX-API-DMAC7.html)
TW (2) TWI745359B (cg-RX-API-DMAC7.html)

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JP6691835B2 (ja) * 2016-06-17 2020-05-13 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージの製造方法
KR102138012B1 (ko) * 2018-08-28 2020-07-27 삼성전자주식회사 팬-아웃 반도체 패키지
CN111415908B (zh) 2019-01-07 2022-02-22 台达电子企业管理（上海）有限公司 电源模块、芯片嵌入式封装模块及制备方法
WO2021111517A1 (ja) * 2019-12-03 2021-06-10 太陽誘電株式会社 部品モジュールおよびその製造方法
US12266581B2 (en) * 2020-10-30 2025-04-01 Intel Corporation Electronic substrates having heterogeneous dielectric layers
US20220238473A1 (en) * 2021-01-25 2022-07-28 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device

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