TWI717260B - 使用表面封端化學性質的薄膜介電質之選擇性沉積 - Google Patents

使用表面封端化學性質的薄膜介電質之選擇性沉積 Download PDF

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TWI717260B
TWI717260B TW109112760A TW109112760A TWI717260B TW I717260 B TWI717260 B TW I717260B TW 109112760 A TW109112760 A TW 109112760A TW 109112760 A TW109112760 A TW 109112760A TW I717260 B TWI717260 B TW I717260B
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substrate
silylamide
silicon
following
thin film
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TW109112760A
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TW202043524A (zh
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大衛 湯普森
馬克 薩利
巴斯卡爾喬帝 布洋
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美商應用材料股份有限公司
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Abstract

相對於第二基板表面選擇性地沉積薄膜到第一基板表面上的方法。方法包括使用矽基胺浸泡包含羥基終端的基板表面以形成矽基醚終端以及沉積薄膜到該矽基醚終端表面以外的表面上。

Description

使用表面封端化學性質的薄膜介電質之選擇性沉積
本揭示的實施例大體而言係關於選擇性沉積薄膜的方法。更具體言之,本揭示的實施例是針對使用醇選擇性還原和選擇性保護選擇性沉積薄膜的方法。
選擇性沉積製程正獲得極大的動力主要是因為半導體需要圖案化的應用。傳統上,微電子工業中的圖案化已使用各種微影術和蝕刻製程來完成。然而,由於微影術正以指數的方式變得複雜和昂貴,使用選擇性沉積來沉積特徵正變得更具吸引力。選擇性沉積的另一種潛在應用是縫隙填充。在縫隙填充中,填充膜是從溝槽的底部朝向頂部選擇性生長的。選擇性沉積可被用於其他的應用,例如薄膜被生長在鰭片的側邊上的選擇性側壁沉積。這將能夠在不需要複雜的圖案化步驟之下沉積側壁間隔物。
因此,所屬技術領域中需要有選擇性地優先於不同的表面將薄膜選擇性地沉積到一個表面上的方法。
本揭示的一個或更多個實施例是針對沉積薄膜的方法。提供包含第一基板表面和第二基板表面的基板,該第一基板表面包括羥基終端表面,該第二基板表面包括氫終端表面。使該基板暴露於矽基醯胺以與該羥基終端表面反應而形成矽基醚終端表面。使該基板暴露於一種或更多種沉積氣體,以優先於該矽基醚終端表面選擇性地在該第二基板表面上沉積薄膜。
本揭示的其他實施例是針對沉積薄膜的方法。提供包含第一基板表面和第二基板表面的基板,該第一基板表面包括羥基終端表面,該第二基板表面包括氫終端介電質。使用矽基醯胺浸泡該基板以與該羥基終端表面反應而形成矽基醚終端表面。使該基板暴露於一種或更多種沉積氣體,以優先於該第一基板表面選擇性地在該第二基板表面上沉積氮化矽薄膜。
本揭示的進一步實施例是針對沉積薄膜的方法。提供包含第一基板表面和第二基板表面的基板,該第一基板表面包括羥基終端表面,該第二基板表面包括氫終端介電質。使用矽基醯胺浸泡該基板以與該羥基終端表面反應而形成矽基醚終端表面,該矽基醯胺包含1-三甲基矽基吡咯啶、1-三甲基矽基吡咯及/或3,5-二甲基-1-三甲基矽基吡唑中之一者或更多者。使該基板暴露於一種或更多種沉積氣體,以優先於該第一基板表面選擇性地在該第二基板表面上沉積氮化矽薄膜。
有各式各樣的、可被用於選擇性沉積的方法。本揭示的實施例是針對藉由利用兩個不同表面的表面化學性質採用表面去活化的方法。由於兩個不同的表面將具有不同的反應操作,故可以藉由使用將與一個表面反應(以使該表面失活)且不與另一個表面反應的分子來利用差異。本揭示的一些實施例使用三甲基矽基醯胺的化學性質來與一個表面的Si-OH基反應並且不與Si-H終端第二表面反應。
本說明書和所附申請專利範圍中使用的術語「基板」和「晶圓」可互換使用,兩者皆指表面、或表面的一部分,製程在該表面上作用。所屬技術領域中具有通常知識者還將理解的是,提及基板也可以僅指基板的一部分,除非上下文另有清楚指明。此外,提及在基板上沉積可意指裸基板及上面沉積或形成有一個或更多個膜或特徵的基板兩者。
本文中使用的「基板」是指在製造製程期間上面進行薄膜處理的任何基板或形成在基板上的材料表面。例如,上面可以進行處理的基板表面包括的材料例如矽、氧化矽、應變矽、絕緣體上矽(SOI)、摻雜碳的氧化矽、氮化矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石、以及任何其他的材料,例如金屬、金屬氮化物、金屬合金及其他導電材料,取決於應用。基板包括、但不限於半導體晶圓。可以使基板暴露於預處理製程,以拋光、蝕刻、還原、氧化、羥化、退火及/或烘烤基板表面。除了直接在基板本身的表面上的薄膜處理之外,在本揭示中,任何揭示的薄膜處理步驟也都可以在形成於基板上的下層上進行,如以下更詳細揭示的,而且術語「基板表面」意圖包括上下文指出的這種下層。因此,舉例來說,當膜/層或部分膜/層已被沉積到基板表面上時,新沉積的膜/層之暴露表面即變成基板表面。給定的基板表面包含什麼將取決於要沉積什麼薄膜、以及使用的特定化學作用。在一個或更多個實施例中,第一基板表面將包含金屬,並且第二基板表面將包含介電質,或反之亦然。在一些實施例中,基板表面可以包含某些官能性(例如-OH、-NH等)。
同樣地,可以在本文描述的方法中使用的薄膜是相當多樣的。在一些實施例中,薄膜可以包含金屬、或基本上由金屬組成。金屬薄膜的實例包括、但不限於鈷(Co)、銅(Cu)、鎳(Ni)、鎢(W)等。在一些實施例中,薄膜包含介電質。實例包括SiO 2、SiN、HfO 2等。
本說明書和所附申請專利範圍中使用的術語「反應氣體」、「前驅物」、「反應物」、及類似物可被互換使用來指稱包括與基板表面反應的物種的氣體。例如,第一「反應氣體」可以僅吸附於基板的表面上,並可用於與第二反應氣體的進一步化學反應。
本揭示的實施例提供優先於第二表面選擇性沉積金屬膜到一個表面上的方法。本說明書和所附申請專利範圍中使用的用語「優先於另一個表面在一個表面上選擇性沉積薄膜」及類似用語意指第一量的薄膜被沉積在第一表面上並且第二量的薄膜被沉積在第二表面上,其中第二量的薄膜少於第一量的薄膜或無。在這方面使用的用語「優先」並非暗指一個表面在另一個表面之頂部上的物理方向,而是與一個表面的化學反應相對於另一個表面的熱力學或動力學性質之關係。例如,優先於介電質表面選擇性沉積鈷膜到銅表面上意指鈷膜沉積在銅表面上並且較少的或無鈷膜沉積在介電質表面上;或是相對於鈷膜形成在介電質表面上,鈷膜形成在銅表面上是熱力學或動力學上優先的。
參照第1圖,本揭示的一個或更多個實施例是針對沉積薄膜的方法。提供包含第一基板表面12和第二基板表面14的基板10。第一基板表面12包括羥基終端表面(即具有-OH基的表面)。第二基板表面14包括氫終端表面(即具有-H端基例如Si-H或Si-NH 2的表面)。氫終端表面可以包括胺終端表面(如在SiN膜中可找到的)。在一些實施例中,第一基板表面12大體上僅包含羥基端基。在這方面使用的用語「大體上僅」意指該第一基板表面的表面端基中至少約75%、80%、85%、90%或95%為羥基端基。在一些實施例中,第二基板表面14大體上僅包含氫端基。在這方面使用的用語「大體上僅」意指該第二基板表面的表面端基中至少約75%、80%、85%、90%或95%為氫端基。在一些實施例中,第一基板表面12與第二基板表面14中之一者或更多者包含介電質。在一個或更多個實施例中,第一基板表面12包含介電質。介電質可以是低介電常數介電質或高介電常數介電質。
使基板10暴露於矽基醯胺以與第一基板表面12及/或第二基板表面14中之一者或更多者反應。使基板表面暴露於矽基醯胺可以藉由任何適當的製程來完成。暴露可被稱為浸泡,其中至少一些基板表面被矽基醯胺「浸泡」或「淹沒」以允許表面反應發生。本說明書和所附申請專利範圍中使用的術語「矽基醯胺」是指具有矽-氮鍵的化合物,其中氮是胺基的一部分或雜環的一部分。第1圖圖示在Si-OH終端表面(第一基板表面12)上對比在Si-H終端表面(第二基板表面14)上發生的初始表面反應之示意圖。
矽-碳鍵是非常強的,而且不是很有活性。不受任何特定的操作理論約束,據信矽基醯胺可以藉由矽-碳鍵使任何表面失活。矽-碳鍵也是熱穩定的、表現出高達600 ℃的穩定性。矽基醯胺基團對鹼性Si-H基無活性,而且將不會使Si-H終端表面失去活性。業已發現,使用矽基醯胺可以允許在Si-H上而不在Si-OH終端表面上選擇性沉積某些介電質製程。
第1圖中的矽基醯胺是由(CH 3) 3Si-L表示,其中L是任意的胺或雜環胺。第1圖圖示的矽基醯胺僅表示一種可能的矽基醯胺,而且不應被視為限制本揭示的範圍。矽基醯胺與第一基板表面12上的羥基端基反應而形成矽基醚終端表面13並逐步形成HL。本說明書和所附申請專利範圍中使用的術語「矽基醚」是指具有形成表面端基的Si-O鍵的化合物。
適當的矽基醯胺是可與表面羥基反應以形成矽基醚終端表面的那些矽基醯胺。在一些實施例中,矽基醯胺包含有機矽基醯胺。本說明書和所附申請專利範圍中使用的術語「有機矽基醯胺」是指其中矽原子鍵結到一個或更多個有機基團的化合物。例如,如第1圖所示,有機矽基醯胺是三甲基矽基醯胺。
在一個或更多個實施例中,有機矽基醯胺包含大體上僅鍵結到碳及/或氮原子的矽原子。本說明書和所附申請專利範圍中使用的術語「大體上僅到碳及/或氮」意指在原子的基礎上有少於約5%的矽原子鍵結到碳或氮以外的原子。在一個或更多個實施例中,有機矽基醯胺大體上不含Si-H或Si-OH鍵。本說明書和所附申請專利範圍中使用的術語「大體上無Si-H及/或Si-OH鍵」意指有少於約5%的矽原子鍵結到氫或氫氧化物。
在一些實施例中,有機矽基醯胺包含三甲基矽基醯胺、三乙基矽基醯胺、乙基二甲基矽基醯胺、及/或二乙基甲基矽基醯胺中之一者或更多者。在一個或更多個實施例中,矽基醯胺包括醯胺,該醯胺包含吡咯啶、吡咯、吡唑、二甲胺、二乙胺、乙基甲基胺、環狀二級胺、飽和環胺及/或不飽和環胺中之一者或更多者。
三甲基矽基醯胺含有鹼性胺基,該鹼性胺基將容易與Si-OH基反應以形成游離胺並導致非常穩定的(CH3)3Si-O-Si部分形成。在某些實施例中,矽基醯胺包含1-三甲基矽基吡咯啶、1-三甲基矽基吡咯及/或3,5-二甲基-1-三甲基矽基吡唑中之一者或更多者。
使基板表面暴露於預處理(即矽基醯胺)的溫度取決於例如第一表面、第二表面、矽基醯胺、計劃的未來處理、過去的處理、及正使用的處理設備。例如,較低溫的製程可以有助於保留基板的熱預算用於進一步的處理。在一些實施例中,使基板表面在約50 ℃至約600 ℃的範圍中的溫度下暴露於矽基醯胺。
矽基醯胺的暴露時間可以視例如矽基醯胺對目標表面材料的反應性而改變。在一些實施例中,使基板暴露於矽基醯胺持續在約10秒至約60分鐘的範圍中的時間。在一些實施例中,矽基醯胺的暴露發生少於約10分鐘、5分鐘、1分鐘或0.5分鐘的時間。
在形成矽基醚終端表面13之後,可以將薄膜沉積到第二基板表面14上而不影響矽基醚終端表面13。薄膜可以藉由任何適當的技術沉積。在一些實施例中,使基板10暴露於一種或更多種沉積氣體以對比矽基醚終端表面13選擇性地在第二基板表面14上沉積薄膜15。在一個或更多個實施例中,沉積的薄膜15包含SiN。一些實施例的薄膜15是藉由原子層沉積所沉積的,該原子層沉積包含相繼暴露於含矽氣體和含氮氣體。適當的含矽氣體包括、但不限於矽烷、乙矽烷、丙矽烷、一氯矽烷、二氯矽烷、三氯矽烷、四氯化矽、六氯乙矽烷(HCDS)、鹵化碳矽烷及上述之組合。適當的含氮氣體包括、但不限於含氮電漿、氨、胺、肼及/或碳氮化物。
薄膜形成製程可以是CVD製程,其中同時使第一反應氣體和第二反應氣體接觸基板表面,使得第一反應氣體與第二反應氣體在薄膜的形成過程中混合。
在一些實施例中,薄膜形成製程是ALD製程,其中使基板或部分的基板相繼暴露於第一反應氣體和第二反應氣體。相繼暴露意指在任何給定的時間只使基板或部分的基板暴露於第一反應氣體和第二反應氣體中之一者。在ALD製程中,大體上沒有第一反應氣體和第二反應氣體的氣相混合。
第2圖圖示稱為處理室110的空間原子層沉積批次處理器之實施例。處理室110的形狀和描述的元件只是例示性的,不應被視為限制本揭示之範圍。例如,八角形的處理室可以是圓形或六邊形的等等。負載鎖定112腔室被連接到處理室110的前部(可以被任意指定為前部),並提供隔離處理室的內部體積與處理室110外部的大氣的方式。負載鎖定112可以是任何適當的負載鎖定,而且能以所屬技術領域中具有通常知識者習知的任何適當負載鎖定的方式操作。
基板160通入處理室110進入裝載區120。在裝載區120中,基板160可經受處理條件或可以靜置。裝載區中的處理條件可以是例如預熱基板160到處理溫度、暴露於預處理(例如矽基胺暴露)或清洗。在一些實施例中,使基板160暴露於包含氣態矽基胺的預處理。
將基板160從裝載區橫向移動通過氣幕140到達第一處理區域121。使用序數來描述處理區域只是例示性的,不應被視為限制本揭示之範圍。使用用語「第一處理區域」、「第二處理區域」等只是意圖作為方便的、描述處理室之不同部分的方式。腔室內的處理區域之具體位置並不限於圖示的實施例。橫向移動基板160可以藉由圍繞箭頭117指示的軸、或在與箭頭117相反的方向上旋轉基座166來發生。在第一處理區域121中,可以使基板160暴露於第一反應氣體或前驅物用於進行ALD製程。
在處理室110內從第一處理區域121橫向移動基板160通過氣幕140到達第二處理區域122。氣幕140在處理室110內提供各個處理區域之間的分隔。氣幕被圖示為帶有截斷內端的楔形元件,但將理解的是,氣幕可以是適用於將處理區域保持隔離的任何形狀。氣幕140可以包括能夠分隔個別處理區域之氛圍的惰性氣體及/或真空口之任何適當組合。在一些實施例中,氣幕140依序包含真空口、惰性氣體口及另一個真空口。在從第一處理區域121移動基板到第二處理區域122的過程中的一些時間點,基板的一個部分被暴露於第二處理區域,同時基板的另一個部分被暴露於第一處理區域121,並且中央部在氣幕140內。
一旦在第二處理區域122中,則可以使基板160暴露於可以完成ALD製程的第二反應氣體。例如,假使正在形成SiN膜,則第一反應氣體可以是含矽前驅物,並且第二反應氣體可以是含氮氣體。
可以使基板160沿著箭頭117指示的圓形路徑連續橫向移動,以使基板暴露於第三處理區域123、第四處理區域124、第五處理區域125、第六處理區域126及第七處理區域127並返回到裝載區。在一些實施例中,裝載區120、第二處理區域122、第四處理區域124及第六處理區域126每個皆使基板暴露於包含醇的第二反應氣體,而且第一處理區域121、第三處理區域123、第五處理區域125及第七處理區域127每個皆使基板160暴露於第一反應氣體。第2圖圖示的實施例具有位於第一、第三、第五及第七處理區域的楔形氣體分配組件130,為了清楚起見將基座166上的基板160圖示在氣體分配組件130之間。然而,將理解的是,任何或所有的處理區域都可以具有氣體分配組件130或其他的氣體分配系統。
一旦沉積了薄膜15,則可以進行進一步的處理。例如,可以進行第一基板表面12的去保護以移除矽基醚端基。這可以在沉積薄膜15之後藉由任何可以從表面移除矽基醚端基的適當方法或技術來完成。進一步的處理可以在相同的處理室或不同的處理室中進行。
在一些實施例中,矽基胺暴露之後進行ALD沉積循環。在一些時間間隔時,蝕刻矽基醚並形成新的矽基醚層。在一些實施例中,在不超過約300個ALD循環、或200個ALD循環、或100個ALD循環、或75個ALD循環或50個ALD循環之後蝕刻矽基醚。在一個或更多個實施例中,在每100個ALD沉積循環之後進行蝕刻製程,之後在連續沉積之前再次使用矽基胺進行處理。
在一些實施例中,製程在批次處理腔中進行。例如,在旋轉平臺腔室中,其中一個或更多個晶圓被放在旋轉支架(「平臺」)上。當平臺旋轉時,晶圓在各個處理區域之間移動。例如,在ALD中,處理區域會使晶圓暴露於前驅物和反應物。此外,電漿暴露可用於適當地處理薄膜或表面以增強薄膜的生長、或獲得理想的薄膜性質。
本揭示的一些實施例在單一處理室中處理具有第一表面和第二表面的基板,其中在腔室的第一部分中使基板表面暴露於矽基胺。然後可以將基板旋轉到處理室的第二部分、及/或處理室的後續部分以沉積薄膜。在一些實施例中,可以將基板進一步旋轉或移動到處理室可以移除矽基醚端基的另一個部分。為了分隔處理室的每個或任何部分、或區域,可以採用氣幕。氣幕在處理區域之間提供淨化氣體和真空口中之一者或更多者,以防止反應氣體從一個區域移動到相鄰的區域。在一些實施例中,使基板同時暴露於超過一個處理區域,且基板的一個部分在第一區域(例如用於矽基胺暴露)中並且同時基板的另一個部分在處理室的不同區域中。
本揭示的實施例可與線性處理系統或旋轉處理系統一起使用。在線性處理系統中,電漿離開殼體的區域之寬度在橫跨正面的整個長度上大致是相同的。在旋轉處理系統中,殼體可以大體為「派形的」或「楔形的」。在楔形的區段中,電漿離開殼體的區域之寬度改變以符合派形。本說明書和所附申請專利範圍中使用的用語「派形的」和「楔形的」可互換使用來描述大體為圓扇形的主體。例如,楔形區段可以是圓形或盤形物體的一小部分,並且可以具有截斷點。派形區段的內緣可以來到一個點或可以被截斷成平邊或圓形。基板的路徑可以垂直於進氣口。在一些實施例中,每個氣體噴射組件皆包含多個在大體上垂直於基板移動路徑的方向上延伸的細長進氣口。本說明書和所附申請專利範圍中使用的用語「大體上垂直」意指基板的移動方向大致上是沿著大致垂直(例如約45º至90º)於進氣口的軸的平面。對於楔形進氣口來說,可以將進氣口的軸視為進氣口寬度的中點沿著進氣口的長度延伸所界定的線。
本揭示的其他實施例是針對處理複數個基板的方法。該複數個基板被裝載到處理室中的基板支座上。基板支座被旋轉以使該複數個基板中的每個基板通過橫跨氣體分配組件,而使基板表面暴露於矽基胺、在基板上沉積薄膜、及可選地移除矽基醚層。
旋轉料架的旋轉可以是不間斷或間斷的。在不間斷的處理中,晶圓被不斷地轉動,使得晶圓依次被暴露於每個噴射器。在間斷的處理中,晶圓可被移到噴射器區域並停止,然後到達噴射器之間的區域並停止。例如,旋轉料架可以旋轉,使得晶圓從注射器間區移動穿過噴射器(或鄰接噴射器停止)並到達下一個噴射器間區上,於此旋轉料架可以再次暫停。噴射器之間的暫停可以為每個層沉積之間的附加處理(例如暴露於電漿)提供時間。可以調整電漿的頻率,取決於使用的具體反應物種。適當的頻率包括、但不限於400 kHz、2 MHz、13.56 MHz、27 MHz、40 MHz、60 MHz及100 MHz。
依據一個或更多個實施例,基板在形成層之前及/或之後經受處理。這個處理可以在同一腔室中或在一個或更多個不同的處理室中進行。在一些實施例中,基板被從第一腔室移到用於進一步處理的、不同的第二腔室。基板可以被直接從第一腔室移到不同的處理室,或是基板可以被從第一腔室移到一個或更多個移送室,然後被移到不同的處理室。因此,處理設備可以包含與移送站通訊的多個腔室。這種類型的設備可被稱為「群集工具」或「群集系統」、及類似物。
一般來說,群集工具是包含多個腔室的模組化系統,該多個腔室執行各種功能,包括基板中心查找和定向、除氣、退火、沉積及/或蝕刻。依據一個或更多個實施例,群集工具包括至少一第一腔室和中央移送室。中央移送室可以容納機器人,該機器人可以在處理室與負載鎖定腔室之間來回移動基板。移送室通常被保持在真空狀態,並提供中間階段用於從一個腔室來回移動基板到另一個腔室及/或到被定位在群集工具前端的負載鎖定腔室。兩種可適用於本揭示的眾所週知群集工具是Centura®和Endura®,皆購自美國加州聖克拉拉的應用材料公司(Applied Materials, Inc., of Santa Clara, Calif.)。一台這種階段式真空基板處理設備的細節被揭示於Tepman等人於1993年2月16日領證、標題為「階段式真空晶圓處理設備和方法(Staged-Vacuum Wafer Processing Apparatus and Method)」的美國專利第5,186,718號中。然而,為了進行本文所述製程之具體步驟的目的,可以改變腔室的確切安排和組合。其他可以使用的處理室包括、但不限於循環性層沉積(CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、蝕刻、預清洗、化學清洗、諸如RTP的熱處理、電漿氮化、除氣、定向、羥基化及其他基板製程。藉由在群集工具上的腔室中進行製程,可以在沉積後續薄膜之前、沒有氧化之下避免基板具有大氣雜質的表面污染物。
依據一個或更多個實施例,基板連續處在真空或「負載鎖定」狀態下,而且在被從一個腔室移到下一個腔室時不暴露於環境空氣。移送室因此處在真空之下,並在真空壓力下被「抽空」。惰性氣體可以存在於處理室或移送室中。在一些實施例中,惰性氣體被用於作為淨化氣體,以在基板的表面上形成層之後移除一些或全部的反應物。依據一個或更多個實施例,在沉積室的出口注射淨化氣體,以防止反應物從沉積室移到移送室及/或其他的處理室。因此,惰性氣體的流動在腔室的出口處形成簾幕。
在處理過程中,基板可以被加熱或冷卻。這種加熱或冷卻可以藉由任何適當的手段來完成,該手段包括、但不限於改變基板支座(例如基座)的溫度及使加熱或冷卻氣體流到基板表面。在一些實施例中,基板支座包括加熱器/冷卻器,該加熱器/冷卻器可被控制來導電式地改變基板溫度。在一個或更多個實施例中,將所採用的氣體(反應氣體或惰性氣體)加熱或冷卻,以局部改變基板溫度。在一些實施例中,加熱器/冷卻器被定位在鄰近基板表面的腔室內,以對流式地改變基板溫度。
在處理過程中基板也可以是靜止的或轉動的。轉動的基板可以被連續轉動或在不連續的步驟中被轉動。例如,基板可以在整個製程從頭至尾被轉動,或者基板可以在暴露於不同的反應或淨化氣體之間少量轉動。在處理過程中轉動基板(連續地或依步驟)可以有助於藉由最小化例如氣流幾何形狀中局部變異性的影響來產生更均勻的沉積或蝕刻。
三甲基矽基醯胺的製備
一種製備三甲基矽基醯胺化合物的方式是藉由使用三甲基矽基氯化物處理鋰胺的鹽置換。將反應方案圖示於方程式1,
Figure 02_image001
(1) 其中L可以等於任何胺或雜環胺。胺的一些具體實例是二甲胺、二乙胺、吡咯啶、吡唑及吡咯。
1-三甲基矽基吡咯啶之合成
方程式2顯示被稱為BL1的1-三甲基矽基吡咯啶之合成方案。將6.5 mL(80 mmol)的吡咯啶溶於250 mL的己烷中,並將溶液冷卻至-78 ℃。在15分鐘的期間將50 mL(80 mmol)在己烷中的1.6 M正丁基鋰逐滴加入此溶液中。讓所得的反應混合物緩慢到達室溫並攪拌30分鐘。然後將反應混合物再次冷卻到-78 ℃,並在10分鐘的期間加入20 mL、含有10.1 mL(80 mmol)三甲基矽基氯化物的己烷溶液。讓反應混合物緩慢到達室溫並攪拌12小時。在惰性氛圍下過濾出白色沉澱物,並在真空下將己烷蒸發。在110 ℃、760托下將產物蒸餾為無色液體。產率:8.9 g(77.5%)。 1HNMR (400.18 MHz, C 6D 6) 2.87 (m, 4H), 1.57 (m, 4H), 0.11 (s, 9H) ppm; 13CNMR (100.64 MHz, C 6D 6) 1.08 ppm。
Figure 02_image003
(2)
1-三甲基矽基吡咯之合成
方程式3顯示也被稱為BL2的1-三甲基矽基吡咯之合成方案。將5.55 mL(80 mmol)的吡咯溶於250 mL的己烷中,並將溶液冷卻至-78 ℃。在15分鐘的期間將50 mL(80 mmol)在己烷中的1.6 M正丁基鋰逐滴加入此溶液中。讓所得的反應混合物緩慢到達室溫並攪拌30分鐘。然後將反應混合物再次冷卻到-78 ℃,並在10分鐘的期間加入10.1 mL(80 mmol)三甲基矽基氯化物的20 mL己烷溶液。讓反應混合物緩慢到達室溫並攪拌12小時。在惰性氛圍下過濾出白色沉澱物,並在真空下將己烷蒸發。在130 ℃、760托下將產物蒸餾為無色液體。產率:8.7 g(78.2%)。 1HNMR (400.18 MHz, C 6D 6) 6.74 (s, 2H), 6.54 (s, 2H), 0.07 (s, 9H) ppm; 13CNMR (100.64 MHz, C 6D 6) 123.47, 112.20, -0.01 ppm。質譜儀:計算[M+H] += 140.1之m/Z,發現為140.2。
Figure 02_image005
(3)
3,5-二甲基-1-三甲基矽基吡唑之合成
方程式4顯示也被稱為BL3的3,5-二甲基-1-三甲基矽基吡唑之合成方案。將7.7 g(80 mmol)的3,5-二甲基吡唑溶於250 mL的己烷中,並將溶液冷卻至-78 ℃。在15分鐘的期間將50 mL(80 mmol)在己烷中的1.6 M正丁基鋰逐滴加入此溶液中。讓所得的反應混合物緩慢到達室溫並攪拌30分鐘。然後將反應混合物再次冷卻到-78 ℃,並在10分鐘的期間加入10.1 mL(80 mmol)三甲基矽基氯化物的20 mL己烷溶液。讓反應混合物緩慢到達室溫並攪拌12小時。在惰性氛圍下過濾出白色沉澱物,並在真空下將己烷蒸發。在70 ℃、20托下將產物蒸餾為無色液體。產率:9.4 g(70.0%)。 1HNMR (400.18 MHz, C 6D 6) 5.80 (S, 1H), 2.30 (S, 3H), 2.00 (s, 3H), 0.32 (s, 9H) ppm; 13CNMR (100.64 MHz, C 6D 6) 151.97, 146.04, 108.40, 32.54, 23.63, 1.02 ppm。
Figure 02_image007
(4)
依據 1HNMR和 13CNMR,合成製備、特徵化、及性質展現良好的純度和高產率。依據TGA分析,這些分子是揮發性(最高蒸發率在90-137 ℃之間)和熱穩定的,有〜0%的殘餘物。 實例
藉由在350 ℃下在蒸汽相中使用BL1處理基板(Si(H)、SiO 21K、Si(天然氧化物))來測試三甲基矽基醯胺作為封端層。然後在相同溫度下進行SiN的ALD。使用的矽前驅物是四溴化矽,並且含氮前驅物包含氨(30T)。總共有100個循環。表1顯示在2.4托下使用BL1浸泡不同時間長度的結果。表2顯示在5托下浸泡30秒的結果。 表1
浸泡時間 (min) 薄膜厚度(Å)
Si(H) Si(天然O) SiO 21K
30 30.4 4.58 2.65
10 28.4 2.02 2.18
5 31.7 4.98 2.12
1 32.5 5.2 2.59
0.5 31.33 7.19 2.62
0 28.5 28.23 20.39
表2
浸泡時間 (min) 薄膜厚度(Å)
Si(H) Si(天然O) SiO 21K
0.5 25.3 1.1 0.84
當不使用BL1進行前處理時,觀察到有很低的、相對於Si(H)、SiO 21K及Si(天然O)的選擇性。在2T下超過1分鐘的BL1浸泡時間能夠有非常好的選擇性。依據接觸角量測,有極少或根本沒有SiN沉積在SiO 2和矽(天然O)基板上。這可藉由在Si(H)上對比在SiO 2和矽(天然O)上的親水性來驗證。在30秒的BL1浸泡時間下,基於橢圓偏光儀仍有一些選擇性,然而接觸角非常相似,這可能表示全部三個表面上都有SiN。壓力增加到5T持續30秒可回復選擇性。
還評估BL1的選擇率為循環數的函數。將結果收集在表3中。在100個循環之後,觀察到~8.6(Si(H) vs SiO 2)的選擇率。100個循環之後選擇率表現出降低。不受任何特定操作理論的約束,據信BL1封端層可促進持續約100個循環的成核延遲。 表3
ALD 循環數 薄膜厚度(Å)
Si(H) Si(天然O) SiO 21K
50 13 1 1
100 29 5 3
150 47 25 17
200 111 86 82
雖然前述係針對本揭示之實施例,但可以在不偏離本揭示之基本範圍下設計出本揭示之其他的和進一步的實施例,而且本揭示之範圍係由隨後的申請專利範圍決定。
10 基板 12 第一基板表面 13 矽基醚終端表面 14 第二基板表面 15 薄膜 110 處理室 112 負載鎖定 117 箭頭 120 裝載區 121 第一處理區域 122 第二處理區域 123 第三處理區域 124 第四處理區域 125 第五處理區域 126 第六處理區域 127 第七處理區域 130 氣體分配組件 140 氣幕 160 基板 166 基座
為詳細瞭解上述本揭示之特徵,可參照實施例(其中一些圖示於附圖中)而對以上簡要概述的本揭示作更特定的描述。然而,應注意的是,附圖僅圖示本揭示之典型實施例,因此不應將該等附圖視為限制本揭示之範圍,因本揭示可認可其他等同有效的實施例。
第1圖圖示依據本揭示之一個或更多個實施例的處理方法之示意圖;以及
第2圖圖示依據本揭示之一個或更多個實施例的批次處理腔室之實施例。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
10 基板 12 第一基板表面 13 矽基醚終端表面 14 第二基板表面 15 薄膜

Claims (20)

  1. 一種沉積一薄膜的方法,該方法包含以下步驟: 使一基板暴露於一矽基醯胺,以與一羥基終端第一基板表面反應而形成一矽基醚終端表面,該基板具有一氫終端第二基板表面,該第一表面及該第二表面中之一或多者包含一介電質;以及藉由使該基板暴露於一或更多種沉積氣體,以優先於該第一表面選擇性地將一薄膜形成在該第二表面上。
  2. 如請求項1所述之方法,其中該矽基醯胺包含一有機矽基醯胺。
  3. 如請求項2所述之方法,其中該有機矽基醯胺包含一矽原子,該矽原子大體上僅鍵結到碳原子及/或氮原子。
  4. 如請求項2所述之方法,其中該有機矽基醯胺大體上不含Si-H或Si-OH鍵。
  5. 如請求項2所述之方法,其中該有機矽基醯胺包含以下一或多者:三甲基矽基醯胺、三乙基矽基醯胺、乙基二甲基矽基醯胺及/或二乙基甲基矽基醯胺。
  6. 如請求項1所述之方法,其中該矽基醯胺包括一醯胺,該醯胺包含以下一或多者:吡咯啶、吡咯、吡唑、二甲胺、二乙胺、乙基甲基胺、環狀二級胺、飽和環胺及/或不飽和環胺。
  7. 如請求項1所述之方法,其中該矽基醯胺包含以下一或多者:1-三甲基矽基吡咯啶、1-三甲基矽基吡咯及/或3,5-二甲基-1-三甲基矽基吡唑。
  8. 如請求項1所述之方法,其中該第一基板表面包含一介電質。
  9. 如請求項1所述之方法,進一步包含以下步驟:在該第二表面上形成預定量的薄膜之後蝕刻該矽基醚終端表面,接著再次暴露於該矽基醯胺,以再次形成該矽基醚終端表面和額外的薄膜形成。
  10. 如請求項9所述之方法,其中在不超過300個原子層沉積循環之後蝕刻並再次形成該矽基醚終端表面。
  11. 如請求項1所述之方法,其中使該基板暴露於該矽基醯胺達約10秒至約60分鐘的範圍中之一時間。
  12. 如請求項1所述之方法,其中該薄膜包含SiN。
  13. 如請求項12所述之方法,其中藉由原子層沉積來沉積該薄膜,該原子層沉積包含相繼暴露於一含矽氣體和一含氮氣體。
  14. 如請求項13所述之方法,其中該含矽氣體包含以下一或多者:矽烷、乙矽烷、丙矽烷、一氯矽烷、二氯矽烷、三氯矽烷、四氯化矽、六氯乙矽烷(HCDS)及鹵化碳矽烷。
  15. 如請求項13所述之方法,其中該含氮氣體包含以下一或多者:一含氮電漿、氨、胺、肼及/或碳氮化物。
  16. 一種沉積一薄膜的方法,該方法包含以下步驟: 提供一基板,該基板包含一第一基板表面及一第二基板表面,該第一基板表面具有一羥基終端表面,該第二基板表面具有一氫終端表面,該第一基板表面及該第二基板表面中之一或多者包含一介電質; 使該第一基板表面的該羥基終端表面與一矽基醯胺浸泡反應,以形成一矽基醚終端表面;以及 藉由一原子層沉積製程以優先於該第一基板表面選擇性地將一氮化矽薄膜沉積在該第二基板表面上,該基板在該原子層沉積製程中相繼暴露於一含矽氣體和一含氮氣體。
  17. 如請求項16所述之方法,其中該矽基醯胺包含矽原子,該等矽原子大體上僅鍵結到碳原子及/或氮原子,並且大體上沒有Si-H或Si-OH鍵,且該矽基醯胺包括一醯胺,該醯胺包含以下一或多者:吡咯啶、吡咯、吡唑、二甲胺、二乙胺、乙基甲基胺、環狀二級胺、飽和環胺及/或不飽和環胺。
  18. 如請求項17所述之方法,其中該矽基醯胺包含以下一或多者:1-三甲基矽基吡咯啶、1-三甲基矽基吡咯及/或3,5-二甲基-1-三甲基矽基吡唑。
  19. 如請求項18所述之方法,其中該含矽氣體包含以下一或多者:矽烷、乙矽烷、丙矽烷、一氯矽烷、二氯矽烷、三氯矽烷、四氯化矽、六氯乙矽烷(HCDS)或鹵化碳矽烷,且該含氮氣體包含以下一或多者:一含氮電漿、氨、胺、肼或碳氮化物。
  20. 一種沉積一薄膜的方法,該方法包含以下步驟: 提供一基板,該基板包含一第一基板表面及一第二基板表面,該第一基板表面包括一羥基終端表面,該第二基板表面包括一氫終端表面,該第一基板表面及該第二基板表面中之一或多者包含一介電質; 將包含一羥基終端第一基板表面及一氫終端第二基板表面之一基板浸泡於一矽基醯胺,以與該羥基終端第一基板表面反應而形成一矽基醚終端機板表面,該矽基醯胺包含以下一或多者:1-三甲基矽基吡咯啶、1-三甲基矽基吡咯或3,5-二甲基-1-三甲基矽基吡唑;以及 藉由相繼使該基板在一第一處理區域中暴露於一含矽氣體、橫向移動該基板通過一氣幕到達一第二處理區域及使該基板在該第二處理區域中暴露於一含氮氣體,以優先於該第一基板表面選擇性地將一氮化矽薄膜形成在該第二基板表面上。
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Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI686499B (zh) 2014-02-04 2020-03-01 荷蘭商Asm Ip控股公司 金屬、金屬氧化物與介電質的選擇性沉積
US10047435B2 (en) 2014-04-16 2018-08-14 Asm Ip Holding B.V. Dual selective deposition
US9490145B2 (en) 2015-02-23 2016-11-08 Asm Ip Holding B.V. Removal of surface passivation
TWI706957B (zh) * 2015-03-30 2020-10-11 法商液態空氣喬治斯克勞帝方法研究開發股份有限公司 碳矽烷與氨、胺類及脒類之觸媒去氫耦合
US10428421B2 (en) 2015-08-03 2019-10-01 Asm Ip Holding B.V. Selective deposition on metal or metallic surfaces relative to dielectric surfaces
WO2017048911A1 (en) * 2015-09-19 2017-03-23 Applied Materials, Inc. Surface-selective atomic layer deposition using hydrosilylation passivation
US10695794B2 (en) 2015-10-09 2020-06-30 Asm Ip Holding B.V. Vapor phase deposition of organic films
US10814349B2 (en) 2015-10-09 2020-10-27 Asm Ip Holding B.V. Vapor phase deposition of organic films
US11081342B2 (en) 2016-05-05 2021-08-03 Asm Ip Holding B.V. Selective deposition using hydrophobic precursors
US10453701B2 (en) 2016-06-01 2019-10-22 Asm Ip Holding B.V. Deposition of organic films
US10373820B2 (en) 2016-06-01 2019-08-06 Asm Ip Holding B.V. Deposition of organic films
US11430656B2 (en) 2016-11-29 2022-08-30 Asm Ip Holding B.V. Deposition of oxide thin films
TWI700750B (zh) * 2017-01-24 2020-08-01 美商應用材料股份有限公司 用於介電薄膜的選擇性沉積之方法及設備
TWI739984B (zh) * 2017-01-31 2021-09-21 美商應用材料股份有限公司 就圖案化應用進行選擇性沉積之方案
US10790140B2 (en) 2017-02-14 2020-09-29 Applied Materials, Inc. High deposition rate and high quality nitride
US11094535B2 (en) * 2017-02-14 2021-08-17 Asm Ip Holding B.V. Selective passivation and selective deposition
US10176984B2 (en) 2017-02-14 2019-01-08 Lam Research Corporation Selective deposition of silicon oxide
US10242866B2 (en) * 2017-03-08 2019-03-26 Lam Research Corporation Selective deposition of silicon nitride on silicon oxide using catalytic control
US10043656B1 (en) * 2017-03-10 2018-08-07 Lam Research Corporation Selective growth of silicon oxide or silicon nitride on silicon surfaces in the presence of silicon oxide
US9911595B1 (en) * 2017-03-17 2018-03-06 Lam Research Corporation Selective growth of silicon nitride
JP7085561B2 (ja) * 2017-03-17 2022-06-16 バーサム マテリアルズ ユーエス,リミティド ライアビリティ カンパニー ケイ素含有表面への選択的堆積
US10559461B2 (en) * 2017-04-19 2020-02-11 Lam Research Corporation Selective deposition with atomic layer etch reset
US10355111B2 (en) 2017-04-26 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Deposition selectivity enhancement and manufacturing method thereof
US11501965B2 (en) 2017-05-05 2022-11-15 Asm Ip Holding B.V. Plasma enhanced deposition processes for controlled formation of metal oxide thin films
CN115233183A (zh) * 2017-05-16 2022-10-25 Asm Ip 控股有限公司 电介质上氧化物的选择性peald
TWI782021B (zh) * 2017-05-28 2022-11-01 美商應用材料股份有限公司 有機及混合有機無機層的選擇性分子層沉積
KR102331718B1 (ko) 2017-06-08 2021-11-26 삼성전자주식회사 반도체 장치 제조 방법
TWI722301B (zh) 2017-07-18 2021-03-21 美商應用材料股份有限公司 在金屬材料表面上沉積阻擋層的方法
US10515896B2 (en) * 2017-08-31 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor device and methods of fabrication thereof
WO2019055508A1 (en) * 2017-09-12 2019-03-21 Applied Materials, Inc. SELECTIVE REMOVAL OF CHEMICAL ENGRAVING DEPOSITION DEFECTS
JP6955090B2 (ja) * 2017-09-19 2021-10-27 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 酸化ケイ素上における誘電体の選択的堆積のための方法
US10403504B2 (en) * 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
WO2019071215A1 (en) * 2017-10-06 2019-04-11 Applied Materials, Inc. METHODS AND PRECURSORS FOR SELECTIVE DEPOSITION OF METALLIC FILMS
JP6956592B2 (ja) * 2017-10-31 2021-11-02 東京エレクトロン株式会社 シリコン酸化膜を形成する方法および装置
US10460930B2 (en) * 2017-11-22 2019-10-29 Lam Research Corporation Selective growth of SiO2 on dielectric surfaces in the presence of copper
US10607841B2 (en) * 2017-12-17 2020-03-31 Applied Materials, Inc. Silicide films through selective deposition
US11404275B2 (en) 2018-03-02 2022-08-02 Lam Research Corporation Selective deposition using hydrolysis
KR20230137501A (ko) * 2018-05-28 2023-10-04 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치 및 프로그램
US11069526B2 (en) 2018-06-27 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Using a self-assembly layer to facilitate selective formation of an etching stop layer
WO2020016915A1 (ja) * 2018-07-17 2020-01-23 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置およびプログラム
KR102640002B1 (ko) * 2018-07-17 2024-02-27 가부시키가이샤 코쿠사이 엘렉트릭 반도체 장치의 제조 방법, 기판 처리 장치, 기록매체, 및 프로그램
WO2020046746A1 (en) * 2018-08-27 2020-03-05 Versum Materials Us, Llc Selective deposition on silicon containing surfaces
US10665715B2 (en) 2018-08-28 2020-05-26 International Business Machines Corporation Controlling gate length of vertical transistors
US10840133B2 (en) * 2018-09-27 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with staggered selective growth
JP2020056104A (ja) 2018-10-02 2020-04-09 エーエスエム アイピー ホールディング ビー.ブイ. 選択的パッシベーションおよび選択的堆積
US10692755B2 (en) 2018-10-24 2020-06-23 International Business Machines Corporation Selective deposition of dielectrics on ultra-low k dielectrics
US10886462B2 (en) 2018-11-19 2021-01-05 International Business Machines Corporation Encapsulated memory pillars
TWI757659B (zh) * 2018-11-23 2022-03-11 美商應用材料股份有限公司 碳膜的選擇性沉積及其用途
JP7286780B2 (ja) * 2019-02-14 2023-06-05 インテグリス・インコーポレーテッド 窒化ケイ素の選択的堆積
JP6860605B2 (ja) * 2019-03-18 2021-04-14 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、およびプログラム
US11965238B2 (en) 2019-04-12 2024-04-23 Asm Ip Holding B.V. Selective deposition of metal oxides on metal surfaces
JP6953480B2 (ja) * 2019-07-31 2021-10-27 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、およびプログラム
US11139163B2 (en) 2019-10-31 2021-10-05 Asm Ip Holding B.V. Selective deposition of SiOC thin films
JP7227122B2 (ja) 2019-12-27 2023-02-21 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理装置、およびプログラム
JP7254044B2 (ja) * 2020-03-25 2023-04-07 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理装置、およびプログラム
TW202140833A (zh) 2020-03-30 2021-11-01 荷蘭商Asm Ip私人控股有限公司 相對於金屬表面在介電表面上之氧化矽的選擇性沉積
TW202140832A (zh) 2020-03-30 2021-11-01 荷蘭商Asm Ip私人控股有限公司 氧化矽在金屬表面上之選擇性沉積
TW202204658A (zh) 2020-03-30 2022-02-01 荷蘭商Asm Ip私人控股有限公司 在兩不同表面上同時選擇性沉積兩不同材料
US11930637B2 (en) 2020-06-19 2024-03-12 Applied Materials, Inc. Confined charge trap layer
US20220127717A1 (en) * 2020-10-27 2022-04-28 Applied Materials, Inc. Selective Deposition Of A Heterocyclic Passivation Film On A Metal Surface
TW202235649A (zh) * 2020-11-24 2022-09-16 荷蘭商Asm Ip私人控股有限公司 填充間隙之方法與相關之系統及裝置
US11756790B2 (en) * 2021-03-09 2023-09-12 Tokyo Electron Limited Method for patterning a dielectric layer
JP7339975B2 (ja) 2021-03-18 2023-09-06 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理装置、及びプログラム
US11702733B2 (en) 2021-05-07 2023-07-18 Applied Materials, Inc. Methods for depositing blocking layers on conductive surfaces

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW411405B (en) * 1997-08-28 2000-11-11 Shipley Co Llc Novel polymers and photoresist compositions, and method for forming positive photoresist relief image
CN1396843A (zh) * 2000-02-02 2003-02-12 住友化学工业株式会社 模制催化剂、制造模制催化剂的方法及制造环氧乙烷化合物的方法
US20060199399A1 (en) * 2005-02-22 2006-09-07 Muscat Anthony J Surface manipulation and selective deposition processes using adsorbed halogen atoms
TW201213592A (en) * 2010-09-10 2012-04-01 Applied Materials Inc Embedded catalyst for atomic layer deposition of silicon oxide
TW201220366A (en) * 2010-10-04 2012-05-16 Applied Materials Inc Atomic layer deposition of silicon nitride using dual-source precursor and interleaved plasma

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2574822B2 (ja) * 1987-12-07 1997-01-22 株式会社日立製作所 半導体装置の製造方法
US6200893B1 (en) 1999-03-11 2001-03-13 Genus, Inc Radical-assisted sequential CVD
JP3797107B2 (ja) * 2000-02-02 2006-07-12 住友化学株式会社 触媒成型体、該触媒成型体の製造方法及びオキシラン化合物の製造方法
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
US6930059B2 (en) * 2003-02-27 2005-08-16 Sharp Laboratories Of America, Inc. Method for depositing a nanolaminate film by atomic layer deposition
US6919636B1 (en) * 2003-07-31 2005-07-19 Advanced Micro Devices, Inc. Interconnects with a dielectric sealant layer
US7132360B2 (en) * 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
US8029698B2 (en) * 2005-04-19 2011-10-04 The Research Foundation Of State University Of New York Production of photoluminescent silicon nanoparticles having surfaces that are essentially free of residual oxygen
WO2008136882A2 (en) * 2007-02-14 2008-11-13 The Board Of Trustees Of The Leland Stanford Junior University Fabrication method of size-controlled, spatially distributed nanostructures by atomic layer deposition
GB2459604B (en) * 2007-02-26 2011-07-06 Wisconsin Alumni Res Found Surface plasmon resonance compatible carbon thin films
US8461026B2 (en) 2007-03-23 2013-06-11 Asahi Kasei Emd Corporation Compound semiconductor lamination, method for manufacturing the same, and semiconductor device
US7763399B2 (en) * 2007-08-31 2010-07-27 Intel Corporation Removal of ionic residues or oxides and prevention of photo-induced defects, ionic crystal or oxide growth on photolithographic surfaces
US8242019B2 (en) 2009-03-31 2012-08-14 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
KR101096031B1 (ko) * 2009-03-31 2011-12-19 한양대학교 산학협력단 자기조립단분자막 형성방법과 이를 이용한 반도체 소자의 구리배선 및 그의 형성방법
US8230720B2 (en) * 2009-11-19 2012-07-31 Honeywell International Inc. Functionalized monolayers for carbon dioxide detection by a resonant nanosensor
US8293658B2 (en) 2010-02-17 2012-10-23 Asm America, Inc. Reactive site deactivation against vapor deposition
US20110308603A1 (en) * 2010-06-17 2011-12-22 Katholieke Universiteit Leuven Method for passivating a silicon surface
WO2012002440A1 (ja) * 2010-06-29 2012-01-05 京セラ株式会社 半導体基板の表面処理方法、半導体基板、および太陽電池の製造方法
US8778816B2 (en) * 2011-02-04 2014-07-15 Applied Materials, Inc. In situ vapor phase surface activation of SiO2
US20120201959A1 (en) * 2011-02-04 2012-08-09 Applied Materials, Inc. In-Situ Hydroxylation System
US8728955B2 (en) 2012-02-14 2014-05-20 Novellus Systems, Inc. Method of plasma activated deposition of a conformal film on a substrate surface
WO2013177326A1 (en) 2012-05-25 2013-11-28 Advanced Technology Materials, Inc. Silicon precursors for low temperature ald of silicon-based thin-films
US10047435B2 (en) 2014-04-16 2018-08-14 Asm Ip Holding B.V. Dual selective deposition
KR102185458B1 (ko) 2015-02-03 2020-12-03 에이에스엠 아이피 홀딩 비.브이. 선택적 퇴적

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW411405B (en) * 1997-08-28 2000-11-11 Shipley Co Llc Novel polymers and photoresist compositions, and method for forming positive photoresist relief image
CN1396843A (zh) * 2000-02-02 2003-02-12 住友化学工业株式会社 模制催化剂、制造模制催化剂的方法及制造环氧乙烷化合物的方法
US20060199399A1 (en) * 2005-02-22 2006-09-07 Muscat Anthony J Surface manipulation and selective deposition processes using adsorbed halogen atoms
TW201213592A (en) * 2010-09-10 2012-04-01 Applied Materials Inc Embedded catalyst for atomic layer deposition of silicon oxide
TW201220366A (en) * 2010-10-04 2012-05-16 Applied Materials Inc Atomic layer deposition of silicon nitride using dual-source precursor and interleaved plasma

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