TWI716621B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI716621B
TWI716621B TW106126037A TW106126037A TWI716621B TW I716621 B TWI716621 B TW I716621B TW 106126037 A TW106126037 A TW 106126037A TW 106126037 A TW106126037 A TW 106126037A TW I716621 B TWI716621 B TW I716621B
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wiring
width
pad
slit
semiconductor device
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宇都宮裕之
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日商艾普凌科有限公司
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Abstract

本發明在與連接於相對而言面積廣的配線或墊1的第2配線2的接合部位6的附近設置狹縫3。藉此，可使由光微影步驟中的烘烤處理或UV固化等所引起的抗蝕劑的拉伸應力分散，並可緩和第2配線端的抗蝕劑的收縮、變形，且可使藉由蝕刻而形成的配線的尺寸及形狀穩定化。

Description

半導體裝置
本發明是有關於一種具有面積廣的配線或墊與連接於面積廣的配線或墊的細寬配線的半導體裝置。
半導體元件及配線是反覆進行於半導體基板上呈所需的形狀加工絕緣膜或導電性膜等的步驟而形成。通常藉由光微影步驟而於規定的膜上形成抗蝕劑圖案，以所述抗蝕劑圖案為遮罩，藉由蝕刻等加工而獲得所需的圖案或尺寸。於進行蝕刻加工的情況下，以提高抗蝕劑的密接性或耐蝕刻性為目的，而對抗蝕劑圖案進行烘烤處理或紫外線(Ultraviolet，UV)固化等處置。
[現有技術文獻] [專利文獻]
[專利文獻1]日本專利特開2004-22653號公報
然而，於形成連接於面積廣的配線或墊的細寬的配線的情況下，產生以下問題。如圖4所示，藉由光微影步驟而形成於金屬膜上的抗蝕劑圖案於步驟內進行烘烤處理或UV固化，因此與面積廣的配線或墊1相對應的抗蝕劑圖案在抗蝕劑的中心方向上收縮。抗蝕劑圖案的上部的收縮率高，對應於抗蝕劑的收縮率，抗 蝕劑圖案端部的傾斜坡度變緩，例如，於配線或墊1的外周部產生應變等，難以藉由蝕刻而穩定地形成所需的尺寸、形狀。連接於面積廣的配線或墊1的細寬的配線2除自身的收縮以外，亦會受到所述面積廣的配線或墊1的收縮的影響，從而產生抗蝕劑圖案的大幅收縮。與面積廣的配線或墊1同樣地，抗蝕劑圖案端的傾斜坡度亦變緩，難以藉由蝕刻而穩定地形成所需的尺寸、形狀。嚴格來說，細寬的配線2應該覆蓋缺損部8而進行配線形成，但介層接觸窗(VIA contact)5部分地露出而未由細寬的配線2被覆。
因此，本發明的目的在於提供一種可呈所需的尺寸或形狀穩定地形成與面積廣的配線或墊連接的細寬的配線的半導體裝置。
為了解決所述課題，而形成在細寬的配線與面積廣的配線或墊連接的接合部位的附近設置狹縫的半導體裝置。
根據本發明，可在連接於面積廣的配線或墊的細寬的配線的形成中，形成所需的尺寸及形狀的配線。
1:第1配線或墊
2:第2配線
3:狹縫
4:第3配線
5:介層接觸窗
6:第1接合部位
7:第2接合部位
8:第2配線缺損部
9:第3配線缺損部
a:第1配線或墊的第1方向上的線寬
b:第1配線或墊的第2方向上的線寬
c:第2配線的線寬(第1方向上的線寬)
d:第2配線的長度(第2方向上的線寬)
e:狹縫的長度(第1方向上的寬)
f:狹縫與第1接合部位的距離
g:第3配線的線寬(第2方向上的線寬)
圖1是本發明的第1實施形態的半導體裝置的平面圖。
圖2是本發明的第2實施形態的半導體裝置的平面圖。
圖3(a)、圖3(b)是本發明的第3實施形態的半導體裝置 的平面圖。
圖4是現有的半導體裝置的平面圖。
以下，使用圖式對本發明的實施形態進行說明。
圖1是本發明的第1實施形態的半導體裝置的平面圖，且是圖示半導體裝置中的絕緣膜上的金屬配線者。金屬配線配置於設置在半導體基板的表面的絕緣膜上，與半導體元件一起構成半導體裝置。示出有作為縱(第1方向)的寬a為50μm以上且橫(第2方向)的寬b為50μm以上的面積廣的配線的第1配線或墊1與連接於第1配線或墊1的細寬的第2配線2。細寬的第2配線2是形成於與第1配線1相同的層的配線。第2配線2的一端藉由接合部位6而與第1配線1連接，於第2配線2的一端的相反側的另一端附近設置有介層接觸窗5，介層接觸窗5不露出地由第2配線2被覆。
第2配線2的線寬c窄於第1配線或墊1的縱橫的寬a、寬b，於連接兩者的接合部位6的附近的第1配線或墊1內設置有狹縫3。此處，自接合部位6至狹縫3的距離f理想為20μm以內。然而，認為：若如所述般於第2配線2的附近設置狹縫3，則電流密度局部變高，配線壽命因遷移而降低，因此理想為預先使狹縫3與第2配線2的距離f大於第2配線2的線寬c。
狹縫3的長度e理想為大於第2配線2的線寬c，但例如若有第2配線2的線寬c的1/2~同等的長度，則可獲得效果。 另外，理想為如圖1所示，對應於第2配線2的線寬方向而呈縱長設置一個狹縫，狹縫3可被分割，於該情況下，若經分割的狹縫的合計長度為所述以上，則可獲得其效果。再者，經分割的小狹縫的一個的長度理想為至少2μm左右以上。
雖亦取決於面積廣的配線或墊1或者第2配線2的線寬c，但於第2配線2的長度d小的情況下，應力強，例如，若第2配線2的長度d為20μm以下左右的範圍，則可獲得狹縫3的效果。
另外，圖1中，狹縫3除第2配線2的附近以外，亦於第1配線或墊1內配置有多個，自配置於接合部位6以外的狹縫3至配置於第2配線2的附近的狹縫3的影響少，其配置並無限制。即，多個狹縫3可均等或無規地配置於第1配線或墊1內。當然，狹縫3亦可僅配置於第2配線2的附近。
此處，對設置於第1配線或墊1內的狹縫3的效果進行說明。
於無狹縫的情況下，藉由光微影步驟而形成遍及第1配線或墊的第2方向上的線寬b及第2配線的長度d的寬廣的抗蝕劑圖案，於進行剖面觀察時，該第2配線端的抗蝕劑圖案保持極緩的傾斜。其是由藉由烘烤處理或UV固化處理而抗蝕劑圖案收縮所引起，於無狹縫的情況下，由於形成遍及線寬b及第2配線的長度d的寬廣的抗蝕劑圖案，因此收縮會大幅影響抗蝕劑圖案端部。相對於此，於如本實施例般在第1配線或墊1內設置狹縫3 的情況下，寬廣的抗蝕劑圖案由狹縫3分割，由烘烤處理或UV固化處理所引起的抗蝕劑圖案的收縮的影響變小。如無狹縫的情況般抗蝕劑圖案保持緩的傾斜時，該傾斜中的抗蝕劑膜厚變得薄於配線的蝕刻所需的原本的膜厚，因此導致第2配線的缺損，但於本實施例的情況下，可確保可耐蝕刻的抗蝕劑膜厚，不會導致缺損而不會使介層接觸窗5露出。
圖2是本發明的第2實施形態的半導體裝置的平面圖。
本實施形態與第1實施形態不同的方面在於：於第1配線或墊1的一邊設置有多個第2配線2。於多個第2配線2與第1配線或墊1連接的各個接合部位6的附近分別設置有相對應的狹縫3。此處，雖僅於多個第2配線2的接合部位6的附近設置有狹縫3，但亦可與圖1同樣地沿第1配線或墊1的邊設置狹縫3。藉此，可呈所需的形狀形成第1配線或墊1的端部。
使用圖3(a)及圖3(b)的平面圖對本發明的第3實施形態的半導體裝置進行說明。
第3實施形態與第1實施形態不同的方面在於：藉由和第2配線2與第1配線1連接的一端為相反側的另一端而連接於第3配線4。圖3(a)示出本實施形態的圖，圖3(b)示出現有圖。
首先，使用圖3(b)進行說明。第2配線2藉由第1接合部位6而連接於具有廣面積的第1配線或墊1，藉由第2接合部位7而連接於作為線寬g的細寬配線的第3配線4。於半導體基 板上製成金屬膜後，藉由光微影步驟而於金屬膜上形成抗蝕劑圖案時，抗蝕劑圖案藉由烘烤處理或UV固化處理而收縮，抗蝕劑圖案被拉至第1配線或墊1側，於第3配線4的第2接合部位7的相反側的抗蝕劑圖案中產生膜厚極薄的部分。該部分中，對於蝕刻而言並非充分的抗蝕劑膜厚，因此若進行蝕刻，則於第3配線4的一部分產生缺損部9。該缺損部9中，電流密度變高，且引起由電遷移所造成的配線壽命的降低。
表示第3實施形態的圖3(a)中，於第1接合部位6的附近的第1配線或墊1內設置有狹縫3，藉由該狹縫3的配置而抗蝕劑圖案的收縮得到緩和，圖3(b)的相當於缺損部9的端部中的抗蝕劑圖案的剖面形狀變陡峭，可確保可耐蝕刻的抗蝕劑膜厚。因此，不會導致缺損，亦不存在由電遷移所造成的配線壽命的降低的擔憂。
再者，圖3(a)中，第2配線2與第3配線4呈T字型連接，即便於呈L字型連接的情況下，亦可藉由設置狹縫3而獲得相同的效果。
如以上所說明般，根據本發明，可形成所需的尺寸及形狀的配線。
1‧‧‧第1配線或墊
2‧‧‧第2配線
3‧‧‧狹縫
5‧‧‧介層接觸窗
6‧‧‧第1接合部位
a‧‧‧第1配線或墊的第1方向上的線寬
b‧‧‧第1配線或墊的第2方向上的線寬
c‧‧‧第2配線的線寬(第1方向上的線寬)
d‧‧‧第2配線的長度(第2方向上的線寬)
e‧‧‧狹縫的長度(第1方向上的寬)
f‧‧‧狹縫與第1接合部位的距離

Claims (8)

  1. 一種半導體裝置，其包括：半導體基板；絕緣膜，設置於所述半導體基板的表面；第1配線，配置於所述絕緣膜上，在第1方向上具有第1寬及在與所述第1方向垂直的第2方向上具有第2寬；第2配線，在所述第1方向上具有窄於所述第1寬及所述第2寬的第3寬；狹縫，和所述第1配線與所述第2配線的一端的設置於所述第1方向上的第1接合部位相距所述第3寬的長度以上而設置於所述第1配線，在所述第1方向上具有成為所述第3寬的1/2以上的長度的第4寬；以及第3配線，接合於與所述第2配線的一端為相反側的另一端，所述第3配線包括與所述第1配線和所述第2配線相同的層，且沿所述第1方向延伸。
  2. 如申請專利範圍第1項所述的半導體裝置，其中，在所述第1方向上，所述狹縫被分割而包含多個小狹縫。
  3. 如申請專利範圍第1項所述的半導體裝置，其中，所述第2配線於所述第1配線的一邊配置有多個，且於所述第1配線與所述第2配線的一端的所述第1接合部位附近分別設置有多個所述狹縫。
  4. 如申請專利範圍第1項至第3項中任一項所述的半導 體裝置，其中，於與所述第2配線的一端為相反側的另一端具有介層接觸窗。
  5. 一種半導體裝置，其包括：半導體基板；絕緣膜，設置於所述半導體基板的表面；墊，配置於所述絕緣膜上，在第1方向上具有第1寬及在與所述第1方向垂直的第2方向上具有第2寬；第2配線，在所述第1方向上具有窄於所述第1寬及所述第2寬的第3寬；狹縫，和所述墊與所述第2配線的一端的設置於所述第1方向上的第1接合部位相距所述第3寬的長度以上而設置於所述墊，在所述第1方向上具有成為所述第3寬的1/2以上的長度的第4寬；以及第3配線，接合於與所述第2配線的一端為相反側的另一端，所述第3配線包括與所述墊和所述第2配線相同的層。
  6. 如申請專利範圍第5項所述的半導體裝置，其中，在所述第1方向上，所述狹縫被分割而包含多個小狹縫。
  7. 如申請專利範圍第5項所述的半導體裝置，其中，所述第2配線於所述墊的一邊配置有多個，且在所述墊與所述第2配線的一端的所述第1接合部位附近分別設置有多個所述狹縫。
  8. 如申請專利範圍第5項至第7項中任一項所述的半導體裝置，其中，於與所述第2配線的一端為相反側的另一端具有 介層接觸窗。
TW106126037A 2016-08-10 2017-08-02 半導體裝置 TWI716621B (zh)

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