CN107731777A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107731777A
CN107731777A CN201710674574.0A CN201710674574A CN107731777A CN 107731777 A CN107731777 A CN 107731777A CN 201710674574 A CN201710674574 A CN 201710674574A CN 107731777 A CN107731777 A CN 107731777A
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wiring
width
semiconductor device
gap
pad
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宇都宫裕之
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Seiko Instruments Inc
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Seiko Instruments Inc
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Abstract

本发明提供一种半导体装置，在面积相对较大的布线或焊盘(1)与和它们相连接的第2布线(2)之间的接合部位(6)附近设置有缝隙(3)。由此，能够分散由于光刻工艺中的烘烤处理和UV固化等产生的抗蚀剂的拉伸应力，从而能够缓和第2布线端的抗蚀剂的收缩、变形，能够使通过蚀刻而形成的布线的尺寸和形状稳定。

Description

半导体装置
技术领域
本发明涉及具有大面积的布线或焊盘以及与其相连接的窄幅布线的半导体装置。
背景技术
半导体元件和布线是通过在半导体衬底上反复地进行将绝缘膜或导电性膜等加工成期望的形状的工艺而形成的。通常是通过光刻工艺在规定的膜上形成抗蚀剂图案并将其作为掩模从而通过蚀刻等加工来获得期望的图案和尺寸。在进行蚀刻加工的情况下，以提高抗蚀剂的紧贴性和蚀刻的耐受性为目的，在抗蚀剂图案上进行烘烤处理和UV固化等处置。
专利文献1：日本特开2004-22653号公报
然而，在形成与大面积的布线或焊盘相连接的窄幅的布线的情况下，会产生如下的问题。如图4所示，通过光刻工艺在金属膜上形成的抗蚀剂图案由于在工艺中进行了烘烤处理和UV固化，因此对应于大面积的布线或焊盘1的抗蚀剂图案向抗蚀剂的中心方向收缩。抗蚀剂图案的上部的收缩率高，并且抗蚀剂图案端部的倾斜坡度根据抗蚀剂的收缩率而变缓，因此例如在布线或焊盘1的外周部发生变形等，难以通过蚀刻稳定地形成期望的尺寸/形状。与大面积的布线或焊盘1相连接的窄幅的布线2除了自身的收缩以外，还受到上述的大面积的布线或焊盘1的收缩的影响，从而会发生较大的抗蚀剂图案的收缩。与大面积的布线或焊盘1相同，在抗蚀剂图案端部的倾斜坡度也变缓，难以通过蚀刻稳定地形成期望的尺寸/形状。原本窄幅的布线2应该是覆盖缺损部8而形成布线的，但是过孔接触区(VIAContact)5局部地露出而没有被窄幅的布线2包覆。
发明内容
因此，本发明的目的在于提供能够实现将与大面积的布线或焊盘连接的窄幅的布线稳定地形成为期望的尺寸和形状的半导体装置。
为了解决上述课题，将半导体装置设为，在大面积的布线或焊盘与窄幅的布线相连接的接合部位附近设置了缝隙。
根据本发明，在形成与大面积的布线或焊盘相连接的窄幅的布线时，能够形成期望的尺寸和形状的布线。
附图说明
图1是本发明的第1实施方式的半导体装置的俯视图。
图2是本发明的第2实施方式的半导体装置的俯视图。
图3是本发明的第3实施方式的半导体装置的俯视图。
图4是现有的半导体装置的俯视图。
标号说明
1：第1布线或焊盘；2：第2布线；3：缝隙；4：第3布线；5：过孔接触区；6：第1接合部位；7：第2接合部位；8：第2布线缺损部；9：第3布线缺损部；a：第1布线或焊盘在第1方向上的线宽；b：第1布线或焊盘在第2方向上的线宽；c：第2布线的线宽(第1方向上的线宽)；d：第2布线的长度(第2方向上的线宽)；e：缝隙的长度(第1方向上的宽度)；f：缝隙与第1接合部位之间的距离；g：第3布线的线宽(第2方向上的线宽)。
具体实施方式
以下，使用附图对本发明实施方式进行说明。
图1是本发明的第1实施方式的半导体装置的俯视图，其中图示出半导体装置的绝缘膜上的金属布线。金属布线配置于在半导体衬底的表面上设置的绝缘膜上，从而与半导体元件一同构成半导体装置。示出了作为纵向(第1方向)的宽度a为50μm以上且横向(第2方向)的宽度b为50μm以上这样大面积的布线的第1布线或焊盘1和与第1布线或焊盘1相连接的窄幅的第2布线2。窄幅的第2布线2是与第1布线1形成在同一层上的布线。第2布线2的一端在接合部位6处与第1布线1连接，在第2布线2的一端的相反侧的另一端附近设置有过孔接触区5，过孔接触区5被第2布线2包覆而不露出。
第2布线2的线宽c比第1布线或焊盘1的纵向和横向的宽度a、b窄，并且在两者相连接的接合部位6附近的第1布线或焊盘1内设置有缝隙3。这里，从接合部位6到缝隙3的距离f优选在20μm以内。然而，考虑到这样在第2布线2附近设置缝隙3时电流密度局部增高，从而因迁移导致的布线寿命的下降，因此，优选将缝隙3与第2布线2之间的距离f设置成比第2布线2的线宽c大。
关于缝隙3的长度e，优选的是比第2布线2的线宽c大，但是，例如只要是第2布线2的线宽c的1/2～同等的长度即可获得效果。另外，如图1所示，虽然优选的是与第2布线2的线宽方向对应地将1个缝隙设置成纵向较长，但缝隙3也可以被分割，在这种情况下，只要被分割的缝隙的总长度为上述长度以上即可获得其效果。另外，被分割后的1个小缝隙的长度优选是至少2um程度。
应力是基于大面积的布线或焊盘1和第2布线2的线宽c的，但在第2布线2的长度d较小的情况下应力较强，例如只要第2布线2的长度d处于20μm以下程度的范围即可获得缝隙3的效果。
另外，在图1中，缝隙3除了配置在第2布线2附近以外，还在第1布线或焊盘1内配置有多个，在除了接合部位6以外的位置处配置的缝隙3对在第2布线2附近配置的缝隙3的影响较小，该配置不受限制。即，也可以是在第1布线或焊盘1内均匀或随机地配置多个缝隙3。当然，也可以是只在第2布线2附近配置缝隙3。
这里，对在第1布线或焊盘1内设置的缝隙3的效果进行说明。
在没有缝隙的情况下，通过光刻工艺形成了遍及第1布线或焊盘在第2方向上的线宽b和第2布线的长度d的宽幅的抗蚀剂图案，而该第2布线端部的抗蚀剂图案在剖视观察时具有极缓的倾斜度。这是由于通过烘烤处理和UV固化处理使抗蚀剂图案收缩而导致的，在没有缝隙的情况下，由于形成了遍及线宽b和第2布线的长度d的宽幅的抗蚀剂图案，因此收缩对抗蚀剂图案端部的影响较大。与之相对，如本实施例那样，在第1布线或焊盘1内设置有缝隙3的情况下，宽幅的抗蚀剂图案被缝隙3断开，因烘烤处理和UV固化处理造成的抗蚀剂图案的收缩的影响减小。当像没有缝隙的情况那样，抗蚀剂图案具有较缓的倾斜度时，该倾斜度下的抗蚀剂膜厚比布线的蚀刻所需的原本的膜厚薄，因此造成了第2布线的缺损，但在本实施例的情况下，能够保证可耐蚀刻的抗蚀剂膜厚，不会造成缺损，并且过孔接触区5不会露出。
图2是本发明的第2实施方式的半导体装置的俯视图。
本实施方式与第1实施方式的不同之处在于，在第1布线或焊盘1的一边设置有多条第2布线2。在多条第2布线2与第1布线或焊盘1连接的每个接合部位6附近分别设置有对应的缝隙3。这里，只是在多条第2布线2的连接位置6附近设置有缝隙3，但是，与图1相同地也可以沿着第1布线或焊盘1的边设置缝隙3。这样，第1布线或焊盘1的端部形成为期望的形状。
使用图3的(a)和图3的(b)对本发明的第3实施方式的半导体装置进行说明。
第3实施方式与第1实施方式的不同之处在于，第2布线2利用与第1布线1连接的一端的相反侧的另一端连接于第3布线4。图3的(a)示出了本实施方式的图，图3的(b)示出了现有技术的图。
首先，使用图3的(b)进行说明。第2布线2在第1接合部位6处与大面积的第1布线或焊盘1连接，在第2接合部位7处与作为线宽g的窄幅布线的第3布线4连接。在半导体衬底上形成金属膜之后，在金属膜上通过光刻工艺形成抗蚀剂图案，此时抗蚀剂图案通过烘烤处理和UV固化处理而收缩，从而使抗蚀剂图案靠近第1布线或焊盘1侧，因此在第3布线4的第2接合部位7的相反侧的抗蚀剂图案上产生膜厚极薄的部分。由于该部分不具有足够进行蚀刻的抗蚀剂厚度，因此在进行蚀刻时，第3布线4的一部分产生缺损部9。该缺损部9使电流密度增高，从而发生由于电迁移导致的布线寿命的下降。
在示出第3实施方式的图3的(a)中，在第1接合部位6附近的第1布线或焊盘1内设置有缝隙3，通过该缝隙3的配置，缓和了抗蚀剂图案的收缩，相当于图3的(b)的缺损部9的端部的抗蚀剂图案的截面形状变得陡峭，能够保证可耐蚀刻的抗蚀剂膜厚。因此，不会导致缺损，也没有由于电迁移导致的布线寿命的下降的担忧。
另外，在图3的(a)中，第2布线2与第3布线4连接成T字形，但在连接成L字形的情况下，通过设置缝隙3也能够获得相同的效果。
如以上说明的那样，根据本发明，能够形成期望的尺寸和形状的布线。

Claims (10)

1.一种半导体装置，该半导体装置具有：
半导体衬底；
绝缘膜，其设置在所述半导体衬底的表面；
第1布线，其配置在所述绝缘膜上，并且在第1方向上具有第1宽度，在与所述第1方向垂直的第2方向上具有第2宽度；
第2布线，其在所述第1方向上具有比所述第1宽度和所述第2宽度窄的第3宽度；以及
缝隙，其设置于所述第1布线且在所述第1方向上具有第4宽度，所述第4宽度的大小为所述第3宽度的1/2以上，所述缝隙与第1接合部位相隔所述第3宽度的大小以上的距离，其中所述第1接合部位是所述第1布线与所述第2布线的一端之间沿所述第1方向设置的接合部位。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述第1方向上，所述缝隙被断开而由多个小缝隙构成。
3.根据权利要求1所述的半导体装置，其特征在于，
在所述第1布线的一边配置有多条所述第2布线，在所述第1布线与所述第2布线的一端之间的第1接合部位附近分别设置有多个所述缝隙。
4.根据权利要求1至3中的任一项所述的半导体装置，其特征在于，
在所述第2布线的一端的相反侧的另一端接合有第3布线。
5.根据权利要求1至3中的任一项所述的半导体装置，其特征在于，
在所述第2布线的一端的相反侧的另一端具有过孔接触区。
6.一种半导体装置，该半导体装置具有：
半导体衬底；
绝缘膜，其设置在所述半导体衬底的表面；
焊盘，其配置在所述绝缘膜上，并且在第1方向上具有第1宽度，在与所述第1方向垂直的第2方向上具有第2宽度；
第2布线，其在所述第1方向上具有比所述第1宽度和所述第2宽度窄的第3宽度；以及
缝隙，其设置于所述焊盘且在所述第1方向上具有第4宽度，所述第4宽度的大小为所述第3宽度的1/2以上，所述缝隙与第1接合部位相隔所述第3宽度的大小以上的距离，其中所述第1接合部位是所述焊盘与所述第2布线的一端之间沿所述第1方向设置的接合部位。
7.根据权利要求6所述的半导体装置，其特征在于，
在所述第1方向上，所述缝隙被断开而由多个小缝隙构成。
8.根据权利要求6所述的半导体装置，其特征在于，
在所述焊盘的一边配置有多条所述第2布线，在所述焊盘与所述第2布线的一端之间的第1接合部位附近分别设置有多个所述缝隙。
9.根据权利要求6至8中的任一项所述的半导体装置，其特征在于，
在所述第2布线的一端的相反侧的另一端接合有第3布线。
10.根据权利要求6至8中的任一项所述的半导体装置，其特征在于，
在所述第2布线的一端的相反侧的另一端具有过孔接触区。
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