1249226 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體積體電路之製造技術，特別是關於可以改 良採對角佈局内連線結構的積體電路效能之技術。 【先前技術】 如該行業者所知，晶片中的微電晶體電子元件通常係藉由多層 採格狀或直角方式佈局邏輯的内連線結構構成電連結組態。這種 内連線方式又被業界泛稱為，「曼哈頓(Manhattan)」佈局，乃取其 ，似城市中的方正格狀街道之意。而不同層之間_連線導線則 是藉由在丫财向_連線金屬元件，或者又稱為介層插塞 (via)，始能構成讓電子訊號暢通的路徑。 •數年來片衣4業者克服了許多技術障礙，加上不斷地改良 製程工藝，例如從〇.18微米製程、㈣微米製程，到9〇奈米世代 或更小，而達成使晶片體積更加微小化的目的，也使得晶片中的 内連線路徑更為驗。為了使運算速度更為提昇，⑼製造業者 使用了許多方法，例如採關製程取代傳統_金屬、採用石夕覆 邑緣(SOI)基板衣作半導體树、獅應變卿論e—)技術 以及低介電常數樹_。_，儘了前述這些先進技術， 1249226 在内連線佈局上仍始終維持著傳統的格狀繞線邏輯，而未採用兩 元件之間最近的直線佈局或對角(diagonal)佈局。 在傳統的「曼哈頓」佈局邏輯中，每一金屬導線層有其較佳的 固定配線佈局方向，各層導線可沿著其相對的方向被畫出，舉例 來說，若第一層導線的較佳配線方向為水平方向，則在其上的第 二層導線的配線方向即呈垂直方向，並依此類推。雖然在另一領 域的印刷電路板製程中配線方向有呈對角佈局者，然而，卻未曾 被應用在晶片設計領域中。這是由於晶片的線路設計相較於電路 板設計更加地複雜精細，且每單一晶片中含有更多的整合元件， 需要一併考量。 在2001年，數家處理器廠商以及設備商組成的半導體供應鍊 協會組織：the X initiative，決定克服傳統在内連線上的佈局限制， 而讓晶片設計者能夠在水平或垂直方向之外，多了在對角方向的 選擇性，同時並將這種概念稱為「X結構(XArchitecture)」，而採 「X結構」做内連線佈局的晶片又稱做「X晶片」。相較於傳統採 用「曼哈頓」佈局邏輯的晶片，採用「X結構」的相同晶片顯然 需要較短的導線長度、較少的介層插塞數目，因此也較節省成本。 然而，儘管有著上述優點，這種先進的「X結構」内連線佈局 邏輯仍有一些缺點猶待克服與改善，才能使晶片的效能與操作時 的可靠度進一步被提昇。 1249226 【發明内容】 據此，本發明之主要目的在提供一種改良之内連線結構或内連 線佈局，可以改良晶片的運作效能以及可靠度。 為達前述之發明目的，本發明之第一較佳實施例提供一種内連 線佈局，包含有沿著垂直方向延伸之下層金屬導線層(Metal_n); 沿著水平方向之45度角方向斜向延伸的上層金屬導線層 (Metal一n+l);以及截面積大小互不相等之第一與第二金屬介層插 塞，設於該下層金屬導線層與該上層金屬導線層之間，用以電連 接該上、下金屬導線層，其中該第一金屬介層插塞之截面積大於 該第二金屬介層插塞之截面積，藉此補償通過該下層金屬導線層 或該上層金屬導線層之不均勻電流阻塞現象。 本發明之第二較佳實施例披露一種内連線佈局結構，包含有沿 著Y轴垂直方向延伸之下層金屬導線層(Metal_n);沿著X軸水平 方向之45度角方向斜向延伸的上層金屬導線層(Metal_n+1);以及 複數個截面積大小約略相等之金屬介層插塞，設於該下層金屬導 線層與該上層金屬導線層之間，用以電連接該上、下金屬導線層， 該複數個金屬介層插塞係從下層金屬導線層的左緣至右緣在排列 上採由密到疏的方式排列成單一列組態。 為了使貴審查委員能更近一步了解本發明之特徵及技術内 Ϊ249226 f實施方式】 請參閱第3圖，其緣示的是在積體電路中典型使用「X 的部分金屬内連線佈局之放大上視示意圖。如第3圖所示，内連 線結構1〇包含有下層金屬導線層12(其在第3圖中以，編μ n，，表 不，其中η代表下層金屬導線層12在㈣電路⑼巾騎處内連 線層數)，下層金屬導線層12並沿著垂直方向或者財參考座標的 γ軸方向延伸。内連線結構1G另包含有沿著水平方向之45度角 或者圖中參考座標X軸之45度財向斜向延伸的上層金屬導線層 K其在第3目中以”Metal_n+1，，表示），以及複數個截面積大小約 略相等之金屬介層插塞24a〜2知’設於下層金屬導線層12與上層 金屬導線層W之間’用以電連接上、下金屬導線層。其中金屬介 層插塞24a〜24e在此例中為矩形截面，具有邊長d，且兩相鄰金屬 介層插塞之間的間距也大致相等(傳統的佈局規則）。為方便說明， 在圖中並未繪示金屬層間介電層。 在操作時’上層金屬導線層14可能接至等電位，如此使得電 流可經由下層金屬導線層12、金屬介層插塞24a〜24e，以及上層 金屬導線層14所構成的導電路徑完成電子訊號的傳遞 ，反之亦 然。然而’上述之内連線結構1〇的問題之一是電流在通過上層金 1249226 屬導線層14時，卻會有不均勻電流阻塞現象發生，而可能因此導 致元件操作時的可靠度問題。 為了解釋這種不均勻電流阻塞現象，第3圖中以五條不同的路 徑作為說明，分別是路徑A、路徑B、路徑C、路徑D以及路徑E。 這五條路徑係分別針對導通下層金屬導線層12與上層金屬導線層 14之金屬介層插塞24a〜24e，其中由於路徑A介於等電位位置16 以及金屬介層插塞24a之間的距離為最長，因此它比較其它的路 徑而言也就具有最大的路徑電阻。理論上，以這五個路徑互相比 較，路徑電阻最大的是路徑A，其次為路徑B，再其次為路徑◦， 然後為路徑D，最小為路徑E。由此可知，上層金屬導線層以在 操作日^顯然於其寬度方向w上，表現出大小不同的電阻梯度，這 造成電流將選擇流過電阻最小的路徑，也就是在此例中的路徑E， 導致吼號延遲、效能上的減損與可靠度等問題。 本發明之主要目的即是在提出新的佈局規則或方法，以及新的 結構，應用在採行「X結構」内連線佈局邏輯的積體電路製造技 術中’而能夠改善前述之不均勻電流阻塞現象。通常，前述之不 均勻電/細塞現象發生在第—層對角斜向配、_金屬導線層(通常 為1C中的8或9層内連線結構中的第4或第5層金屬），以及在第 一層對角斜向配線的金屬導線層下—層採「曼哈頓」佈局邏輯的 金屬層(通常為1C中的8或9層内連線結構中的第3或第4層金 屬，但不限於此)之間。 1249226 接著，請參閱第1圖，其緣示的是本發明第一較佳實施例在積 體電路中使用「X結構」（從第(n+1)層金屬層開始)以及「曼哈頓」 佈局(從第1層金屬到第⑻層金屬，例如n=3)的部分金屬内連線佈 局100之放大上視示意圖。為簡化說明，圖中的金屬層間介電層 亚未標7F出來。如第1圖所示，内連線結構1〇〇包含有沿著垂直 ， 方向或者圖中參考座標的γ軸方向延伸之下層金屬導線層 Π(以’’Metal一η”表示）、沿著水平方向之μ度角或者圖中參考座標 X軸之45度角方向斜向延伸的上層金屬導線層14(以”Metal_n+1 ” 表示），以及複數個截面積大小不相等之金屬介層插塞 鲁 124a〜124e，設於下層金屬導線層12與上層金屬導線層14之間， 用以電連接上、下金屬導線層。在此實施例中，金屬介層插塞 / 124a〜124e係從下層金屬導線層12的左緣至右緣排列成單一列組 - 態。在其它實施例中，金屬介層插塞124a〜124e亦可以做45度旋 轉，但不限於此。 在此實施例中，金屬介層插塞124a〜124e在佈局圖上呈矩形截 _ 面。相較於第3圖中大小相等的金屬介層插塞24a〜24e，金屬介層 插塞124a〜124e係經過重新改變尺寸，以補償前述之不均勻電流 阻塞現象。如前所述，由於路徑電阻最大的是路徑A，其次為路 -徑B，再其次為路徑C，然後為路徑D，最小為路徑e，上層金屬 ’ 導線層14在操作時會在其寬度方向W上，表現出大小不同的電 阻梯度，造成電流將選擇流過電阻最小的路徑，為補償這個電阻 梯度差異，本發明將金屬介層插塞124a的尺寸山相較於位於金屬 11 1249226 介層減他右侧之其它金屬介層插塞伽〜咖調敕至 然後將金屬介層插塞遍的尺寸調整為次大，然後^向=修正 金屬介層減施〜1故的尺寸。結果如第i騎示，金屬介芦 插塞馳〜馳的尺寸，以㈣表示，其大小依序為心^ >d4>d5。由於金屬介層插塞124a的尺寸最大，因此在操作時3 . 較多的電流會通過金屬介躲塞咖，崎關償上層金料線, 層14的電阻梯度差異。 ' 請參閱第2圖，其緣示的是本發明第二較佳實施例在積體電路修 中使用「X結構」（從第(n+l)層金屬層開始)的部分金屬内連線佈 局2〇0之放大上視不意圖。圖中的金屬層間介電層並未標示出來。， 如第2圖所示，内連線結構綱同樣包含有沿著垂直方向或者圖\ 中參考座標的γ軸方向延伸之下層金屬導線層12(以，，Metal』，，表 不）、沿著水平方向之45度角或者圖中參考座標χ軸之45度角方 向斜向延伸的上層金屬導線層14(以，，Metal—n+1，，表示），以及複數 個截面積大小約略相等之金屬介層插塞124a〜124e，設於下層金屬籲 導線層12與上層金屬導線層14之間，用以電連接上、下金屬導 線層。金屬介層插塞124a〜124e係從下層金屬導線層12的左緣至 右緣排列成單一列組態。 - r 在此實施例中，金屬介層插塞124a〜124e在佈局圖上仍然呈矩 形截面狀’但不限於此。相較於第3圖中大小相等的金屬介層插 塞24a〜24e，金屬介層插塞雖然也是大小相同，但是卻 12 1249226 是經過重新制，以補翁述之稍句電餘塞聽。其中，金 屬介層插塞伽與金屬介層插塞迦之間的距離以符號Sl表. 示’金屬介層插塞義與金屬介層插塞魏之間的距離以符號 S2表不’金屬"層插塞咖與金屬介層插塞⑽之間的距離以 符號S3表不’而金屬介層插塞侧與金屬介層插塞魏之間的 距離以符號&表示。諸路徑電阻最大的是路徑a，其次為路握 B ’再U馳C，然後為路徑D，最小為路徑E，上層金屬導 線層Μ在操作時會在其寬度方向胃上，表現歧小不同的電阻 梯度’造成電流將選擇流過電阻最小的路徑，為補償這個電阻梯 度差八本么a月將金屬介層插塞1;2如與金属介層插塞1施之間 的距離Sl調整至最小，然後依序向上修正金屬介層插塞124b與金 屬；丨層插塞12如之間的距離&、金屬介層插塞與金屬介層 插塞測之間的距離&以及金屬介層插塞⑽與金屬介層插^ 124e之間的距離S4。結果如第2圖所示，Si<s2<s^S4，使位 於同-列的金屬介層插塞魏〜耻在排列上採由密到疏的方 式，因此在操作時’較多的電流會通過路徑A或B，而得以補償 上層金屬導線層14的電阻梯度差異。 =發明之其它實施财，也可以有第二刺金屬介層插塞， 其與前述實施中的前一列介層插塞平行排列，並且可與前一列的 介層插塞同樣以由密到疏的方式排列佈局。 以上所述僅為本發明之雛實施例，凡依本發明申請專利範 13 1249226 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖緣示的是本發明第-較佳實施例在積體電路中使用Γχ 結構」（從第(η+ι)層金屬層開始)以及「曼哈頓」佈局(從第i層金 屬到第⑻層金屬)的部分金屬喊線佈局之放大上視示意圖。 第2圖繪示的是本發明第二較佳實施例在積體電路中使用「χ 結構」（從第㈣層金屬層開始)的部分金屬内連線佈局之放大上 視示意圖。 「X結構」的部分金屬 第3圖繪示的是在積體電路中典型使用 内連線佈局之放大上視示意圖。 【主要元件符號說明】 10 内連線結構 100、200 内連線佈局 12 下層金屬導線層 14 上層金屬導線層 24a〜24e 金屬介層插塞 224a〜224e 金屬介層插塞 16 等電位位置 124a〜124e金屬介層插塞BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor integrated circuit, and more particularly to a technique for improving the performance of an integrated circuit in a diagonal layout interconnect structure. [Prior Art] As is known to those skilled in the art, micro-transistor electronic components in a wafer are typically constructed by interconnecting a plurality of interconnected or right-angled layout logic structures. This kind of interconnection method has been widely referred to by the industry. The "Manhattan" layout is taken from the meaning of a square street in the city. Between the different layers, the wire is connected to the metal component, or the via, to form a path for the electronic signal to pass. • Over the years, the Coatings 4 industry has overcome many technical hurdles, coupled with continually improving process processes, such as 〇.18 micron process, (four) micron process, to 9 〇 nano generation or smaller, to achieve a smaller wafer size. The purpose of theization also makes the interconnect path in the wafer more inspectable. In order to make the operation speed even higher, (9) manufacturers use many methods, such as the cutting process to replace the traditional _ metal, the use of the stone rim (SOI) substrate clothing for the semiconductor tree, the lion strain theory e-) technology and low Dielectric constant tree _. _, using these advanced technologies, 1249226 still maintains the traditional grid winding logic in the interconnect layout, without the nearest straight or diagonal layout between the two components. In the traditional "Manhattan" layout logic, each metal wire layer has its preferred fixed wiring layout direction, and each layer of wire can be drawn along its opposite direction. For example, if the first layer of wire is preferred When the wiring direction is horizontal, the wiring direction of the second layer of wires thereon is in the vertical direction, and so on. Although the wiring direction has a diagonal layout in the printed circuit board process in another field, it has not been applied in the field of wafer design. This is due to the fact that the circuit design of the wafer is more complex and detailed than the circuit board design, and that there are more integrated components per single wafer, which needs to be considered together. In 2001, several semiconductor manufacturers and equipment vendors formed a semiconductor supply chain association: the X initiative, decided to overcome the traditional layout restrictions on the interconnect, allowing the chip designer to be outside the horizontal or vertical direction, There is more selectivity in the diagonal direction, and this concept is called "XArchitecture", and the wafer with "X structure" as the interconnect layout is also called "X-chip". Compared to conventional wafers using the "Manhattan" layout logic, the same wafers with "X-structure" clearly require shorter wire lengths and fewer via plugs, which is also more cost effective. However, despite these advantages, there are still some shortcomings in this advanced "X-structure" interconnect layout logic that need to be overcome and improved to further improve the performance and operational reliability of the wafer. 1249226 SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide an improved interconnect structure or interconnect layout that improves wafer operational efficiency and reliability. In order to achieve the foregoing object, a first preferred embodiment of the present invention provides an interconnect layout including a metal wire layer (Metal_n) extending below the vertical direction; and an oblique direction at an angle of 45 degrees in the horizontal direction. An extended upper metal wire layer (Metal-n+l); and first and second metal interposer plugs having mutually different cross-sectional areas, disposed between the lower metal wire layer and the upper metal wire layer, Electrically connecting the upper and lower metal wire layers, wherein a cross-sectional area of the first metal via plug is larger than a cross-sectional area of the second metal via plug, thereby compensating through the lower metal wire layer or the upper metal wire Uneven current blocking of the layer. A second preferred embodiment of the present invention discloses an interconnect layout structure including a metal wire layer (Metal_n) extending in a direction perpendicular to the Y-axis and obliquely extending at an angle of 45 degrees in the horizontal direction of the X-axis. An upper metal wire layer (Metal_n+1); and a plurality of metal interlayer plugs having approximately the same cross-sectional area, disposed between the lower metal wire layer and the upper metal wire layer for electrically connecting the upper and lower metal layers The wire layer, the plurality of metal interlayer plugs are arranged in a single column configuration from the left edge to the right edge of the lower metal wire layer in a dense to sparse manner. In order to enable the reviewing committee to learn more about the features and technical aspects of the present invention, please refer to Figure 3, which shows that the partial metal interconnect layout of X is typically used in integrated circuits. The upper view is enlarged. As shown in FIG. 3, the interconnect structure 1 〇 includes the underlying metal wire layer 12 (which is illustrated in FIG. 3, hereinafter, wherein η represents the underlying metal wire layer 12). In the fourth circuit (9), the lower metal wire layer 12 extends along the vertical direction or the γ axis direction of the fiscal reference coordinate. The inner wire structure 1G further includes a 45 degree angle along the horizontal direction. Or the upper metal wire layer K extending obliquely 45 degrees from the X axis of the coordinate axis in the figure, which is represented by "Metal_n+1," in the third object, and a plurality of metal intervening layers having approximately the same cross-sectional area. The plugs 24a to 2 are known to be disposed between the lower metal wire layer 12 and the upper metal wire layer W for electrically connecting the upper and lower metal wire layers. The metal via plugs 24a to 24e are rectangular in cross section in this example, have a side length d, and the spacing between two adjacent metal via plugs is also substantially equal (conventional layout rule). For convenience of explanation, the inter-metal dielectric layer is not shown in the figure. In operation, the upper metal wire layer 14 may be connected to an equipotential, such that current can be electronically tuned via the underlying metal wire layer 12, the metal via plugs 24a-24e, and the conductive traces formed by the upper metal wire layer 14. Pass and vice versa. However, one of the problems with the above-mentioned inner wiring structure is that when the current passes through the upper layer of gold 1249226, it is a non-uniform current blocking phenomenon, which may cause reliability problems in the operation of the element. In order to explain this uneven current blocking phenomenon, five different paths are illustrated in Fig. 3, which are path A, path B, path C, path D, and path E, respectively. The five paths are respectively for the metal via plugs 24a-24e of the lower metal wire layer 12 and the upper metal wire layer 14, wherein the distance between the equipotential position 16 and the metal via plug 24a is It is the longest, so it has the largest path resistance compared to other paths. In theory, the five paths are compared with each other. Path A is the largest, followed by path B, followed by path ◦, then path D, and minimum is path E. It can be seen that the upper metal wire layer exhibits a different resistance gradient in the width direction w on the operation day, which causes the current to flow through the path with the least resistance, that is, the path E in this example. , causing problems such as nickname delay, performance impairment, and reliability. The main object of the present invention is to improve the aforementioned uneven current by proposing a new layout rule or method, and a new structure, which is applied in the integrated circuit manufacturing technology that adopts the "X structure" wiring layout logic. Blocking phenomenon. In general, the aforementioned uneven electric/plug phenomenon occurs in the layer-diagonal diagonal alignment, _metal wire layer (usually the 4th or 5th layer metal in the 8 or 9-layer interconnect structure in 1C) And the metal layer of the "Manhattan" layout logic under the metal wire layer of the diagonal diagonal wiring of the first layer (usually the 3rd or 4th metal in the 8 or 9 layer interconnection structure in 1C) , but not limited to this). 1249226 Next, please refer to FIG. 1, which illustrates the use of "X structure" (starting from the (n+1)th metal layer) and "Manhattan" layout in the integrated circuit of the first preferred embodiment of the present invention. An enlarged schematic top view of a portion of the metal interconnect layout 100 (from a first layer of metal to a (8)th layer of metal, such as n=3). To simplify the description, the inter-metal dielectric layer in the figure is not labeled 7F. As shown in Fig. 1, the interconnect structure 1〇〇 includes a metal wire layer Π (indicated by ''Metal-η) extending along the vertical direction, the direction or the γ-axis direction of the reference coordinates in the figure, along The upper-order metal wire layer 14 (indicated by "Metal_n+1") extending obliquely in the horizontal direction or the 45-degree angular direction of the reference coordinate X-axis in the figure, and a plurality of metal intercalations having unequal cross-sectional areas Seru 124a~124e is disposed between the lower metal wire layer 12 and the upper metal wire layer 14 for electrically connecting the upper and lower metal wire layers. In this embodiment, the metal interlayer plugs / 124a~124e are The left edge to the right edge of the lower metal wire layer 12 are arranged in a single column group state. In other embodiments, the metal via plugs 124a to 124e may also be rotated by 45 degrees, but are not limited thereto. In this embodiment The metal via plugs 124a-124e have a rectangular cross-section on the layout. The metal via plugs 124a-124e are re-changed compared to the equal-sized metal via plugs 24a-24e in FIG. Dimensions to compensate for the aforementioned uneven current blocking phenomenon. As mentioned above, the path resistance is the path A, the second is the path B, then the path C, then the path D, the minimum is the path e, and the upper metal 'wire layer 14 is in its width direction during operation. On W, a different resistance gradient is exhibited, causing a current to flow through the path with the smallest resistance. To compensate for this difference in resistance gradient, the present invention compares the size of the metal via plug 124a to the dielectric layer of the metal 11 1249226. Subtract the other metal interlayer plug on the right side to adjust the size of the metal via plug to the next largest size, and then reduce the size of the metal via layer by ~1. The i-th riding, the size of the metal-based reed plug-in, is represented by (d), and its size is in the order of ^^gt;d4>d5. Since the metal interlayer plug 124a has the largest size, it is operated at the time of 3 . More current will pass through the metal, and the resistance gradient of the layer 14 will be compensated. 'Please refer to FIG. 2, which shows the second preferred embodiment of the present invention in the integrated body. "X structure" is used in circuit repair (from the (n+l) layer metal Part of the metal interconnects at the beginning of the layer) is not intended to be enlarged. The inter-metal dielectric layer in the figure is not shown. As shown in Fig. 2, the interconnect structure also includes a layer of metal wire 12 (ie, Metal), along the vertical direction or in the γ-axis direction of the reference coordinate in the figure. The upper metal wire layer 14 (indicated by Metal-n+1,) which is obliquely extending at an angle of 45 degrees in the horizontal direction or in the direction of the 45-degree angle of the reference coordinate axis, and the plurality of sectional areas are approximately equal in size The metal via plugs 124a-124e are disposed between the lower metal-clad wire layer 12 and the upper metal wire layer 14 for electrically connecting the upper and lower metal wire layers. The metal via plugs 124a to 124e are arranged in a single column configuration from the left edge to the right edge of the lower metal wiring layer 12. - r In this embodiment, the metal via plugs 124a to 124e are still rectangular in shape in the layout view, but are not limited thereto. Compared with the metal via plugs 24a to 24e of the same size in Fig. 3, although the metal via plugs are of the same size, 12 1249226 is reworked to compensate for the electric plug. Wherein, the distance between the metal intercalation plug and the metal intercalation plug is indicated by the symbol S1. The distance between the metal intercalation plug and the metal intercalation plug is indicated by the symbol S2. The distance between the layer plug and the metal via plug (10) is indicated by the symbol S3 and the distance between the metal via plug side and the metal via plug is indicated by the symbol & The path resistance is the largest path a, followed by the road grip B 're-U Chi C, then the path D, the minimum path E, the upper metal wire layer Μ will be in the width direction of the stomach during operation, the performance is different The resistance gradient 'causes the current to be selected to flow through the path of the least resistance. To compensate for this resistance gradient difference, the metal interlayer plug 1; 2 is adjusted with the distance S1 between the metal interlayer plug 1 and the metal interlayer plug 1 To a minimum, then correct the metal via plug 124b and the metal in sequence; the distance between the germanium plug 12, the distance between the metal via plug and the metal via plug, and the metal The distance S4 between the via plug (10) and the metal via plug 124e. As a result, as shown in Fig. 2, Si < s2 < s ^ S4, so that the metal interlayer plugs in the same column are in a dense to sparse manner in the arrangement, so that more current is flowed during operation. The difference in resistance gradient of the upper metal wire layer 14 can be compensated by the path A or B. = other implementations of the invention, there may also be a second thorn metal via plug, which is arranged in parallel with the previous column of the previous embodiment, and may be the same as the via plug of the previous column. The way the layout is arranged. The above is only the embodiment of the present invention, and all the equivalent changes and modifications made by the patent application 13 1249226 are covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a first embodiment of the present invention using a Γχ structure in an integrated circuit (starting from a (n+ι) metal layer) and a "manhattan" layout (from A schematic top view of a partial metal shunt line layout of the i-th metal to the (8)-layer metal). Fig. 2 is a schematic enlarged plan view showing a partial metal interconnection layout using a "χ structure" (starting from the (fourth) metal layer) in the integrated circuit of the second preferred embodiment of the present invention. Part of the metal of the "X structure" Figure 3 shows an enlarged top view of the typical use of the interconnect layout in the integrated circuit. [Main component symbol description] 10 interconnect structure 100, 200 interconnect layout 12 lower metal wiring layer 14 upper metal wiring layer 24a to 24e metal via plug 224a to 224e metal via plug 16 equipotential position 124a~ 124e metal interlayer plug