WO2015097979A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2015097979A1
WO2015097979A1 PCT/JP2014/005805 JP2014005805W WO2015097979A1 WO 2015097979 A1 WO2015097979 A1 WO 2015097979A1 JP 2014005805 W JP2014005805 W JP 2014005805W WO 2015097979 A1 WO2015097979 A1 WO 2015097979A1
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WO
WIPO (PCT)
Prior art keywords
wiring
semiconductor device
plating layer
opening
layer
Prior art date
Application number
PCT/JP2014/005805
Other languages
French (fr)
Japanese (ja)
Inventor
平野　博茂
道成 手谷
浜田　政一
垂水　喜明
Original Assignee
パナソニックＩｐマネジメント株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to JP2015554515A priority Critical patent/JP6303137B2/en
Publication of WO2015097979A1 publication Critical patent/WO2015097979A1/en
Priority to US15/160,033 priority patent/US9673139B2/en

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611—Smooth layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
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    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
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    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 describes a method for forming a wiring on an insulating substrate by a semi-additive method. Specifically, first, a copper seed layer is formed on a substrate made of an insulating resin. Thereafter, a resist pattern having an opening for pattern formation is formed, and electroplating is performed to form a thick wiring in the opening of the resist pattern. After the wiring is formed, the resist pattern is removed, and then the seed layer remaining in the portion other than the wiring is removed.
  • Patent Document 2 discloses a wiring that is a connection terminal formed on a semiconductor chip mounting substrate and the surface of the connection terminal formed on the surface of the substrate is covered with an electroless plating film.
  • Patent Document 3 describes a structure in which the side surface of a copper wiring is covered with nickel or gold by electroplating.
  • JP 2006-24902 A JP 2009-1117637 A JP 2013-93360 A
  • connection terminals including the side surfaces can be covered with an electroless plating film.
  • electroless plating is difficult to control plating compared to electroplating, and has problems such as plating on insulating films other than wiring. In general, the plating rate is slow and there is a problem in terms of productivity.
  • Patent Document 3 it is necessary to connect a current supply source and a seed layer in order to perform electroplating. For this reason, unnecessary wiring and seed layers are removed after the film is formed. Therefore, a structure in which a part of the wiring is always exposed from the film is obtained. As a result, the wiring may be short-circuited due to deterioration or migration due to oxidation in the exposed portion of copper.
  • a first insulating film formed over a semiconductor substrate, a first wiring formed over the first insulating film, and the first wiring are covered.
  • the second insulating film has a first opening and a second opening that expose the upper surface of the first wiring.
  • the second wiring includes a first opening and a seed layer provided around the first opening, and a first plating layer provided on the seed layer and covering all sides of the seed layer. .
  • the seed layer is not provided in the second opening and the periphery thereof.
  • the seed layer may be made of a first metal
  • the first plating layer may be made of a second metal having a hardness higher than that of the first metal
  • the first metal may be copper and the second metal may be nickel.
  • One aspect of the semiconductor device further includes a second plating layer provided between the seed layer and the first plating layer, and the first plating layer covers the upper surface and all side surfaces of the second plating layer. It can be set as the structure to do.
  • the second plating layer can be a base layer in the second wiring.
  • the semiconductor device there are a plurality of first openings, and the second plating layer is provided corresponding to each of the plurality of first openings, and has a plurality of portions separated from each other.
  • the first plating layer can be configured to integrally cover a plurality of portions of the second plating layer.
  • the plurality of portions may be arranged in a line or may be arranged in a matrix.
  • the first plating layer can be a base layer in the second wiring.
  • a plurality of first openings can be provided.
  • the first opening may have a planar rectangular shape.
  • One embodiment of the semiconductor device further includes a third wiring provided adjacent to the first wiring on the first insulating film, and the second wiring includes the first wiring and the third wiring. It is possible to adopt a configuration in which the third wiring is not connected to the third wiring.
  • the second wiring may have a third plating layer provided on the first plating layer.
  • the first wiring may have a recess in a portion exposed from the second opening.
  • the second wiring can be a bump pad.
  • a barrier layer may be provided between the seed layer and the first wiring in the first opening.
  • the seed layer and the barrier layer may have the same side end position.
  • a semiconductor device including wiring having sufficient oxidation resistance or migration resistance can be realized.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • FIG. 1B is a cross-sectional view taken along line 1B-1B of the semiconductor device shown in FIG. 1A. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • FIG. 8B is a cross-sectional view of the semiconductor device shown in FIG. 8A taken along line 8B-8B. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.
  • FIG. 12B is a cross-sectional view taken along line 12B-12B of the semiconductor device shown in FIG. 12A.
  • FIG. 12B is a cross-sectional view of the semiconductor device shown in FIG. 12A taken along line 12C-12C.
  • FIG. 13B is a cross-sectional view taken along line 13B-13B of the semiconductor device shown in FIG. 13A.
  • FIG. 13C is a cross-sectional view of the semiconductor device shown in FIG. 13A taken along line 13C-13C. It is a top view which shows the semiconductor device which concerns on 3rd Embodiment.
  • a first insulating film 121 is provided on a base layer 110 provided on a semiconductor substrate 101.
  • a first wiring 131 is provided on the first insulating film 121.
  • a second insulating film 122 is provided on the first insulating film 121 so as to cover the first wiring 131.
  • the second insulating film 122 has a first opening 122 a and a second opening 122 b that expose the upper surface of the first wiring 131.
  • a second wiring 132 is provided on the second insulating film 122.
  • the second wiring 132 is provided in the first opening 122a and the periphery thereof, and is not provided in the second opening 122b and the periphery thereof.
  • the second wiring 132 is connected to the first wiring 131 in the first opening 122a, and is not connected to the first wiring 131 in the second opening 122b.
  • the second wiring 132 has a barrier layer 141, a seed layer 142 provided in contact with the barrier layer 141, and an electrolytic plating layer provided in contact with the seed layer 142.
  • the barrier layer 141 is exposed from the portion around the first opening 122 a on the upper surface of the second insulating film 122, the side surface of the first opening 122 a, and the first opening 122 a on the upper surface of the first wiring 131. It touches the part to be.
  • the electrolytic plating layer was provided on the first plating layer 145, the second plating layer 146 provided between the first plating layer 145 and the seed layer 142, and the first plating layer 145.
  • the second plating layer 146 is in contact with the seed layer 142.
  • the barrier layer 141, the seed layer 142, and the second plating layer 146 have substantially the same size. Accordingly, the positions of the side end portions of the barrier layer 141, the seed layer 142, and the second plating layer 146 are substantially the same.
  • the barrier layer 141, the seed layer 142, and the second plating layer 146 are collectively referred to as a lower region 148.
  • the side surface of the lower region 148 is substantially perpendicular to the main surface of the semiconductor substrate 101.
  • the first plating layer 145 is larger than the lower region 148 and extends outside the lower region 148. Accordingly, the first plating layer 145 covers the upper surface and side surfaces of the lower region 148, and the lower end portion is in contact with the upper surface of the second insulating film 122 outside the lower region 148. For this reason, the lower region 148 is blocked from the outside by the first wiring 131, the second insulating film 122, and the first plating layer 145.
  • the lower region 148 does not completely fill the first opening 122a, and there is a recess at a position corresponding to the first opening 122a on the upper surface of the lower region 148.
  • the first plating layer 145 is provided so as to fill the concave portion of the lower region 148.
  • the first plating layer 145 is sufficiently thick, and the upper surface of the first plating layer 145 is flat.
  • the upper surface of the third plating layer 147 provided on the first plating layer 145 is also flat.
  • the first plating layer 145 and the third plating layer 147 have substantially the same size in plan view, and the positions of the side end portions of the first plating layer 145 and the third plating layer 147 are substantially the same. Yes.
  • the barrier layer 141 is made of, for example, titanium. The thickness of the barrier layer 141 can be set to, for example, about 0.2 ⁇ m.
  • the seed layer 142 is made of, for example, copper. The thickness of the seed layer 142 can be set to, for example, about 0.2 ⁇ m.
  • the first plating layer 145 is made of nickel, for example. The thickness of the 1st plating layer 145 can be about 10 micrometers, for example.
  • the second plating layer 146 is made of, for example, copper. The thickness of the second plating layer 146 can be set to, for example, about 0.4 ⁇ m.
  • the third plating layer 147 is made of, for example, gold. The thickness of the third plating layer 147 can be set to, for example, about 0.3 ⁇ m.
  • the first plating layer 145 is a base layer having the largest mass among the metal layers constituting the second wiring 132.
  • the second wiring 132 is not provided around the second opening 122b. Accordingly, the lower region 148 including the barrier layer 141 and the seed layer 142, the first plating layer 145, the second plating layer 146, and the third plating layer 147 are provided in the second opening 122b and the periphery thereof. Not. Further, the barrier layer 141 is not in contact with a portion exposed from the second opening 122 b of the first wiring 131. A portion of the first wiring 131 exposed from the second opening 122 b is a recess 131 a that is recessed from the other portions of the first wiring 131.
  • a third wiring 133 and a fourth wiring 134 are provided on the first insulating film 121.
  • the third wiring 133 and the fourth wiring 134 are provided in parallel with the first wiring 131.
  • the second wiring 132 is formed over the first wiring 131, the third wiring 133, and the fourth wiring 134.
  • the second wiring 132 is not connected to the third wiring 133 and the fourth wiring 134, and is connected only to the first wiring 131.
  • the second insulating film 122 does not need to have an opening exposing the third wiring 133 and an opening exposing the fourth wiring 134.
  • the first wiring 131, the third wiring 133, and the fourth wiring 134 can be aluminum wiring, for example.
  • the third wiring 133 and the fourth wiring 134 are not necessarily provided.
  • a lower layer wiring 111 is provided on the base layer 110.
  • the lower layer wiring 111 can be an aluminum wiring, for example.
  • the first insulating film 121 is provided so as to cover the lower layer wiring 111.
  • the first wiring 131 is connected to the lower wiring 111 by a via 112 that penetrates the first insulating film 121.
  • the first insulating film 121 and the second insulating film 122 can be a silicon nitride (SiN) film, a tetraethoxysilane (TEOS) film, or the like.
  • the semiconductor substrate 101 may be provided with a semiconductor element such as a transistor.
  • the upper surface and the side surface of a portion made of a material such as copper, which is likely to be oxidized or migrated, of the wiring are covered with a film made of a stable metal such as nickel. For this reason, reliability can be improved particularly in a semiconductor device in which a protective film is not provided on wiring such as bump pads. Further, since the surface of the wiring is covered with a nickel material having a hardness higher than that of copper, the strength of the bump can be increased and the pressure bonding force at the time of connecting the bump can be increased. Further, the surface of the wiring can be further stabilized by coating gold on nickel. For this reason, connectivity can also be improved.
  • the semiconductor device according to the first embodiment can be formed as follows. First, as shown in FIG. 2A, a lower layer wiring 111 is formed on a base layer 110 provided on a semiconductor substrate 101. Subsequently, a first insulating film 121 is formed on the base layer 110. Subsequently, an opening for exposing the lower layer wiring 111 is provided in the first insulating film 121. Thereafter, a first wiring 131 and a via 112 that connects the first wiring 131 and the lower layer wiring 111 are formed on the first insulating film 121. Subsequently, a second insulating film 122 is formed on the first insulating film 121 so as to cover the first wiring 131.
  • the first opening 122 a and the second opening 122 b are formed in the second insulating film 122.
  • the first opening 122a is formed in a region where the second wiring 132 is provided, and the second opening 122b is formed in a region where the second wiring 132 is not provided.
  • the first opening 122a and the second opening 122b have such a size that the flatness of the upper surface of the second wiring 132 can be ensured.
  • the planar size of the first opening 122a and the second opening 122b can be about 5 ⁇ m square.
  • the first opening 122a and the second opening 122b are preferably chamfered at the corners.
  • the first opening 122a and the second opening 122b do not have to have a planar square shape. Further, the first opening 122a and the second opening 122b may be different in at least one of size and planar shape.
  • the first insulating film 121 and the second insulating film 122 can be SiN films, TEOS films, or the like.
  • the first insulating film 121 and the second insulating film 122 can be formed by a chemical vapor deposition (CVD) method or the like.
  • the thickness of the first insulating film 121 and the second insulating film 122 may be approximately 1 ⁇ m.
  • the lower layer wiring 111 and the first wiring 131 can be formed by forming an aluminum film by sputtering or the like, and then patterning the aluminum film by lithography and dry etching.
  • the via 112 can be formed simultaneously with the first wiring 131 by providing an opening for exposing the lower layer wiring 111 in the first insulating film 121.
  • a barrier layer 141 made of titanium and a seed layer 142 made of copper are formed on the entire surface of the second insulating film 122 including the insides of the first opening 122a and the second opening 122b.
  • the barrier layer 141 and the seed layer 142 can be formed by a sputtering method or the like.
  • the thicknesses of the barrier layer 141 and the seed layer 142 can be about 0.2 ⁇ m, respectively.
  • a resist pattern 171 is formed so as to surround a region where the second wiring 132 is formed.
  • the resist pattern 171 is formed so that the part that will eventually become the lower region 148 is exposed and the outer dimension matches the outer dimension of the first plating layer 145.
  • the thickness of the resist pattern 171 is not particularly limited, but can be about 1 ⁇ m.
  • copper electroplating is performed to form a copper plating layer to be the second plating layer 146 on the portion where the seed layer 142 is exposed.
  • the resist pattern 171 is removed, and the second plating layer 146 is etched until the thickness becomes about 0.4 ⁇ m.
  • a lower region 148 including the barrier layer 141, the seed layer 142, and the second plating layer 146 is formed in a portion not covered with the resist pattern 171.
  • the seed layer 142 and the barrier layer 141 are removed and the second insulating film 122 is exposed in a portion that is covered with the resist pattern 171 and where the second plating layer 146 is not formed. Accordingly, the lower region 148 formed around the first opening 122a and the lower region 148 formed around the second opening 122b are separated.
  • a resist pattern 172 having an opening that exposes a region for forming the second wiring 132 is formed.
  • the opening of the resist pattern 172 is larger than the lower region 148 formed around the first opening 122a so that the upper surface of the second insulating film 122 is exposed.
  • the first plating layer 145 can have a thickness of about 10 ⁇ m.
  • the third plating layer 147 can have a thickness of about 0.3 ⁇ m.
  • the first plating layer 145 and the third plating layer 147 When forming the first plating layer 145 and the third plating layer 147, current is supplied from the lower region 148 formed around the second opening 122b.
  • the lower region 148 formed around the first opening 122a and the lower region 148 formed around the second opening 122b are separated from each other, but are electrically connected via the first wiring 131. It is connected to the. Therefore, the first plating layer 145 can be formed so as to cover the upper surface and side surfaces of the lower region 148 formed around the first opening 122 a and the exposed portion of the second insulating film 122.
  • the second plating layer 146, the seed layer 142, The barrier layer 141 is removed. At this time, a portion exposed from the second opening 122b in the first wiring 131 may also be etched to form a recess. Even if the recess is formed, there is no problem in the operation of the semiconductor device.
  • a semiconductor device in which oxidation or migration of a portion made of copper is greatly reduced can be formed without greatly changing the conventional semi-additive method. Therefore, it is possible to realize a highly reliable semiconductor device in which the occurrence of wiring shorts or the like is significantly reduced. In addition, there is an advantage that the formation position of the second wiring can be accurately set by the position of the resist pattern.
  • FIG. 4 shows a planar configuration of a semiconductor device according to a first modification of the first embodiment.
  • the semiconductor device of this modification is different from the semiconductor device of the first embodiment in that the second wiring 132 is formed on the wide first wiring 131.
  • the first opening 122 a may be rectangular according to the width of the first wiring 131.
  • the ratio of the portion of the lower region 148 that is in contact with the first wiring 131 is increased, and the amount of current supplied during electrolytic plating can be increased.
  • the first plating layer 145 and the third plating layer 147 can be stably formed.
  • the planar size of the first opening 122a is not particularly limited, but can be about 20% of the planar size of the lower region 148.
  • the width of the first opening 122 a is preferably about 5 ⁇ m from the viewpoint of ensuring the flatness of the upper surface of the second wiring 132.
  • the corner of the first opening 122a is preferably chamfered from the viewpoint of embedding.
  • FIG. 5 shows a planar configuration of a semiconductor device according to a second modification of the first embodiment.
  • a plurality of first openings 122 a may be provided instead of providing a rectangular first opening 122 a that matches the width of the first wiring 131.
  • the ratio of the portion in contact with the first wiring 131 in the lower region 148 can be increased, and the amount of current supplied during electrolytic plating can be increased.
  • the planar size of the first opening 122a can be about 5 ⁇ m square from the viewpoint of ensuring the flatness of the upper surface of the second wiring 132.
  • the corner of the first opening 122a is preferably chamfered from the viewpoint of embedding.
  • the number of the first openings 122a is not limited to two and may be three or more. When a plurality of first openings 122a are provided, all of them may not have the same size and shape.
  • the second plating layer 146 is provided between the seed layer 142 and the first plating layer 145.
  • the second plating layer 146 may not be provided. By not providing the second plating layer 146, the number of manufacturing steps of the semiconductor device can be reduced.
  • the semiconductor device of this modification can be formed as follows. First, as shown in FIG. 7A, a barrier layer 141 and a seed layer 142 are formed on the second insulating film 122 in the same manner as in the first embodiment. Thereafter, a resist pattern 173 provided with an opening so as to surround a portion to be the lower region 148 of the second wiring 132 is formed.
  • etching is performed using the resist pattern 173 as a mask, and the seed layer 142 and the barrier layer 141 are selectively removed to expose the second insulating film 122.
  • a lower region 148 composed of the barrier layer 141 and the seed layer 142 is formed.
  • the lower region 148 formed around the first opening 122a and the lower region 148 formed around the second opening 122b are separated.
  • a resist pattern 172 having an opening that exposes a region where the second wiring 132 is to be formed is formed.
  • the opening of the resist pattern 172 is larger than the lower region 148 formed around the first opening 122a so that the upper surface of the second insulating film 122 is exposed.
  • nickel electroplating is performed to form a first plating layer 145 in the opening of the resist pattern 172.
  • the resist pattern 172 is removed, and unnecessary portions of the seed layer 142 and the barrier layer 141 are removed.
  • the second plating layer 146 since the second plating layer 146 is not formed, the number of steps can be reduced as compared with the first embodiment.
  • the semiconductor device according to the first modification and the second modification of the first embodiment can be configured as in this modification.
  • FIGS. 8A and 8B show a semiconductor device according to the second embodiment.
  • the semiconductor device of the present embodiment is a first implementation in that a second plating layer 146A that is a thick copper plating layer is provided, and a first plating layer 145A that is thinner than the second plating layer 146A is provided.
  • a second plating layer 146A that is a thick copper plating layer
  • a first plating layer 145A that is thinner than the second plating layer 146A is provided.
  • the thickness of the second plating layer 146A on the second insulating film 122 excluding the first opening 122a can be, for example, about 10 ⁇ m.
  • the second plating layer 146 ⁇ / b> A is a base layer having the largest mass among the metal layers constituting the second wiring 132.
  • the second plating layer 146A is provided so as to fill the first opening 122a.
  • the planar size of the second plating layer 146A is substantially the same as that of the barrier layer 141 and the seed layer 142 as in the first embodiment.
  • the side surface of the lower region 148A composed of the barrier layer 141, the seed layer 142, and the second plating layer 146A is a substantially vertical surface.
  • the thickness of the first plating layer 145A can be about 0.4 ⁇ m.
  • the first plating layer 145A completely covers the upper surface and the side surface of the lower region 148A, as in the first embodiment.
  • the planar size of the first plating layer 145A is larger than the lower region 148A.
  • the first plating layer 145A is in contact with the second insulating film 122 outside the lower region 148A. Therefore, the lower region 148A is blocked from the outside by the first wiring 131, the second insulating film 122, and the first plating layer 145A.
  • the thickness of the third plating layer 147A can be about 0.3 ⁇ m.
  • the third plating layer 147A is provided on the first plating layer 145A including the upper surface and the side surface.
  • the planar size of the third plating layer 147A is larger than that of the first plating layer 145A.
  • the third plating layer 147A is in contact with the second insulating film 122 outside the first plating layer 145A.
  • the copper portion of the second wiring 132 is covered with a film made of a stable metal such as nickel, as in the semiconductor device of the first embodiment.
  • a film made of a stable metal such as nickel
  • reliability can be improved particularly in a semiconductor device in which a protective film is not provided on wiring such as bump pads.
  • by increasing the thickness of the copper plating layer it is possible to relieve the stress on the underlying wiring and the element at the time of bump connection while ensuring the hardness and strength as a bump pad. Reduction of electrical resistance can also be expected.
  • the amount of nickel used can be reduced compared to the first embodiment.
  • the semiconductor device of this embodiment can be formed as follows. First, similarly to the first embodiment, the portion up to the second plating layer 146 shown in FIG. 9A is formed.
  • a resist pattern 175 having an opening in a region where the second wiring 132 is to be formed is formed with the resist pattern 171 remaining.
  • the resist pattern 171 and the resist pattern 175 are removed, and etching is performed until the thickness of the second plating layer 146 reaches about 0.4 ⁇ m in the portion covered with the resist pattern 175. To do.
  • a lower region 148A having a thick second plating layer 146A is formed in a portion corresponding to the opening of the resist pattern 175.
  • a lower region 148 having a thin second plating layer 146 is formed in a portion that is not covered with the resist pattern 171.
  • the seed layer 142 and the barrier layer 141 are removed from the portion covered with the resist pattern 171 and the second insulating film 122 is exposed. Therefore, the lower region 148A and the lower region 148 are separated.
  • a resist pattern 172 having an opening that exposes a region for forming the second wiring 132 is formed.
  • the opening of the resist pattern 172 is larger than the lower region 148A formed around the first opening 122a so that the upper surface of the second insulating film 122 is exposed.
  • nickel electroplating is performed to form a first plating layer 145A that covers the upper and side surfaces of the lower region 148A.
  • gold electrolytic plating is performed to form a third plating layer 147A that covers the first plating layer 145A.
  • a current is supplied from the lower region 148 formed around the second opening 122b, as in the first embodiment.
  • the resist pattern 172 is removed and unnecessary portions of the seed layer 142 and the barrier layer 141 are removed.
  • the resist pattern 171 and the resist pattern 175 do not need to be aligned with high accuracy.
  • the resist pattern 172 may be thin as long as it can cover the second plating layer 146 formed outside the region where the second wiring 132 is formed. In addition, highly accurate alignment is not necessary.
  • the resist pattern 175 is formed without removing the resist pattern 171 is shown.
  • the resist pattern 171 may be removed.
  • the process up to forming the second plating layer 146 is performed.
  • the resist pattern 171 is removed, and a resist pattern 176 having an opening in a region where the second wiring 132 is formed is formed.
  • copper is electroplated, and copper is stacked in the openings of the resist pattern 176 to form a second plating layer 146A.
  • the resist pattern 176 is removed, and the seed layer 142 and the barrier layer 141 are selectively removed in the same manner as in the second embodiment, and the first plating layer 145A and the third plating layer 147A are electroplated. Form. Subsequently, unnecessary portions of the seed layer 142 and the barrier layer 141 are removed.
  • the second plating layer 146B has three portions 246.
  • the widths of the barrier layer 141 and the seed layer 142 substantially coincide with the width of the portion 246.
  • the width of the portion 246 is shorter than the widths of the barrier layer 141 and the seed layer 142 in the longitudinal direction of the second wiring 132.
  • the portions 246 are provided in a row at intervals. The upper surface and the side surface of each portion 246 are covered with the first plating layer 145B. Accordingly, the portion 246 is adjacent via the first plating layer 145B.
  • the first plating layer 145B integrally covers the plurality of portions 246 of the second plating layer 146B. Therefore, the first plating layer 145B made of nickel or the like has a lattice shape in plan view. Accordingly, the strength of the second wiring 132 can be further improved.
  • the number of divisions of the second plating layer 146B is not limited to three. There may be two or four or more. Moreover, although the example which divided
  • the semiconductor device of this modification can be formed in the same manner as in the second embodiment by changing the shape of the resist pattern 175.
  • first openings 122 a are provided in the short direction of the second wiring 132. For this reason, two portions 246 adjacent to each other in the short direction of the second wiring 132 are connected to the first wiring 131.
  • the first opening 122a may be one.
  • the number of divisions of the second plating layer 146B is not limited to 2 ⁇ 3.
  • a matrix in which both the vertical direction and the horizontal direction are divided into an arbitrary number can be used.
  • the number of first openings 122a is not limited to two.
  • the first opening 122a may be provided in accordance with the number of divisions of the second plating layer 146B.
  • the first opening 122a as in the first modification or the second modification of the first embodiment may be formed depending on the shape of the first wiring 131. Can be provided.
  • one portion 246 may correspond to the plurality of first openings 122a.
  • FIG. 14 shows a semiconductor device according to the third embodiment.
  • the device chip 401 has a bump pad group 402 for input and control signals arranged on the left side and an output bump pad group 403 arranged on the right side. Since the individual bump pads of the left bump pad group 402 are relatively large in size, like the second modification of the second embodiment, the copper plating layer serving as the base of the second wiring is arranged in a matrix.
  • the bump pad can be divided into a plurality of portions, and the nickel plating layer can have a lattice shape in plan view to improve the strength.
  • the individual bump pads of the bump pad group 403 on the right side are smaller than the individual bump pads of the bump pad group 402 and the intervals between them are also narrow. For this reason, the resist pattern for forming the nickel plating layer and the gold plating layer is formed by forming an opening including a plurality of copper plating layers without providing an opening for each copper plating layer. Plating can also be performed.
  • the strength of the bump pad (second wiring) can be enhanced, and a balance between the bump pad groups 402 and 403 having different sizes and arrangements can be obtained.
  • the semiconductor device of the present disclosure includes wiring having sufficient oxidation resistance or migration resistance, and is useful as a semiconductor device having a bump pad or the like. In particular, it is useful as a semiconductor device having a thick film and a wiring pattern with thin lines / spaces.

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Abstract

To provide a semiconductor device that is equipped with wiring having sufficient oxidation resistance or migration resistance. This semiconductor device is equipped with: a first insulating film (121) that is formed on a semiconductor substrate (101); first wiring (131) formed on the first insulating film (121); a second insulating film (122) that is provided on the first insulating film (121) so as to cover the first wiring (131); and second wiring (132) that is formed on the second insulating film (122). The second insulating film (122) has a first opening (122a) and a second opening (122b), from which an upper surface of the first wiring (131) is exposed. The second wiring (132) has a seed layer (142), and a first plating layer (145) that covers the whole side surfaces of the seed layer (142), and the seed layer (142) is not formed around the second opening (122b).

Description

半導体装置Semiconductor device
　本開示は、半導体装置に関する。 The present disclosure relates to a semiconductor device.
　半導体基板及び半導体装置等に厚膜の配線を形成する方法として、セミアディティブ（semi additive）法がある。例えば、特許文献１には、セミアディティブ法による、絶縁性基板上への配線形成方法が記載されている。具体的には、まず、絶縁性樹脂からなる基板上に銅のシード層を形成する。その後、パターン形成用の開口部を有するレジストパターンを形成し、電界めっきを行いレジストパターンの開口部内に厚膜の配線を形成する。配線を形成した後にレジストパターンを除去し、その後、配線以外の部分に残存するシード層を除去する。 There is a semi-additive method as a method of forming a thick film wiring on a semiconductor substrate, a semiconductor device or the like. For example, Patent Document 1 describes a method for forming a wiring on an insulating substrate by a semi-additive method. Specifically, first, a copper seed layer is formed on a substrate made of an insulating resin. Thereafter, a resist pattern having an opening for pattern formation is formed, and electroplating is performed to form a thick wiring in the opening of the resist pattern. After the wiring is formed, the resist pattern is removed, and then the seed layer remaining in the portion other than the wiring is removed.
　また、特許文献２には、半導体チップ搭載用基板に形成された接続端子であって、基板表面に形成された接続端子の表面が無電界めっき皮膜で被覆される配線が開示されている。 Further, Patent Document 2 discloses a wiring that is a connection terminal formed on a semiconductor chip mounting substrate and the surface of the connection terminal formed on the surface of the substrate is covered with an electroless plating film.
　また、特許文献３には、電界めっきにより銅配線の側面をニッケルや金により被覆した構造が記載されている。 Patent Document 3 describes a structure in which the side surface of a copper wiring is covered with nickel or gold by electroplating.
特開２００６－２４９０２号公報JP 2006-24902 A 特開２００９－１１７６３７号公報JP 2009-1117637 A 特開２０１３－９３３６０号公報JP 2013-93360 A
　しかしながら、特許文献１の構成では、配線の側面から銅のシード層が露出した状態となる。このため、例えば銅の酸化による劣化又は銅のマイグレーションにより配線ショートが発生するおそれがある。 However, in the configuration of Patent Document 1, the copper seed layer is exposed from the side surface of the wiring. For this reason, there is a possibility that a wiring short circuit may occur due to deterioration due to copper oxidation or copper migration.
　特許文献２の構成では、接続端子を側面も含めてすべて無電解めっき皮膜により被覆できる。しかし、無電界めっきは電界めっきに比べてめっき制御性が難しく、配線以外の絶縁膜にもめっきされるなどの課題がある。また、一般にめっき速度が遅く生産性の面からも課題がある。 In the configuration of Patent Document 2, all the connection terminals including the side surfaces can be covered with an electroless plating film. However, electroless plating is difficult to control plating compared to electroplating, and has problems such as plating on insulating films other than wiring. In general, the plating rate is slow and there is a problem in terms of productivity.
　特許文献３の構成では、電界めっきを行うために、電流供給源とシード層とを接続する必要がある。このため、皮膜を形成した後に、不必要な配線及びシード層を除去することになる。従って、配線の一部が必ず皮膜から露出した構造となる。その結果、銅の露出部における酸化による劣化又はマイグレーションにより、配線がショートするおそれがある。 In the configuration of Patent Document 3, it is necessary to connect a current supply source and a seed layer in order to perform electroplating. For this reason, unnecessary wiring and seed layers are removed after the film is formed. Therefore, a structure in which a part of the wiring is always exposed from the film is obtained. As a result, the wiring may be short-circuited due to deterioration or migration due to oxidation in the exposed portion of copper.
　本開示は、十分な酸化耐性又はマイグレーション耐性を有する配線を備えた半導体装置を実現できるようにすることを目的とする。 It is an object of the present disclosure to realize a semiconductor device including a wiring having sufficient oxidation resistance or migration resistance.
　本開示の半導体装置の一態様は、半導体基板の上に形成された第１の絶縁膜と、第１の絶縁膜の上に形成された第１の配線と、第１の配線を覆うように、第１の絶縁膜の上に設けられた第２の絶縁膜と、第２の絶縁膜の上に形成された第２の配線とを備えている。そして第２の絶縁膜は、第１の配線の上面を露出する第１の開口部及び第２の開口部を有している。そして第２の配線は、第１の開口部及びその周囲に設けられたシード層と、シード層の上に設けられ、シード層の全側面を被覆する第１のめっき層とを有している。そしてシード層は、第２の開口部及びその周囲には設けられていない。 In one embodiment of the semiconductor device of the present disclosure, a first insulating film formed over a semiconductor substrate, a first wiring formed over the first insulating film, and the first wiring are covered. And a second insulating film provided on the first insulating film, and a second wiring formed on the second insulating film. The second insulating film has a first opening and a second opening that expose the upper surface of the first wiring. The second wiring includes a first opening and a seed layer provided around the first opening, and a first plating layer provided on the seed layer and covering all sides of the seed layer. . The seed layer is not provided in the second opening and the periphery thereof.
　半導体装置の一態様において、シード層は第１の金属からなり、第１のめっき層は、第１の金属よりも硬度が高い、第２の金属からなる構成とすることができる。 In one embodiment of the semiconductor device, the seed layer may be made of a first metal, and the first plating layer may be made of a second metal having a hardness higher than that of the first metal.
　この場合において、第１の金属は銅であり、第２の金属はニッケルである構成とすることができる。 In this case, the first metal may be copper and the second metal may be nickel.
　半導体装置の一態様は、シード層と第１のめっき層との間に設けられた第２のめっき層をさらに備え、第１のめっき層は、第２のめっき層の上面及び全側面を被覆する構成とすることができる。 One aspect of the semiconductor device further includes a second plating layer provided between the seed layer and the first plating layer, and the first plating layer covers the upper surface and all side surfaces of the second plating layer. It can be set as the structure to do.
　この場合において、第２のめっき層は、第２の配線におけるベース層とすることができる。 In this case, the second plating layer can be a base layer in the second wiring.
　半導体装置の一態様において、第１の開口部は、複数であり、第２のめっき層は、複数の第１の開口部のそれぞれに対応して設けられ、互いに分離された複数の部分を有し、第１のめっき層は、第２のめっき層の複数の部分を一体に被覆する構成とすることができる。 In one embodiment of the semiconductor device, there are a plurality of first openings, and the second plating layer is provided corresponding to each of the plurality of first openings, and has a plurality of portions separated from each other. In addition, the first plating layer can be configured to integrally cover a plurality of portions of the second plating layer.
　この場合において、複数の部分は、一列に配置されていてもよく、マトリックス状に配置されていてもよい。 In this case, the plurality of portions may be arranged in a line or may be arranged in a matrix.
　半導体装置の一態様において、第１のめっき層は、第２の配線におけるベース層とすることができる。 In one embodiment of the semiconductor device, the first plating layer can be a base layer in the second wiring.
　さらに、第１の開口部は、複数設けられている構成とすることができる。 Furthermore, a plurality of first openings can be provided.
　半導体装置の一態様において、第１の開口部は、平面長方形状であってもよい。 In one aspect of the semiconductor device, the first opening may have a planar rectangular shape.
　半導体装置の一態様は、第１の絶縁膜の上に、第１の配線と隣接して設けられた第３の配線をさらに備え、第２の配線は、第１の配線及び第３の配線の上に跨がって設けられており、第３の配線と接続されていない構成とすることができる。 One embodiment of the semiconductor device further includes a third wiring provided adjacent to the first wiring on the first insulating film, and the second wiring includes the first wiring and the third wiring. It is possible to adopt a configuration in which the third wiring is not connected to the third wiring.
　半導体装置の一態様において、第２の配線は、第１のめっき層の上に設けられた第３のめっき層を有していてもよい。 In one embodiment of the semiconductor device, the second wiring may have a third plating layer provided on the first plating layer.
　半導体装置の一態様において、第１の配線は、第２の開口部から露出する部分に凹部を有していてもよい。 In one embodiment of the semiconductor device, the first wiring may have a recess in a portion exposed from the second opening.
　半導体装置の一態様において、第２の配線はバンプパッドとすることができる。 In one embodiment of the semiconductor device, the second wiring can be a bump pad.
　半導体装置の一態様において、第１の開口部において、シード層と第１の配線との間にバリア層が設けられていてもよい。 In one embodiment of the semiconductor device, a barrier layer may be provided between the seed layer and the first wiring in the first opening.
　半導体装置の一態様において、シード層とバリア層とは側端部の位置が一致していてもよい。 In one embodiment of the semiconductor device, the seed layer and the barrier layer may have the same side end position.
　本開示の半導体装置によれば、十分な酸化耐性又はマイグレーション耐性を有する配線を備えた半導体装置を実現できる。 According to the semiconductor device of the present disclosure, a semiconductor device including wiring having sufficient oxidation resistance or migration resistance can be realized.
第１の実施形態に係る半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment. 図１Ａに示す半導体装置の１Ｂ－１Ｂ線における断面図である。FIG. 1B is a cross-sectional view taken along line 1B-1B of the semiconductor device shown in FIG. 1A. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態の第１変形例に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on the 1st modification of 1st Embodiment. 第１の実施形態の第２変形例に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on the 2nd modification of 1st Embodiment. 第１の実施形態の第３変形例に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on the 3rd modification of 1st Embodiment. 第１の実施形態の第３変形例に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of 1st Embodiment. 第１の実施形態の第３変形例に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of 1st Embodiment. 第１の実施形態の第３変形例に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of 1st Embodiment. 第２の実施形態に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a 2nd embodiment. 図８Ａに示す半導体装置の８Ｂ－８Ｂ線における断面図である。FIG. 8B is a cross-sectional view of the semiconductor device shown in FIG. 8A taken along line 8B-8B. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法の変形例を示す断面図である。It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法の変形例を示す断面図である。It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法の変形例を示す断面図である。It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態の第１変形例に係る半導体装置の平面図である。It is a top view of a semiconductor device concerning the 1st modification of a 2nd embodiment. 図１２Ａに示す半導体装置の１２Ｂ－１２Ｂ線における断面図である。FIG. 12B is a cross-sectional view taken along line 12B-12B of the semiconductor device shown in FIG. 12A. 図１２Ａに示す半導体装置の１２Ｃ－１２Ｃ線における断面図である。FIG. 12B is a cross-sectional view of the semiconductor device shown in FIG. 12A taken along line 12C-12C. 第２の実施形態の第２変形例に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning the 2nd modification of a 2nd embodiment. 図１３Ａに示す半導体装置の１３Ｂ－１３Ｂ線における断面図である。FIG. 13B is a cross-sectional view taken along line 13B-13B of the semiconductor device shown in FIG. 13A. 図１３Ａに示す半導体装置の１３Ｃ－１３Ｃ線における断面図である。FIG. 13C is a cross-sectional view of the semiconductor device shown in FIG. 13A taken along line 13C-13C. 第３の実施形態に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on 3rd Embodiment.
　（第１の実施形態）
　図１Ａ及び図１Ｂに示すように第１の実施形態に係る半導体装置は、半導体基板１０１の上に設けられた下地層１１０の上に第１の絶縁膜１２１が設けられている。第１の絶縁膜１２１の上には第１の配線１３１が設けられている。第１の配線１３１を覆うように第１の絶縁膜１２１の上には第２の絶縁膜１２２が設けられている。第２の絶縁膜１２２は、第１の配線１３１の上面を露出する第１の開口部１２２ａ及び第２の開口部１２２ｂを有している。第２の絶縁膜１２２の上には第２の配線１３２が設けられている。第２の配線１３２は、第１の開口部１２２ａ及びその周囲に設けられており、第２の開口部１２２ｂ及びその周囲には設けられていない。第２の配線１３２は、第１の開口部１２２ａにおいて第１の配線１３１と接続されており、第２の開口部１２２ｂにおいては、第１の配線１３１と接続されていない。 (First embodiment)
As shown in FIGS. 1A and 1B, in the semiconductor device according to the first embodiment, a first insulating film 121 is provided on a base layer 110 provided on a semiconductor substrate 101. A first wiring 131 is provided on the first insulating film 121. A second insulating film 122 is provided on the first insulating film 121 so as to cover the first wiring 131. The second insulating film 122 has a first opening 122 a and a second opening 122 b that expose the upper surface of the first wiring 131. A second wiring 132 is provided on the second insulating film 122. The second wiring 132 is provided in the first opening 122a and the periphery thereof, and is not provided in the second opening 122b and the periphery thereof. The second wiring 132 is connected to the first wiring 131 in the first opening 122a, and is not connected to the first wiring 131 in the second opening 122b.
　第２の配線１３２は、バリア層１４１と、バリア層１４１の上に接して設けられたシード層１４２と、シード層１４２の上に接して設けられた電解めっき層とを有している。バリア層１４１は、第２の絶縁膜１２２の上面における第１の開口部１２２ａの周囲の部分、第１の開口部１２２ａの側面及び第１の配線１３１の上面における第１の開口部１２２ａから露出する部分と接している。電解めっき層は、第１のめっき層１４５と、第１のめっき層１４５とシード層１４２との間に設けられた第２のめっき層１４６と、第１のめっき層１４５の上に設けられた第３のめっき層１４７とを有している。第２のめっき層１４６は、シード層１４２と接している。 The second wiring 132 has a barrier layer 141, a seed layer 142 provided in contact with the barrier layer 141, and an electrolytic plating layer provided in contact with the seed layer 142. The barrier layer 141 is exposed from the portion around the first opening 122 a on the upper surface of the second insulating film 122, the side surface of the first opening 122 a, and the first opening 122 a on the upper surface of the first wiring 131. It touches the part to be. The electrolytic plating layer was provided on the first plating layer 145, the second plating layer 146 provided between the first plating layer 145 and the seed layer 142, and the first plating layer 145. A third plating layer 147. The second plating layer 146 is in contact with the seed layer 142.
　平面視において、バリア層１４１、シード層１４２及び第２のめっき層１４６は、ほぼ同じ大きさである。従って、バリア層１４１、シード層１４２及び第２のめっき層１４６の側端部の位置はほぼ一致している。以下において、バリア層１４１、シード層１４２及び第２のめっき層１４６を合わせて下部領域１４８と呼ぶ。下部領域１４８の側面は、半導体基板１０１の主面に対してほぼ垂直となる。 In a plan view, the barrier layer 141, the seed layer 142, and the second plating layer 146 have substantially the same size. Accordingly, the positions of the side end portions of the barrier layer 141, the seed layer 142, and the second plating layer 146 are substantially the same. Hereinafter, the barrier layer 141, the seed layer 142, and the second plating layer 146 are collectively referred to as a lower region 148. The side surface of the lower region 148 is substantially perpendicular to the main surface of the semiconductor substrate 101.
　平面視において、第１のめっき層１４５は、下部領域１４８よりも大きく、下部領域１４８の外側に拡がっている。従って、第１のめっき層１４５は、下部領域１４８の上面及び側面を覆い、下部領域１４８よりも外側において下端部が第２の絶縁膜１２２の上面と接している。このため、下部領域１４８は、第１の配線１３１、第２の絶縁膜１２２及び第１のめっき層１４５により外部から遮断されている。 In plan view, the first plating layer 145 is larger than the lower region 148 and extends outside the lower region 148. Accordingly, the first plating layer 145 covers the upper surface and side surfaces of the lower region 148, and the lower end portion is in contact with the upper surface of the second insulating film 122 outside the lower region 148. For this reason, the lower region 148 is blocked from the outside by the first wiring 131, the second insulating film 122, and the first plating layer 145.
　下部領域１４８は、第１の開口部１２２ａを完全に埋め込んでおらず、下部領域１４８の上面における第１の開口部１２２ａと対応する位置には凹部が存在している。第１のめっき層１４５は、下部領域１４８の凹部を埋めるように設けられている。第１のめっき層１４５は十分に厚く、第１のめっき層１４５の上面は平坦になっている。第１のめっき層１４５の上に設けられた第３のめっき層１４７の上面も平坦になっている。第１のめっき層１４５と第３のめっき層１４７とは、平面視においてほぼ同じ大きさであり、第１のめっき層１４５及び第３のめっき層１４７の側端部の位置はほぼ一致している。 The lower region 148 does not completely fill the first opening 122a, and there is a recess at a position corresponding to the first opening 122a on the upper surface of the lower region 148. The first plating layer 145 is provided so as to fill the concave portion of the lower region 148. The first plating layer 145 is sufficiently thick, and the upper surface of the first plating layer 145 is flat. The upper surface of the third plating layer 147 provided on the first plating layer 145 is also flat. The first plating layer 145 and the third plating layer 147 have substantially the same size in plan view, and the positions of the side end portions of the first plating layer 145 and the third plating layer 147 are substantially the same. Yes.
　バリア層１４１は、例えばチタンからなる。バリア層１４１の厚さは、例えば０．２μｍ程度とすることができる。シード層１４２は、例えば銅からなる。シード層１４２の厚さは、例えば０．２μｍ程度とすることができる。第１のめっき層１４５は、例えばニッケルからなる。第１のめっき層１４５の厚さは、例えば１０μｍ程度とすることができる。第２のめっき層１４６は、例えば銅からなる。第２のめっき層１４６の厚さは、例えば０．４μｍ程度とすることができる。第３のめっき層１４７は、例えば金からなる。第３のめっき層１４７の厚さは、例えば０．３μｍ程度とすることができる。第１のめっき層１４５は、第２の配線１３２を構成する金属層のうち最も質量が大きいベース層である。 The barrier layer 141 is made of, for example, titanium. The thickness of the barrier layer 141 can be set to, for example, about 0.2 μm. The seed layer 142 is made of, for example, copper. The thickness of the seed layer 142 can be set to, for example, about 0.2 μm. The first plating layer 145 is made of nickel, for example. The thickness of the 1st plating layer 145 can be about 10 micrometers, for example. The second plating layer 146 is made of, for example, copper. The thickness of the second plating layer 146 can be set to, for example, about 0.4 μm. The third plating layer 147 is made of, for example, gold. The thickness of the third plating layer 147 can be set to, for example, about 0.3 μm. The first plating layer 145 is a base layer having the largest mass among the metal layers constituting the second wiring 132.
　第２の配線１３２は、第２の開口部１２２ｂの周囲には設けられていない。従って、バリア層１４１及びシード層１４２を含む下部領域１４８並びに第１のめっき層１４５、第２のめっき層１４６及び第３のめっき層１４７は、第２の開口部１２２ｂ及びその周囲には設けられていない。また、バリア層１４１は、第１の配線１３１の第２の開口部１２２ｂから露出する部分とは接していない。第１の配線１３１における第２の開口部１２２ｂから露出する部分は、第１の配線１３１の他の部分よりも窪んだ凹部１３１ａとなっている。 The second wiring 132 is not provided around the second opening 122b. Accordingly, the lower region 148 including the barrier layer 141 and the seed layer 142, the first plating layer 145, the second plating layer 146, and the third plating layer 147 are provided in the second opening 122b and the periphery thereof. Not. Further, the barrier layer 141 is not in contact with a portion exposed from the second opening 122 b of the first wiring 131. A portion of the first wiring 131 exposed from the second opening 122 b is a recess 131 a that is recessed from the other portions of the first wiring 131.
　第１の絶縁膜１２１の上には、第３の配線１３３及び第４の配線１３４が設けられている。第３の配線１３３及び第４の配線１３４は、第１の配線１３１と並行して設けられている。第２の配線１３２は、第１の配線１３１、第３の配線１３３及び第４の配線１３４の上に跨がって形成されている。第２の配線１３２は、第３の配線１３３及び第４の配線１３４とは接続されておらず、第１の配線１３１とのみ接続されている。第２の絶縁膜１２２は、第３の配線１３３を露出する開口部及び第４の配線１３４を露出する開口部を有していなくてよい。第１の配線１３１、第３の配線１３３及び第４の配線１３４は、例えばアルミ配線とすることができる。第３の配線１３３及び第４の配線１３４は設けられていなくてもよい。 A third wiring 133 and a fourth wiring 134 are provided on the first insulating film 121. The third wiring 133 and the fourth wiring 134 are provided in parallel with the first wiring 131. The second wiring 132 is formed over the first wiring 131, the third wiring 133, and the fourth wiring 134. The second wiring 132 is not connected to the third wiring 133 and the fourth wiring 134, and is connected only to the first wiring 131. The second insulating film 122 does not need to have an opening exposing the third wiring 133 and an opening exposing the fourth wiring 134. The first wiring 131, the third wiring 133, and the fourth wiring 134 can be aluminum wiring, for example. The third wiring 133 and the fourth wiring 134 are not necessarily provided.
　下地層１１０の上には、下層配線１１１が設けられている。下層配線１１１は例えばアルミ配線とすることができる。第１の絶縁膜１２１は、下層配線１１１を覆うように設けられている。第１の配線１３１は、第１の絶縁膜１２１を貫通するビア１１２により、下層配線１１１と接続されている。 A lower layer wiring 111 is provided on the base layer 110. The lower layer wiring 111 can be an aluminum wiring, for example. The first insulating film 121 is provided so as to cover the lower layer wiring 111. The first wiring 131 is connected to the lower wiring 111 by a via 112 that penetrates the first insulating film 121.
　第１の絶縁膜１２１及び第２の絶縁膜１２２は、窒化シリコン（ＳｉＮ）膜又はテトラエトキシシラン（ＴＥＯＳ）膜等とすることができる。半導体基板１０１には、トランジスタ等の半導体素子が設けられていてよい。 The first insulating film 121 and the second insulating film 122 can be a silicon nitride (SiN) film, a tetraethoxysilane (TEOS) film, or the like. The semiconductor substrate 101 may be provided with a semiconductor element such as a transistor.
　本実施形態の半導体装置は、配線のうち酸化又はマイグレーションの懸念がある銅等の材料からなる部分の上面及び側面が、ニッケル等の安定した金属からなる皮膜により覆われている。このため、バンプパッド等の配線の上に保護膜が設けられていない半導体装置において、特に信頼性を向上させることができる。また、配線の表面が銅よりも硬度が高いニッケル材料によって被覆されていることにより、バンプの強度を高め、バンプの接続時の圧着力を大きくすることができる。また、ニッケルの上に金を被覆することにより配線の表面をより安定させることができる。このため、接続性を向上させることもできる。 In the semiconductor device of this embodiment, the upper surface and the side surface of a portion made of a material such as copper, which is likely to be oxidized or migrated, of the wiring are covered with a film made of a stable metal such as nickel. For this reason, reliability can be improved particularly in a semiconductor device in which a protective film is not provided on wiring such as bump pads. Further, since the surface of the wiring is covered with a nickel material having a hardness higher than that of copper, the strength of the bump can be increased and the pressure bonding force at the time of connecting the bump can be increased. Further, the surface of the wiring can be further stabilized by coating gold on nickel. For this reason, connectivity can also be improved.
　第１の実施形態に係る半導体装置は以下のようにして形成することができる。まず、図２Ａに示すように、半導体基板１０１の上に設けられた下地層１１０の上に、下層配線１１１を形成する。続いて、下地層１１０の上に第１の絶縁膜１２１を形成する。続いて、第１の絶縁膜１２１に下層配線１１１を露出する開口部を設ける。この後、第１の絶縁膜１２１の上に、第１の配線１３１及びその第１の配線１３１と下層配線１１１とを接続するビア１１２を形成する。続いて、第１の絶縁膜１２１の上に、第１の配線１３１を覆うように、第２の絶縁膜１２２を形成する。この後、第２の絶縁膜１２２に第１の開口部１２２ａ及び第２の開口部１２２ｂを形成する。第１の開口部１２２ａは、第２の配線１３２を設ける領域に形成し、第２の開口部１２２ｂは、第２の配線１３２を設けない領域に形成する。 The semiconductor device according to the first embodiment can be formed as follows. First, as shown in FIG. 2A, a lower layer wiring 111 is formed on a base layer 110 provided on a semiconductor substrate 101. Subsequently, a first insulating film 121 is formed on the base layer 110. Subsequently, an opening for exposing the lower layer wiring 111 is provided in the first insulating film 121. Thereafter, a first wiring 131 and a via 112 that connects the first wiring 131 and the lower layer wiring 111 are formed on the first insulating film 121. Subsequently, a second insulating film 122 is formed on the first insulating film 121 so as to cover the first wiring 131. Thereafter, the first opening 122 a and the second opening 122 b are formed in the second insulating film 122. The first opening 122a is formed in a region where the second wiring 132 is provided, and the second opening 122b is formed in a region where the second wiring 132 is not provided.
　第１の開口部１２２ａ及び第２の開口部１２２ｂは、第２の配線１３２の上面の平坦性を確保できる大きさとすることが好ましい。例えば、第１の開口部１２２ａ及び第２の開口部１２２ｂの平面サイズは５μｍ角程度とすることができる。埋め込み性の観点からは、第１の開口部１２２ａ及び第２の開口部１２２ｂは、角部が面取りされている方が好ましい。第１の開口部１２２ａ及び第２の開口部１２２ｂは、平面正方形状でなくてもよい。また、第１の開口部１２２ａと第２の開口部１２２ｂとは、大きさ及び平面形状の少なくとも一方が異なっていてもよい。 It is preferable that the first opening 122a and the second opening 122b have such a size that the flatness of the upper surface of the second wiring 132 can be ensured. For example, the planar size of the first opening 122a and the second opening 122b can be about 5 μm square. From the viewpoint of embeddability, the first opening 122a and the second opening 122b are preferably chamfered at the corners. The first opening 122a and the second opening 122b do not have to have a planar square shape. Further, the first opening 122a and the second opening 122b may be different in at least one of size and planar shape.
　第１の絶縁膜１２１及び第２の絶縁膜１２２は、ＳｉＮ膜又はＴＥＯＳ膜等とすることができる。第１の絶縁膜１２１及び第２の絶縁膜１２２は化学気相堆積（ＣＶＤ）法等により形成することができる。第１の絶縁膜１２１及び第２の絶縁膜１２２の膜厚は１μｍ程度とすればよい。下層配線１１１、第１の配線１３１は、スパッタ法等によりアルミニウム膜を形成し、その後、リソグラフィー及びドライエッチングによりアルミニウム膜をパターニングして形成することができる。ビア１１２は、第１の絶縁膜１２１に下層配線１１１を露出する開口部を設けておくことにより、第１の配線１３１と同時に形成することができる。 The first insulating film 121 and the second insulating film 122 can be SiN films, TEOS films, or the like. The first insulating film 121 and the second insulating film 122 can be formed by a chemical vapor deposition (CVD) method or the like. The thickness of the first insulating film 121 and the second insulating film 122 may be approximately 1 μm. The lower layer wiring 111 and the first wiring 131 can be formed by forming an aluminum film by sputtering or the like, and then patterning the aluminum film by lithography and dry etching. The via 112 can be formed simultaneously with the first wiring 131 by providing an opening for exposing the lower layer wiring 111 in the first insulating film 121.
　次に、図２Ｂに示すように、第１の開口部１２２ａ及び第２の開口部１２２ｂの内部を含む第２の絶縁膜１２２上の全面にチタンからなるバリア層１４１及び銅からなるシード層１４２を順次形成する。バリア層１４１及びシード層１４２はスパッタ法等により形成することができる。バリア層１４１及びシード層１４２の厚さは、それぞれ０．２μｍ程度とすることができる。続いて、第２の配線１３２を形成する領域を囲むようにレジストパターン１７１を形成する。レジストパターン１７１は、最終的に下部領域１４８となる部分を露出し、外寸が第１のめっき層１４５の外寸と一致するように形成する。レジストパターン１７１の厚さは特に限定されないが、１μｍ程度とすることができる。 Next, as shown in FIG. 2B, a barrier layer 141 made of titanium and a seed layer 142 made of copper are formed on the entire surface of the second insulating film 122 including the insides of the first opening 122a and the second opening 122b. Are sequentially formed. The barrier layer 141 and the seed layer 142 can be formed by a sputtering method or the like. The thicknesses of the barrier layer 141 and the seed layer 142 can be about 0.2 μm, respectively. Subsequently, a resist pattern 171 is formed so as to surround a region where the second wiring 132 is formed. The resist pattern 171 is formed so that the part that will eventually become the lower region 148 is exposed and the outer dimension matches the outer dimension of the first plating layer 145. The thickness of the resist pattern 171 is not particularly limited, but can be about 1 μm.
　次に、図２Ｃに示すように、銅の電解めっきを行い、シード層１４２が露出した部分の上に第２のめっき層１４６となる銅めっき層を形成する。 Next, as shown in FIG. 2C, copper electroplating is performed to form a copper plating layer to be the second plating layer 146 on the portion where the seed layer 142 is exposed.
　次に、図２Ｄに示すように、レジストパターン１７１を除去し、第２のめっき層１４６を厚さが０．４μｍ程度になるまでエッチングする。これにより、レジストパターン１７１に覆われていなかった部分には、バリア層１４１、シード層１４２及び第２のめっき層１４６からなる下部領域１４８が形成される。一方、レジストパターン１７１に覆われていて、第２のめっき層１４６が形成されていなかった部分においては、シード層１４２及びバリア層１４１が除去されて、第２の絶縁膜１２２が露出する。従って、第１の開口部１２２ａの周辺に形成された下部領域１４８と第２の開口部１２２ｂの周辺に形成された下部領域１４８とは、分離される。 Next, as shown in FIG. 2D, the resist pattern 171 is removed, and the second plating layer 146 is etched until the thickness becomes about 0.4 μm. As a result, a lower region 148 including the barrier layer 141, the seed layer 142, and the second plating layer 146 is formed in a portion not covered with the resist pattern 171. On the other hand, the seed layer 142 and the barrier layer 141 are removed and the second insulating film 122 is exposed in a portion that is covered with the resist pattern 171 and where the second plating layer 146 is not formed. Accordingly, the lower region 148 formed around the first opening 122a and the lower region 148 formed around the second opening 122b are separated.
　次に、図３Ａに示すように、第２の配線１３２を形成する領域を露出する開口部を有するレジストパターン１７２を形成する。レジストパターン１７２の開口部は、第１の開口部１２２ａの周辺に形成された下部領域１４８よりも大きくし、第２の絶縁膜１２２の上面が露出するようにする。 Next, as shown in FIG. 3A, a resist pattern 172 having an opening that exposes a region for forming the second wiring 132 is formed. The opening of the resist pattern 172 is larger than the lower region 148 formed around the first opening 122a so that the upper surface of the second insulating film 122 is exposed.
　次に、図３Ｂに示すように、ニッケルの電解めっきを行い、レジストパターン１７２の開口部に第１のめっき層１４５を形成する。この後、第１のめっき層１４５の上に、金の電解めっきを行い、第３のめっき層１４７を形成する。第１のめっき層１４５は、１０μｍ程度の膜厚とすることができる。第３のめっき層１４７は０．３μｍ程度の膜厚とすることができる。 Next, as shown in FIG. 3B, nickel electroplating is performed to form a first plating layer 145 in the opening of the resist pattern 172. Thereafter, gold electroplating is performed on the first plating layer 145 to form a third plating layer 147. The first plating layer 145 can have a thickness of about 10 μm. The third plating layer 147 can have a thickness of about 0.3 μm.
　第１のめっき層１４５及び第３のめっき層１４７を形成する際には、第２の開口部１２２ｂの周辺に形成された下部領域１４８から電流を供給する。第１の開口部１２２ａの周辺に形成された下部領域１４８と、第２の開口部１２２ｂの周辺に形成された下部領域１４８とは分離されているが、第１の配線１３１を介して電気的に接続されている。このため、第１のめっき層１４５は、第１の開口部１２２ａの周辺に形成された下部領域１４８の上面及び側面と、第２の絶縁膜１２２の露出部分を覆うように形成できる。 When forming the first plating layer 145 and the third plating layer 147, current is supplied from the lower region 148 formed around the second opening 122b. The lower region 148 formed around the first opening 122a and the lower region 148 formed around the second opening 122b are separated from each other, but are electrically connected via the first wiring 131. It is connected to the. Therefore, the first plating layer 145 can be formed so as to cover the upper surface and side surfaces of the lower region 148 formed around the first opening 122 a and the exposed portion of the second insulating film 122.
　次に、図３Ｃに示すように、レジストパターン１７２を除去した後、全面エッチ等により第２の配線１３２の下部領域１４８となった部分を除いて、第２のめっき層１４６、シード層１４２及びバリア層１４１を除去する。この際、第１の配線１３１における第２の開口部１２２ｂから露出する部分もエッチングされ、凹部が形成される場合がある。凹部が形成されても半導体装置の動作には問題ない。 Next, as shown in FIG. 3C, after removing the resist pattern 172, the second plating layer 146, the seed layer 142, The barrier layer 141 is removed. At this time, a portion exposed from the second opening 122b in the first wiring 131 may also be etched to form a recess. Even if the recess is formed, there is no problem in the operation of the semiconductor device.
　本実施形態の半導体装置の製造方法によれば、従来のセミアディティブ法を大きく変更することなく、銅からなる部分の酸化又はマイグレーション等を大きく低減した半導体装置を形成できる。このため、配線ショート等の発生が大幅に低減された信頼性が高い半導体装置を実現できる。また、第２の配線の形成位置を、レジストパターンの位置により正確に設定できるという利点も得られる。 According to the method for manufacturing a semiconductor device of this embodiment, a semiconductor device in which oxidation or migration of a portion made of copper is greatly reduced can be formed without greatly changing the conventional semi-additive method. Therefore, it is possible to realize a highly reliable semiconductor device in which the occurrence of wiring shorts or the like is significantly reduced. In addition, there is an advantage that the formation position of the second wiring can be accurately set by the position of the resist pattern.
　（第１の実施形態の第１変形例）
　第１の実施形態の第１変形例について、図４を用いて説明する。図４は第１の実施形態の第１変形例に係る半導体装置の平面構成を示している。 (First modification of the first embodiment)
A first modification of the first embodiment will be described with reference to FIG. FIG. 4 shows a planar configuration of a semiconductor device according to a first modification of the first embodiment.
　本変形例の半導体装置は、第２の配線１３２が幅広の第１の配線１３１の上に形成されている点で、第１の実施形態の半導体装置と異なる。この場合には、図４に示すように、第１の開口部１２２ａを第１の配線１３１の幅に合わせて長方形状としてもよい。これにより、下部領域１４８における第１の配線１３１と接触している部分の割合が高くなり、電解めっきの際に供給する電流量を多くすることができる。これにより、第１のめっき層１４５及び第３のめっき層１４７を安定して形成することが可能となる。 The semiconductor device of this modification is different from the semiconductor device of the first embodiment in that the second wiring 132 is formed on the wide first wiring 131. In this case, as shown in FIG. 4, the first opening 122 a may be rectangular according to the width of the first wiring 131. As a result, the ratio of the portion of the lower region 148 that is in contact with the first wiring 131 is increased, and the amount of current supplied during electrolytic plating can be increased. As a result, the first plating layer 145 and the third plating layer 147 can be stably formed.
　第１の開口部１２２ａの平面サイズは、特に限定されないが下部領域１４８の平面サイズの２０％程度とすることができる。第１の開口部１２２ａの幅は、第２の配線１３２の上面の平坦性を確保する観点から５μｍ程度とすることが好ましい。第１の開口部１２２ａの角部は、埋め込み性の観点から面取りされている方が好ましい。 The planar size of the first opening 122a is not particularly limited, but can be about 20% of the planar size of the lower region 148. The width of the first opening 122 a is preferably about 5 μm from the viewpoint of ensuring the flatness of the upper surface of the second wiring 132. The corner of the first opening 122a is preferably chamfered from the viewpoint of embedding.
　（第１の実施形態の第２変形例）
　図５は、第１の実施形態の第２変形例に係る半導体装置の平面構成を示している。図５に示すように、第１の配線１３１の幅に合わせた長方形状の第１の開口部１２２ａを設ける代わりに、第１の開口部１２２ａを複数設けてもよい。このような構成としても、下部領域１４８における第１の配線１３１と接触している部分の割合を高くし、電解めっきの際に供給する電流量を多くすることができる。特に、第１の開口部１２２ａ同士の間隔をある程度広くすることにより、第２の配線１３２を形成する領域全体にわたって均一に安定して電流を供給することが可能となる。 (Second modification of the first embodiment)
FIG. 5 shows a planar configuration of a semiconductor device according to a second modification of the first embodiment. As shown in FIG. 5, a plurality of first openings 122 a may be provided instead of providing a rectangular first opening 122 a that matches the width of the first wiring 131. Even with such a configuration, the ratio of the portion in contact with the first wiring 131 in the lower region 148 can be increased, and the amount of current supplied during electrolytic plating can be increased. In particular, by increasing the distance between the first openings 122a to some extent, it becomes possible to supply a current uniformly and stably over the entire region where the second wiring 132 is formed.
　第１の開口部１２２ａの平面サイズは、第２の配線１３２の上面の平坦性を確保する観点から５μｍ角程度とすることができる。第１の開口部１２２ａの角部は、埋め込み性の観点から面取りされている方が好ましい。第１の開口部１２２ａの数は２つに限らない、３つ以上設けてもよい。第１の開口部１２２ａを複数設ける場合に、すべてが同じ大きさ及び形状を有していなくてかまわない。 The planar size of the first opening 122a can be about 5 μm square from the viewpoint of ensuring the flatness of the upper surface of the second wiring 132. The corner of the first opening 122a is preferably chamfered from the viewpoint of embedding. The number of the first openings 122a is not limited to two and may be three or more. When a plurality of first openings 122a are provided, all of them may not have the same size and shape.
　（第１の実施形態の第３変形例）
　第１の実施形態においては、シード層１４２と第１のめっき層１４５との間に第２のめっき層１４６を設けた。しかし、図６に示すように、第２のめっき層１４６を設けなくてもよい。第２のめっき層１４６を設けないことにより、半導体装置の製造工数を低減することができる。 (Third Modification of First Embodiment)
In the first embodiment, the second plating layer 146 is provided between the seed layer 142 and the first plating layer 145. However, as shown in FIG. 6, the second plating layer 146 may not be provided. By not providing the second plating layer 146, the number of manufacturing steps of the semiconductor device can be reduced.
　本変形例の半導体装置は以下のようにして形成することができる。まず、図７Ａに示すように、第１の実施形態と同様にして、第２の絶縁膜１２２の上に、バリア層１４１及びシード層１４２を形成する。この後、第２の配線１３２の下部領域１４８となる部分を囲むように開口部が設けられたレジストパターン１７３を形成する。 The semiconductor device of this modification can be formed as follows. First, as shown in FIG. 7A, a barrier layer 141 and a seed layer 142 are formed on the second insulating film 122 in the same manner as in the first embodiment. Thereafter, a resist pattern 173 provided with an opening so as to surround a portion to be the lower region 148 of the second wiring 132 is formed.
　次に、図７Ｂに示すように、レジストパターン１７３をマスクとしてエッチングを行い、シード層１４２及びバリア層１４１を選択的に除去して第２の絶縁膜１２２を露出させる。これにより、バリア層１４１及びシード層１４２からなる下部領域１４８が形成される。第１の開口部１２２ａの周辺に形成された下部領域１４８と第２の開口部１２２ｂの周辺に形成された下部領域１４８とは分離されている。 Next, as shown in FIG. 7B, etching is performed using the resist pattern 173 as a mask, and the seed layer 142 and the barrier layer 141 are selectively removed to expose the second insulating film 122. As a result, a lower region 148 composed of the barrier layer 141 and the seed layer 142 is formed. The lower region 148 formed around the first opening 122a and the lower region 148 formed around the second opening 122b are separated.
　次に、図７Ｃに示すように、レジストパターン１７３を除去した後、第２の配線１３２を形成する領域を露出する開口部を有するレジストパターン１７２を形成する。第１の実施形態と同様に、レジストパターン１７２の開口部は、第１の開口部１２２ａの周辺に形成された下部領域１４８よりも大きくし、第２の絶縁膜１２２の上面が露出するようにする。続いて、第１の実施形態と同様にして、ニッケルの電解めっきを行い、レジストパターン１７２の開口部に第１のめっき層１４５を形成する。 Next, as shown in FIG. 7C, after removing the resist pattern 173, a resist pattern 172 having an opening that exposes a region where the second wiring 132 is to be formed is formed. As in the first embodiment, the opening of the resist pattern 172 is larger than the lower region 148 formed around the first opening 122a so that the upper surface of the second insulating film 122 is exposed. To do. Subsequently, similarly to the first embodiment, nickel electroplating is performed to form a first plating layer 145 in the opening of the resist pattern 172.
　この後、第１の実施形態と同様にして、レジストパターン１７２の除去、シード層１４２及びバリア層１４１の不要部分の除去を行う。 Thereafter, similarly to the first embodiment, the resist pattern 172 is removed, and unnecessary portions of the seed layer 142 and the barrier layer 141 are removed.
　本変形例においては、第２のめっき層１４６を形成しないため、第１の実施形態よりも工数を減らすことができる。 In the present modification, since the second plating layer 146 is not formed, the number of steps can be reduced as compared with the first embodiment.
　第１の実施形態の第１変形例及び第２変形例の半導体装置を、本変形例のようにすることもできる。 The semiconductor device according to the first modification and the second modification of the first embodiment can be configured as in this modification.
　（第２の実施形態）
　第２の実施形態について、図８Ａ及び図８Ｂを用いて説明する。図８Ａ及び図８Ｂは第２の実施形態に係る半導体装置を示している。 (Second Embodiment)
A second embodiment will be described with reference to FIGS. 8A and 8B. 8A and 8B show a semiconductor device according to the second embodiment.
　本実施形態の半導体装置は、厚い銅めっき層である第２のめっき層１４６Ａが設けられ、第２のめっき層１４６Ａよりも薄い第１のめっき層１４５Ａが設けられている点で第１の実施形態の半導体装置と異なる。以下においては、第１の実施形態と相違する点を中心に説明する。 The semiconductor device of the present embodiment is a first implementation in that a second plating layer 146A that is a thick copper plating layer is provided, and a first plating layer 145A that is thinner than the second plating layer 146A is provided. Different from the semiconductor device of the embodiment. In the following, the description will focus on the differences from the first embodiment.
　第１の開口部１２２ａを除く第２の絶縁膜１２２の上における第２のめっき層１４６Ａの厚さは、例えば１０μｍ程度とすることができる。第２のめっき層１４６Ａは、第２の配線１３２を構成する金属層のうち最も質量が大きいベース層である。第２のめっき層１４６Ａは第１の開口部１２２ａを埋めるように設けられている。第２のめっき層１４６Ａの平面サイズは、第１の実施形態と同様にバリア層１４１及びシード層１４２とほぼ同じである。バリア層１４１、シード層１４２及び第２のめっき層１４６Ａからなる下部領域１４８Ａの側面は、ほぼ垂直な面となっている。 The thickness of the second plating layer 146A on the second insulating film 122 excluding the first opening 122a can be, for example, about 10 μm. The second plating layer 146 </ b> A is a base layer having the largest mass among the metal layers constituting the second wiring 132. The second plating layer 146A is provided so as to fill the first opening 122a. The planar size of the second plating layer 146A is substantially the same as that of the barrier layer 141 and the seed layer 142 as in the first embodiment. The side surface of the lower region 148A composed of the barrier layer 141, the seed layer 142, and the second plating layer 146A is a substantially vertical surface.
　第１のめっき層１４５Ａの厚さは０．４μｍ程度とすることができる。第１のめっき層１４５Ａは、第１の実施形態と同様に、下部領域１４８Ａの上面及び側面を完全に覆っている。第１のめっき層１４５Ａの平面サイズは、下部領域１４８Ａよりも大きい。第１のめっき層１４５Ａは、下部領域１４８Ａよりも外側において、第２の絶縁膜１２２と接している。このため、下部領域１４８Ａは、第１の配線１３１、第２の絶縁膜１２２及び第１のめっき層１４５Ａにより外部から遮断されている。 The thickness of the first plating layer 145A can be about 0.4 μm. The first plating layer 145A completely covers the upper surface and the side surface of the lower region 148A, as in the first embodiment. The planar size of the first plating layer 145A is larger than the lower region 148A. The first plating layer 145A is in contact with the second insulating film 122 outside the lower region 148A. Therefore, the lower region 148A is blocked from the outside by the first wiring 131, the second insulating film 122, and the first plating layer 145A.
　第３のめっき層１４７Ａの厚さは０．３μｍ程度とすることができる。第３のめっき層１４７Ａは、上面及び側面を含む第１のめっき層１４５Ａの上に設けられている。第３のめっき層１４７Ａの平面サイズは、第１のめっき層１４５Ａよりも大きい。第３のめっき層１４７Ａは、第１のめっき層１４５Ａよりも外側において、第２の絶縁膜１２２と接している。 The thickness of the third plating layer 147A can be about 0.3 μm. The third plating layer 147A is provided on the first plating layer 145A including the upper surface and the side surface. The planar size of the third plating layer 147A is larger than that of the first plating layer 145A. The third plating layer 147A is in contact with the second insulating film 122 outside the first plating layer 145A.
　本実施形態の半導体装置は、第１の実施形態の半導体装置と同様に、第２の配線１３２における銅からなる部分がニッケル等の安定した金属からなる皮膜により覆われている。このため、バンプパッド等の配線の上に保護膜が設けられていない半導体装置において、特に信頼性を向上させることができる。また、銅めっき層の厚さを厚くすることにより、バンプパッドとしての硬度及び強度を確保しつつ、バンプ接続時における下地配線及び素子への応力を緩和することもできる。電気的抵抗の低減も期待できる。また、第１の実施形態と比べて、ニッケルの使用量を低減できる。 In the semiconductor device of the present embodiment, the copper portion of the second wiring 132 is covered with a film made of a stable metal such as nickel, as in the semiconductor device of the first embodiment. For this reason, reliability can be improved particularly in a semiconductor device in which a protective film is not provided on wiring such as bump pads. Further, by increasing the thickness of the copper plating layer, it is possible to relieve the stress on the underlying wiring and the element at the time of bump connection while ensuring the hardness and strength as a bump pad. Reduction of electrical resistance can also be expected. In addition, the amount of nickel used can be reduced compared to the first embodiment.
　本実施形態の半導体装置は、以下のようにして形成することができる。まず、第１の実施形態と同様にして、図９Ａに示す第２のめっき層１４６までの部分を形成する。 The semiconductor device of this embodiment can be formed as follows. First, similarly to the first embodiment, the portion up to the second plating layer 146 shown in FIG. 9A is formed.
　次に、図９Ｂに示すように、レジストパターン１７１を残したまま、第２の配線１３２を形成する領域に開口を有するレジストパターン１７５を形成する。 Next, as shown in FIG. 9B, a resist pattern 175 having an opening in a region where the second wiring 132 is to be formed is formed with the resist pattern 171 remaining.
　次に、図９Ｃに示すように、銅の電解めっきを行い、レジストパターン１７５の開口部内に銅を積み増し、第２のめっき層１４６Ａを形成する。 Next, as shown in FIG. 9C, copper is electroplated, and copper is accumulated in the openings of the resist pattern 175 to form the second plating layer 146A.
　次に、図１０Ａに示すように、レジストパターン１７１及びレジストパターン１７５を除去し、レジストパターン１７５に覆われていた部分において、第２のめっき層１４６の厚さが０．４μｍ程度となるまでエッチングする。これにより、レジストパターン１７５の開口部に対応する部分には、厚い第２のめっき層１４６Ａを有する下部領域１４８Ａが形成される。レジストパターン１７１に覆われていなかった部分には、薄い第２のめっき層１４６を有する下部領域１４８が形成される。レジストパターン１７１に覆われていた部分はシード層１４２及びバリア層１４１が除去されて、第２の絶縁膜１２２が露出する。従って、下部領域１４８Ａと下部領域１４８とは分離される。 Next, as shown in FIG. 10A, the resist pattern 171 and the resist pattern 175 are removed, and etching is performed until the thickness of the second plating layer 146 reaches about 0.4 μm in the portion covered with the resist pattern 175. To do. As a result, a lower region 148A having a thick second plating layer 146A is formed in a portion corresponding to the opening of the resist pattern 175. A lower region 148 having a thin second plating layer 146 is formed in a portion that is not covered with the resist pattern 171. The seed layer 142 and the barrier layer 141 are removed from the portion covered with the resist pattern 171 and the second insulating film 122 is exposed. Therefore, the lower region 148A and the lower region 148 are separated.
　次に、図１０Ｂに示すように、第２の配線１３２を形成する領域を露出する開口部を有するレジストパターン１７２を形成する。レジストパターン１７２の開口部は、第１の開口部１２２ａの周辺に形成された下部領域１４８Ａよりも大きくし、第２の絶縁膜１２２の上面が露出するようにする。 Next, as shown in FIG. 10B, a resist pattern 172 having an opening that exposes a region for forming the second wiring 132 is formed. The opening of the resist pattern 172 is larger than the lower region 148A formed around the first opening 122a so that the upper surface of the second insulating film 122 is exposed.
　次に、図１０Ｃに示すように、ニッケルの電解めっきを行い、下部領域１４８Ａの上面及び側面を覆う第１のめっき層１４５Ａを形成する。次に、金の電解めっきを行い、第１のめっき層１４５Ａを覆う第３のめっき層１４７Ａを形成する。第１のめっき層１４５Ａ及び第３のめっき層１４７Ａを形成する際には、第１の実施形態と同様に、第２の開口部１２２ｂの周辺に形成された下部領域１４８から電流を供給する。 Next, as shown in FIG. 10C, nickel electroplating is performed to form a first plating layer 145A that covers the upper and side surfaces of the lower region 148A. Next, gold electrolytic plating is performed to form a third plating layer 147A that covers the first plating layer 145A. When the first plating layer 145A and the third plating layer 147A are formed, a current is supplied from the lower region 148 formed around the second opening 122b, as in the first embodiment.
　この後、図１０Ｄに示すように、第１の実施形態と同様にして、レジストパターン１７２の除去、シード層１４２及びバリア層１４１の不要部分の除去を行う。 Thereafter, as shown in FIG. 10D, similarly to the first embodiment, the resist pattern 172 is removed and unnecessary portions of the seed layer 142 and the barrier layer 141 are removed.
　本実施形態の半導体装置の製造方法において、レジストパターン１７１とレジストパターン１７５とは、高精度な位置合わせが不要である。また、レジストパターン１７２は、第２の配線１３２を形成する領域以外に形成されている第２のめっき層１４６を被覆できればよいため、膜厚が薄くてかまわない。また、高精度な位置合わせは不要である。 In the semiconductor device manufacturing method of the present embodiment, the resist pattern 171 and the resist pattern 175 do not need to be aligned with high accuracy. The resist pattern 172 may be thin as long as it can cover the second plating layer 146 formed outside the region where the second wiring 132 is formed. In addition, highly accurate alignment is not necessary.
　本実施形態においては、レジストパターン１７１を除去せずにレジストパターン１７５を形成する例を示した。しかし、レジストパターン１７１を除去してもよい。 In the present embodiment, an example in which the resist pattern 175 is formed without removing the resist pattern 171 is shown. However, the resist pattern 171 may be removed.
　例えば、図１１Ａに示すように、第２のめっき層１４６を形成する工程までを行う。次に、図１１Ｂに示すように、レジストパターン１７１を除去し、第２の配線１３２を形成する領域に開口を有するレジストパターン１７６を形成する。次に、図１１Ｃに示すように、銅の電解めっきを行い、レジストパターン１７６の開口部内に銅を積み増し、第２のめっき層１４６Ａを形成する。 For example, as shown in FIG. 11A, the process up to forming the second plating layer 146 is performed. Next, as shown in FIG. 11B, the resist pattern 171 is removed, and a resist pattern 176 having an opening in a region where the second wiring 132 is formed is formed. Next, as shown in FIG. 11C, copper is electroplated, and copper is stacked in the openings of the resist pattern 176 to form a second plating layer 146A.
　この後、レジストパターン１７６を除去し、第２の実施形態と同様にして、シード層１４２及びバリア層１４１を選択的に除去し、電解めっきにより第１のめっき層１４５Ａ及び第３のめっき層１４７Ａを形成する。続いて、シード層１４２及びバリア層１４１の不要部分の除去を行う。 Thereafter, the resist pattern 176 is removed, and the seed layer 142 and the barrier layer 141 are selectively removed in the same manner as in the second embodiment, and the first plating layer 145A and the third plating layer 147A are electroplated. Form. Subsequently, unnecessary portions of the seed layer 142 and the barrier layer 141 are removed.
　（第２の実施形態の第１変形例）
　第２の実施形態においては、バリア層１４１及びシード層１４２と平面サイズがほぼ等しい第２のめっき層１４６Ａを設ける例を示した。しかし、図１２Ａ～図１２Ｃに示すように、互いに分離された複数の部分２４６に分割された第２のめっき層１４６Ｂを設けてもよい。 (First Modification of Second Embodiment)
In the second embodiment, the example in which the second plating layer 146A having the same planar size as the barrier layer 141 and the seed layer 142 is provided has been described. However, as shown in FIGS. 12A to 12C, a second plating layer 146B divided into a plurality of portions 246 separated from each other may be provided.
　図１２Ａ～図１２Ｃに示すように、本変形例の半導体装置において、第２のめっき層１４６Ｂは、３つの部分２４６を有している。第２の配線１３２の短手方向において、バリア層１４１及びシード層１４２の幅と、部分２４６の幅とはほぼ一致している。一方、第２の配線１３２の長手方向において、部分２４６の幅は、バリア層１４１及びシード層１４２の幅よりも短い。第２の配線１３２の長手方向において、部分２４６は、互いに間隔をおいて一列に設けられている。それぞれの部分２４６の上面及び側面は、第１のめっき層１４５Ｂに覆われている。従って、部分２４６は、第１のめっき層１４５Ｂを介して隣接している。本変形例の半導体装置は、第１のめっき層１４５Ｂが、第２のめっき層１４６Ｂの複数の部分２４６を一体に被覆している。このため、ニッケル等からなる第１のめっき層１４５Ｂは、平面視において格子状となる。従って、第２の配線１３２の強度をさらに向上させることができる。 As shown in FIGS. 12A to 12C, in the semiconductor device of this modification, the second plating layer 146B has three portions 246. In the short direction of the second wiring 132, the widths of the barrier layer 141 and the seed layer 142 substantially coincide with the width of the portion 246. On the other hand, the width of the portion 246 is shorter than the widths of the barrier layer 141 and the seed layer 142 in the longitudinal direction of the second wiring 132. In the longitudinal direction of the second wiring 132, the portions 246 are provided in a row at intervals. The upper surface and the side surface of each portion 246 are covered with the first plating layer 145B. Accordingly, the portion 246 is adjacent via the first plating layer 145B. In the semiconductor device of this modification, the first plating layer 145B integrally covers the plurality of portions 246 of the second plating layer 146B. Therefore, the first plating layer 145B made of nickel or the like has a lattice shape in plan view. Accordingly, the strength of the second wiring 132 can be further improved.
　第２のめっき層１４６Ｂの分割数は３つに限らない。２つであっても、４つ以上であってもよい。また、第２の配線１３２の長手方向において、第２のめっき層１４６Ｂを分割した例を示したが、第２の配線１３２の短手方向において、第２のめっき層１４６Ｂを分割してもよい。また、第２の配線１３２の長手方向と短手方向との両方において、第２のめっき層１４６Ｂを分割して、部分２４６をマトリックス状に配置してもよい。 The number of divisions of the second plating layer 146B is not limited to three. There may be two or four or more. Moreover, although the example which divided | segmented 2nd plating layer 146B in the longitudinal direction of the 2nd wiring 132 was shown, you may divide 2nd plating layer 146B in the transversal direction of the 2nd wiring 132. . Further, the second plating layer 146B may be divided in both the longitudinal direction and the short direction of the second wiring 132, and the portions 246 may be arranged in a matrix.
　本変形例の半導体装置は、レジストパターン１７５の形状を変形することにより第２の実施形態と同様にして形成することができる。 The semiconductor device of this modification can be formed in the same manner as in the second embodiment by changing the shape of the resist pattern 175.
　（第２の実施形態の第２変形例）
　第１変形例においては、部分２４６の１つだけが第１の開口部１２２ａにより第１の配線１３１と接続されている例を示した。しかし、図１３Ａ～図１３Ｃに示すように、複数の部分２４６が第１の開口部１２２ａにより第１の配線１３１と接続されている構成としてもよい。 (Second modification of the second embodiment)
In the first modification, an example is shown in which only one of the portions 246 is connected to the first wiring 131 through the first opening 122a. However, as shown in FIGS. 13A to 13C, the plurality of portions 246 may be connected to the first wiring 131 through the first opening 122a.
　図１３Ａ～図１３Ｃにおいては、第１の開口部１２２ａが第２の配線１３２の短手方向に２つ設けられている。このため、第２の配線１３２の短手方向に隣接する２つの部分２４６が第１の配線１３１と接続されている。但し、第１の開口部１２２ａは１つであってもよい。 13A to 13C, two first openings 122 a are provided in the short direction of the second wiring 132. For this reason, two portions 246 adjacent to each other in the short direction of the second wiring 132 are connected to the first wiring 131. However, the first opening 122a may be one.
　第２のめっき層１４６Ｂの分割数は２×３に限らない。縦方向及び横方向の両方を任意の数に分割したマトリックスとすることができる。第１の開口部１２２ａの数も２つに限らない。第２のめっき層１４６Ｂの分割数に合わせて、第１の開口部１２２ａを設ければよい。 The number of divisions of the second plating layer 146B is not limited to 2 × 3. A matrix in which both the vertical direction and the horizontal direction are divided into an arbitrary number can be used. The number of first openings 122a is not limited to two. The first opening 122a may be provided in accordance with the number of divisions of the second plating layer 146B.
　第２の実施形態及びその変形例の半導体装置においても、第１の配線１３１の形状によっては、第１の実施形態の第１変形例又は第２変形例のような第１の開口部１２２ａを設けることができる。第２の実施形態の第２変形例においては、１つの部分２４６が複数の第１の開口部１２２ａと対応するようにしてもよい。 Also in the semiconductor device of the second embodiment and the modification thereof, the first opening 122a as in the first modification or the second modification of the first embodiment may be formed depending on the shape of the first wiring 131. Can be provided. In the second modification of the second embodiment, one portion 246 may correspond to the plurality of first openings 122a.
　（第３の実施形態）
　第３の実施形態について、図１４を用いて説明する。図１４は第３の実施形態に係る半導体装置を示している。図１４に示すように、デバイスチップ４０１は、左側に入力及び制御信号のバンプパッド群４０２が配置され、右側に出力のバンプパッド群４０３が配置されている。左側のバンプパッド群４０２の個々のバンプパッドは相対的に大きなサイズであるため、第２の実施形態の第２変形例のように、第２の配線のベースとなる銅めっき層をマトリックス状に複数の部分に分割し、ニッケルめっき層を平面視において格子状として強度を向上させたバンプパッドとすることができる。 (Third embodiment)
A third embodiment will be described with reference to FIG. FIG. 14 shows a semiconductor device according to the third embodiment. As shown in FIG. 14, the device chip 401 has a bump pad group 402 for input and control signals arranged on the left side and an output bump pad group 403 arranged on the right side. Since the individual bump pads of the left bump pad group 402 are relatively large in size, like the second modification of the second embodiment, the copper plating layer serving as the base of the second wiring is arranged in a matrix. The bump pad can be divided into a plurality of portions, and the nickel plating layer can have a lattice shape in plan view to improve the strength.
　右側のバンプパッド群４０３の個々のバンプパッドはバンプパッド群４０２の個々のバンプパッドよりも小さく各々の間隔も狭い。このため、ニッケルめっき層と金めっき層を形成するためのレジストパターンは、個々の銅めっき層ごとに開口部を設けなくても、複数個の銅めっき層を含む開口部を形成して、電解めっきを行うことも可能である。 The individual bump pads of the bump pad group 403 on the right side are smaller than the individual bump pads of the bump pad group 402 and the intervals between them are also narrow. For this reason, the resist pattern for forming the nickel plating layer and the gold plating layer is formed by forming an opening including a plurality of copper plating layers without providing an opening for each copper plating layer. Plating can also be performed.
　このような構造によりバンプパッド（第２の配線）の強度を強化した構造とすることができると共に、個々の大きさ、配置の異なるバンプパッド群４０２及び４０３のバランスもとることができる。 With such a structure, the strength of the bump pad (second wiring) can be enhanced, and a balance between the bump pad groups 402 and 403 having different sizes and arrangements can be obtained.
　本開示の半導体装置は、十分な酸化耐性又はマイグレーション耐性を有する配線を備えており、バンプパッド等を有する半導体装置等として有用である。特に、厚膜で、ライン／スペースが細い配線パターンを有する半導体装置等として有用である。 The semiconductor device of the present disclosure includes wiring having sufficient oxidation resistance or migration resistance, and is useful as a semiconductor device having a bump pad or the like. In particular, it is useful as a semiconductor device having a thick film and a wiring pattern with thin lines / spaces.
１０１　　　半導体基板
１１０　　　下地層
１１１　　　下層配線
１１２　　　ビア
１２１　　　第１の絶縁膜
１２２　　　第２の絶縁膜
１２２ａ　　第１の開口部
１２２ｂ　　第２の開口部
１３１　　　第１の配線
１３１ａ　　凹部
１３２　　　第２の配線
１３３　　　第３の配線
１３４　　　第４の配線
１４１　　　バリア層
１４２　　　シード層
１４５　　　第１のめっき層
１４５Ａ　　第１のめっき層
１４５Ｂ　　第１のめっき層
１４６　　　第２のめっき層
１４６Ａ　　第２のめっき層
１４６Ｂ　　第２のめっき層
１４７　　　第３のめっき層
１４７Ａ　　第３のめっき層
１４８　　　下部領域
１４８Ａ　　下部領域
１７１　　　レジストパターン
１７２　　　レジストパターン
１７３　　　レジストパターン
１７４　　　レジストパターン
１７５　　　レジストパターン
１７６　　　レジストパターン
２４６　　　部分
４０１　　　デバイスチップ
４０２　　　バンプパッド群
４０３　　　バンプパッド群 101 Semiconductor substrate 110 Underlayer 111 Lower layer wiring 112 Via 121 First insulating film 122 Second insulating film 122a First opening 122b Second opening 131 First wiring 131a Recess 132 Second wiring 133 Third Wiring 134 Fourth wiring 141 Barrier layer 142 Seed layer 145 First plating layer 145A First plating layer 145B First plating layer 146 Second plating layer 146A Second plating layer 146B Second plating layer 147 Third plating layer 147A Third plating layer 148 Lower region 148A Lower region 171 Resist pattern 172 Resist pattern 173 Resist pattern 174 Resist pattern 175 Resist pattern 176 Resist pattern 246 Portion 401 Device chip 402 Bang Pad group 403 bump pad group

Claims (17)

  1. 　半導体基板の上に形成された第１の絶縁膜と、
    　前記第１の絶縁膜の上に形成された第１の配線と、
    　前記第１の配線を覆うように、前記第１の絶縁膜の上に設けられた第２の絶縁膜と、
    　前記第２の絶縁膜の上に形成された第２の配線とを備え、
    　前記第２の絶縁膜は、前記第１の配線を露出する第１の開口部及び第２の開口部を有し、
    　前記第２の配線は、前記第１の開口部及びその周囲に設けられたシード層と、前記シード層の上に設けられ、前記シード層の全側面を被覆する第１のめっき層とを有し、
    　前記シード層は、前記第２の開口部及びその周囲には設けられていない、半導体装置。     A first insulating film formed on the semiconductor substrate;
    A first wiring formed on the first insulating film;
    A second insulating film provided on the first insulating film so as to cover the first wiring;
    A second wiring formed on the second insulating film,
    The second insulating film has a first opening and a second opening that expose the first wiring,
    The second wiring includes a seed layer provided around the first opening and the periphery thereof, and a first plating layer provided on the seed layer and covering all side surfaces of the seed layer. And
    The seed layer is a semiconductor device which is not provided in the second opening and the periphery thereof.
  2. 　前記シード層は第１の金属からなり、
    　前記第１のめっき層は、前記第１の金属よりも硬度が高い、第２の金属からなる、請求項１に記載の半導体装置。     The seed layer comprises a first metal;
    The semiconductor device according to claim 1, wherein the first plating layer is made of a second metal having a hardness higher than that of the first metal.
  3. 　前記第１の金属は銅であり、
    　前記第２の金属はニッケルである、請求項２に記載の半導体装置。     The first metal is copper;
    The semiconductor device according to claim 2, wherein the second metal is nickel.
  4. 　前記シード層と前記第１のめっき層との間に設けられた第２のめっき層をさらに備え、
    　前記第１のめっき層は、前記第２のめっき層の上面及び全側面を被覆する、請求項１～３のいずれか１項に記載の半導体装置。     A second plating layer provided between the seed layer and the first plating layer;
    The semiconductor device according to any one of claims 1 to 3, wherein the first plating layer covers an upper surface and all side surfaces of the second plating layer.
  5. 　前記第２のめっき層は、前記第２の配線におけるベース層である、請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the second plating layer is a base layer in the second wiring.
  6. 　前記第１の開口部は、複数であり、
    　前記第２のめっき層は、複数の前記第１の開口部のそれぞれに対応して設けられ、互いに分離された複数の部分を有し、
    　前記第１のめっき層は、前記第２のめっき層の前記複数の部分を一体に被覆する、請求項４又は５に記載の半導体装置。     A plurality of the first openings;
    The second plating layer is provided corresponding to each of the plurality of first openings, and has a plurality of portions separated from each other,
    The semiconductor device according to claim 4, wherein the first plating layer integrally covers the plurality of portions of the second plating layer.
  7. 　前記複数の部分は、一列に配置されている、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the plurality of portions are arranged in a line.
  8. 　前記複数の部分は、マトリックス状に配置されている、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the plurality of portions are arranged in a matrix.
  9. 　前記第１のめっき層は、前記第２の配線におけるベース層である、請求項１～３のいずれか１項に記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the first plating layer is a base layer in the second wiring.
  10. 　前記第１の開口部は、複数設けられている、請求項９に記載の半導体装置。 The semiconductor device according to claim 9, wherein a plurality of the first openings are provided.
  11. 　前記第１の開口部は、平面長方形状である、請求項１～１０のいずれか１項に記載の半導体装置。 11. The semiconductor device according to claim 1, wherein the first opening has a planar rectangular shape.
  12. 　前記第１の絶縁膜の上に、前記第１の配線と隣接して設けられた第３の配線をさらに備え、
    　前記第２の配線は前記第１の配線及び前記第３の配線の上に跨がって形成されている、請求項１～１１のいずれか１項に記載の半導体装置。     A third wiring provided adjacent to the first wiring on the first insulating film;
    12. The semiconductor device according to claim 1, wherein the second wiring is formed over the first wiring and the third wiring.
  13. 　前記第２の配線は、前記第１のめっき層の上に設けられた第３のめっき層を有している、請求項１～１２のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 12, wherein the second wiring has a third plating layer provided on the first plating layer.
  14. 　前記第１の配線は、前記第２の開口部から露出する部分に凹部を有する、請求項１～１３のいずれか１項に記載の半導体装置。 14. The semiconductor device according to claim 1, wherein the first wiring has a recess in a portion exposed from the second opening.
  15. 　前記第２の配線はバンプパッドである、請求項１～１４のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 14, wherein the second wiring is a bump pad.
  16. 　前記第１の開口部において、前記シード層と前記第１の配線との間にバリア層が設けられている請求項１～１５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 15, wherein a barrier layer is provided between the seed layer and the first wiring in the first opening.
  17. 　前記シード層と前記バリア層とは側端部の位置が一致している請求項１６に記載の半導体装置。 The semiconductor device according to claim 16, wherein the seed layer and the barrier layer have side end portions that coincide with each other.
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