JP2006245558A - Copper wiring layer, method of forming copper wiring layer, semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a copper wiring layer, which makes it possible to form a copper wiring layer that has a uniform film thickness and is free from disconnection of wiring and generation of leak current between the copper wiring layer and an upper wiring layer in all conductive regions across a wide area. <P>SOLUTION: A method of forming a copper wiring layer is characterized in that the method comprises a process of forming a pattern of a copper seed layer on a substrate and a process of forming a copper wiring layer on the pattern of the copper seed layer by means of electroless plating. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a copper wiring layer, a method for forming a copper wiring layer, a semiconductor device, and a method for manufacturing a semiconductor device, and particularly suitable for manufacturing a display device typified by a liquid crystal display device and a semiconductor device such as ULSI. The present invention relates to the formation of a copper wiring layer to be used.

  In general, aluminum (Al) or an alloy thereof is mainly used as a wiring material in a semiconductor device typified by LSI or ULSI. However, due to the recent demands for miniaturization and thinning due to the improvement in integration, and the demand for improvement in operation speed, etc., copper having lower resistance than Al wiring and high resistance to electromigration and stress migration ( It has been studied to adopt Cu) as a material for next-generation wiring and electrodes.

  Furthermore, in the field of display devices represented by liquid crystal display devices, etc., there is an increase in wiring length due to an increase in display area, and due to demands for monolithic mounting with various additional functions such as a driver circuit for driving and a memory in a pixel. As in the field of semiconductor devices, there is an increasing demand for low resistance wiring.

For fine copper wiring processing, as with Al wiring formation technology, masking technology using PEP (Photo Engraving Process, so-called photolithography), RIE (Reactive Ion Etching) method, etc. It was difficult to realize by simply combining the etching technique. In other words, the vapor pressure of the copper halide is very low compared to the halide of Al and is difficult to evaporate. Therefore, when etching copper using an etching technique such as RIE, the substrate temperature is set to 200 to 300 degrees Celsius. It is necessary to set the temperature at or higher, and there are many problems in practical use. Further, it is necessary to use a mask made of SiO ₂ or SiNx instead of a normal photoresist mask.

  Therefore, as a method for forming a copper wiring layer, for example, a method for forming a copper wiring layer using a damascene method disclosed in Patent Document 1 and Patent Document 2 has been proposed. This damascene method is a method of forming a copper wiring layer by the following process. First, a silicon oxide layer is formed as an insulating layer on a substrate, and a wiring groove having a desired wiring pattern is formed in advance on the insulating layer. Next, in order to prevent copper from diffusing into the silicon oxide layer, a diffusion preventing layer such as TaN, Ta, or TiN is formed as a base layer of the copper wiring layer.

  Next, a PVD (Physical Vapor Deposition) method such as a sputtering method, a plating method, or a CVD (Chemical Vapor Deposition) method using an organic metal material so as to embed a wiring groove on the diffusion prevention layer, etc. Using these various methods, a copper thin layer serving as a copper wiring layer is embedded in the groove and formed over the entire surface of the insulating layer. Thereafter, the copper thin layer is polished using a polishing method such as CMP (Chemical Mechanical Polishing) or etch back until the lower insulating layer is exposed from the substrate surface side (opening end surface of the groove portion). When removed, a wiring pattern made of copper embedded in the trench is formed. Finally, an insulating layer or metal layer having a diffusion preventing function is formed on the copper wiring.

  However, the damascene method as disclosed in Patent Document 1 has the following problems. That is, the damascene method includes a film forming process for forming a metal diffusion prevention layer, a metal seed layer, a metal wiring layer, and a polishing stopper film in addition to a groove processing process for forming at least a groove for embedding wiring, Many processes such as a lithography process, an etching process, and a polishing process are required, which complicates the manufacturing process and increases the manufacturing cost.

  Further, in order to reduce the wiring resistance, it is necessary to increase the cross-sectional area of the wiring. However, increasing the cross-sectional area of the wiring is restricted due to high integration. As a means of increasing the cross-sectional area of the wiring without impairing the high integration, it is conceivable to adopt a groove or via hole having a high aspect ratio (that is, a narrow width and a narrow diameter and a deep groove). It is difficult to fill the via hole with copper, and the copper filling property is low. In addition, a CMP process or the like in which a copper thin layer is formed on the entire surface of the substrate and then unnecessary portions are removed and flattened takes a long processing time and deteriorates throughput.

  Furthermore, a large-sized CMP apparatus corresponding to a large-diameter semiconductor wafer size such as 12 inches in diameter has been developed, but a CMP apparatus apparatus for a display device using a rectangular glass substrate having a larger area than the semiconductor wafer is practical. It has not been converted. Further, in the case of a display device, for example, a large-sized liquid crystal display device, even if the entire surface polishing by CMP or the formation of the wiring layer by the etching method is possible, the thin copper layer portion used as the wiring is the area of the glass substrate. In contrast, the copper thin layer formed is largely removed and discarded. As a result, the utilization efficiency of expensive copper resources as materials becomes very poor, and the product price increases due to the high cost.

As a technique for forming a copper wiring that enables effective use of the copper resource, there is a technique described in Patent Document 3 using an electrolytic plating method. With this technique, a copper plating film can be formed only in the wiring formation region, and the cost can be reduced.
JP 2001-189295 A Japanese Patent Laid-Open No. 11-135504 JP 2004-134771 A

  However, in the case where a copper wiring layer is formed by electrolytic plating on a conductive region such as a wiring layer, an electrode, and an electrode pad of a circuit having a thin film transistor, etc., a process of separating each wiring, electrode, electrode pad, etc. in a later step In addition to the need for a large-area substrate, the film thickness variation due to the distance from the peripheral electrode part for electrolytic plating and the current density distribution, and the influence on elements such as transistors and capacitors are taken into account. There is a problem that a high voltage application method is required.

  An object of the present invention is to provide a copper wiring layer capable of forming a copper wiring layer having a uniform film thickness in all conductive regions over a wide range without occurrence of breakage and leakage current between the upper wiring layer. An object of the present invention is to provide a forming method and a manufacturing method of a semiconductor device.

  Another object of the present invention is to provide a copper wiring layer formed with a uniform film thickness in the entire conductive region over a wide range without occurrence of breakage and leakage current between the upper wiring layer and a semiconductor device including the same Is to provide.

  A first aspect of the present invention includes a step of forming a copper seed layer pattern on a substrate, and a step of forming a copper wiring layer on the copper seed layer pattern by an electroless plating method. A method for forming a copper wiring layer is provided.

  In the method for forming a copper wiring layer according to the first aspect of the present invention, the step of forming the copper seed layer pattern includes forming a copper seed layer on the substrate and etching the copper seed layer into a wiring pattern. Can be done. In addition, the step of forming a pattern of the copper seed layer includes forming at least one wiring pattern layer of a resist layer, an insulating layer, and a metal layer on the copper seed layer, and using the wiring pattern layer as a mask. This can be done by etching the seed layer.

  The copper seed layer is preferably oriented in (111).

  Also, a base barrier layer is formed between the substrate and the copper seed layer, and the base barrier layer is etched using the copper wiring layer as a mask. In addition, a capping metal layer for preventing copper diffusion can be formed on the surface of the copper wiring layer.

    According to a second aspect of the present invention, a source region, a drain region, a channel region sandwiched between the source region and the drain region, a gate insulating film and a gate electrode formed on the channel region on the substrate, In a method for manufacturing a semiconductor device, comprising: a transistor including a source electrode connected to a source region and a drain electrode connected to the drain region; and a wiring layer connected to the gate electrode, the source electrode, and the drain electrode. At least one selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected to at least one of them is a step of forming a copper seed layer pattern, and the copper seed layer pattern A method of manufacturing a semiconductor device, characterized by being formed by a process of forming a copper wiring layer on the surface by electroless plating To provide.

  According to a third aspect of the present invention, there is provided a copper seed layer pattern formed on a substrate, and a copper wiring layer formed on the copper seed layer pattern by an electroless plating method. A copper wiring layer is provided.

  Furthermore, a fourth aspect of the present invention provides a source region, a drain region, a channel region sandwiched between the source region and the drain region, a gate insulating film and a gate electrode formed on the channel region on the substrate. A semiconductor device comprising: a source electrode connected to the source region; a transistor including a drain electrode connected to the drain region; and a wiring layer connected to the gate electrode, the source electrode, and the drain electrode. , At least one selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected to at least one of the gate electrode, the copper seed layer pattern, and the copper seed layer pattern. A semiconductor device including a copper wiring layer formed by an electrolytic plating method is provided.

  Note that in this specification, the copper wiring layer is not limited to wiring that allows current to flow between two distant points, but includes conductive regions such as electrodes such as source electrodes, drain electrodes, and gate electrodes, electrode pads, and lead lines. Any of them shall be included.

  According to the present invention, by performing electroless plating of copper on the pattern of the copper seed layer, a uniform film free from breakage and leakage current between the upper wiring layer in the entire conductive region over a wide range. A thick copper wiring layer can be obtained.

  A method of forming a copper layer by an electroless plating method directly on a barrier layer formed on a substrate using an electroless plating bath after forming a palladium nucleus by a palladium catalyst treatment is known. However, since the film growth by plating is formed so as to cover the surface of the palladium nucleus (several nm to several tens of nm), when the film thickness is thin, a continuous film can be obtained unless the palladium nucleus is formed at a high density. It is difficult, and it is difficult to plate a large area with a uniform thickness.

  In the present invention, the copper wiring layer is formed by the electroless plating method on the pattern of the copper seed layer formed on the substrate, thereby solving all the above problems.

  Hereinafter, a method for forming a copper wiring layer according to an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a cross-sectional view for explaining in order of steps until a resist pattern for processing a copper seed layer is formed. FIGS. 12 and 3 show a copper seed using the resist pattern formed by the step of FIG. It is sectional drawing explaining from etching of a layer to formation of a copper wiring layer in order of a process.

  In FIG. 1 to FIG. 3, the same reference numerals are given to the same parts, and duplicate explanations are omitted. In this specification, the copper wiring layer includes, in an integrated circuit, a display device, and the like, a conductive region such as an electrical wiring for electrically connecting circuit elements, for example, transistors, electrodes, terminals (pads), and the like. Shall be.

  According to the method according to the present embodiment, a copper seed layer is formed in a wiring pattern in advance, and electroless plating is performed on the copper seed layer, so that the copper plating layer is formed only on the surface of all the copper seed layers. Can be formed. According to this method, since the copper wiring layer is electrolessly plated after patterning the copper seed layer, film thickness variation due to the pattern width, disconnection, and upper wiring layer compared to the case where the plating film is formed in the groove Can be prevented from occurring.

  First, as shown in FIG. 1A, a base insulating layer 2, for example, a SiN (silicon nitride) film having a thickness of, for example, 300 nm is formed on the substrate 1 in order to prevent the permeation of impurities from the substrate 1. It is formed. The material of the substrate 1 may be any of a conductor, an insulator, and a semiconductor. The SiN film 2 can be formed on the glass substrate 1 having a relatively flat surface by, for example, plasma CVD.

  Next, as shown in FIG. 1B, a base barrier layer 3 is formed on the base insulating layer 2 having a relatively flat surface. As the base barrier layer 3, for example, a barrier metal made of at least one layer such as Ta, TaN, TiN, TaSiN or the like that suppresses copper diffusion and improves adhesion with the base insulating layer 2 is used. it can. These barrier metals are formed to a thickness of, for example, about 30 nm on the base insulating layer 2 by sputtering.

Formation of Copper Seed Layer Pattern First, as shown in FIG. 1C, a metal seed layer mainly composed of copper, for example, a copper seed layer 4 is formed on a base barrier layer 3 having a relatively flat surface. Is done. As a method for forming the copper seed layer 4, for example, a sputtering method can be used. The copper seed layer 4 is formed to a thickness of 30 nm to 300 nm, for example. The copper seed layer 4 desirably has the crystal orientation of the crystal plane mainly oriented to (111).

  Next, as shown in FIG. 1D, a photoresist layer 5 is formed on the copper seed layer 4. The film formation method of the photoresist layer 5 is, for example, a spin coating method, and the film thickness of the photoresist layer 5 is, for example, 1.2 μm.

  After the photoresist layer 5 has been applied and cured, the substrate 1 is carried into an exposure apparatus, where the photo resist is passed through an exposure mask having a predetermined electrode pattern, a desired wiring formation pattern, a pattern such as a pad, and the like. The resist layer 5 is exposed. After the exposure, the photoresist layer 5 is developed to form a photoresist layer 5a having a desired wiring pattern as shown in FIG.

  Next, as shown in FIG. 2A, the exposed portion of the copper seed layer 4 from the photoresist opening 6 is removed, for example, by etching, thereby forming a copper seed layer pattern 4a. As an etching method of the copper seed layer 4, a wet etching method can be used. Since the copper seed layer is thin, etching can be easily performed and side etching can be suppressed.

  In the case of forming a fine pattern, the exposed copper seed layer 4 is dissolved in water by plasma or reactive ion etching using a gas containing a halogen element such as chlorine gas, chlorine hydrogen gas, hydrogen bromide gas or the like. It is desirable to use a method of removing after converting to copper halide such as CuClx or CuBrx. At this time, since the copper seed layer 4 is thin, copper halide can be sufficiently formed over the thickness of the copper seed layer 4. Of course, it is possible to use a dry process such as sputter etching using argon gas or the like. In that case, it is desirable to use an inorganic insulating layer or a metal layer instead of the resist layer 5 and remove the inorganic insulating layer or the metal layer after etching the copper seed layer. In this way, a copper seed layer pattern 4a can be obtained as shown in FIG.

Formation of Copper Wiring Layer Next, as shown in FIG. 2C, a copper thin film, for example, a copper wiring layer 7 is formed on the copper seed layer 4 by an electroless plating method. Unlike the electroplating method, the electroless plating method does not require wiring formation for applying an electric field and a subsequent cutting step. In addition, since an apparatus for applying an electric field is unnecessary, uniform film formation is possible even on a rectangular substrate in which the size of one side of the substrate 1 exceeds 1 meter. The thickness of the copper wiring layer 7 is 400 nm, for example. The copper wiring layer 7 is formed only on the surface of the copper seed layer 4 as shown in FIG.

  At this time, the copper (plating) wiring pattern 7 was formed only on the copper seed layer pattern 4a by epitaxial growth. For this reason, the crystal grain orientation of the copper seed layer 4 is mainly (111), and the larger the average crystal grain size of the copper seed layer 4 is, the larger the average crystal grain size of the copper (plating) wiring layer 7 is. This is desirable because a copper (plating) wiring layer 7 of resistance is obtained. As a pretreatment for forming the copper wiring layer 7 by the electroless plating method, it is desirable to apply a cleaning process for removing oxides on the surface of the copper seed layer 4.

  As the electroless plating bath, it is desirable to use a neutral electroless plating bath not containing an alkali metal, in which a cobalt salt, for example, a copper salt as a reducing agent is added to a solution containing copper sulfate, but the resist layer is removed. Therefore, it can be applied even to a strongly alkaline plating bath, for example, a plating bath using formaldehyde as a reducing agent can be used. Here, a normal formaldehyde bath uses sodium hydroxide as a pH adjuster. However, when using an organic alkali or the like rather than an inorganic alkali, application of a thin film transistor manufacturing process as in a liquid crystal display device. Is desirable.

  Formation of the copper wiring layer 7 containing copper as a main component by electroless plating enables a thin film to be formed on a glass substrate for a liquid crystal display device having a size of 1 meter or more as the substrate 1.

  Electroless plating of the copper wiring layer 7 only on the copper seed layer 4 is a method having a resource saving effect because copper is not deposited on unnecessary portions. In this way, the copper wiring layer 7 can be formed.

Subsequently, as shown in FIG. 2D, using the copper wiring layer 7 as a mask, the exposed underlying barrier layer 3 is removed by, for example, etching to form a barrier layer pattern 3a. As an etching method, for example, when a Ta-based barrier metal is used as the underlying barrier layer 3, plasma etching using, for example, a mixed gas of CF ₄ gas and O ₂ gas as the etching gas is preferable.

  The copper wiring layer 7 mainly composed of copper has easy diffusibility. Therefore, in order to prevent the diffusion of copper, as shown in FIG. 3, a material having a copper diffusion barrier property, for example, an interlayer insulating layer 8 such as SiN, SiC, benzocyclobutene (BCB) or the like is formed on the copper wiring layer 7. It is desirable to form so as to cover the surface.

  According to the method for forming the copper wiring layer 7 according to the present embodiment, a fine metal wiring mainly composed of copper can be selectively formed. The copper wiring layer 7 can obtain a low specific resistance of 2.5 μΩcm or less even if the wiring film thickness is a thin film of sub-μm order of about 200 to 1000 nm. Furthermore, the low specific resistance copper wiring layer 7 can be formed even on a large substrate 1 having a size of 1 meter or more.

  That is, in the formation of normal electrolytic copper plating or electroless copper plating layer, since the wiring thickness is as thick as about 1 to 30 μm, the film thickness of the plating increases and the crystal grain size increases.

  On the other hand, since wiring such as a liquid crystal display device requires a thin film of the order of sub-μm, the copper wiring layer 7 cannot be made thick. In order to reduce the specific resistance of the copper (plating) wiring layer 7, the crystal grain size of the copper (plating) wiring layer 7 may be increased.

  As means for increasing the crystal grain size of the copper wiring layer, (1) annealing the copper seed layer 4 to increase the crystal grain size of the copper seed layer 4 and then crystal grain size of the copper plating layer 7 formed thereon (2) A method of increasing the crystal grain size of the copper wiring layer after forming an electroless copper plating layer on the copper seed layer 4, and (3) the material of the underlying barrier layer 3 and There is a method of forming a copper seed layer 4 having a large crystal grain size by controlling crystal orientation.

  The copper seed layer 4 having a large crystal grain size can be formed, for example, by selecting a sputtering condition when the copper seed layer 4 is formed by a sputtering method.

  As a method of increasing the crystal grain size of the copper seed layer 4 by annealing the copper seed layer 4, after forming the copper seed layer 4, in a non-oxidizing atmosphere, for example, in a nitrogen atmosphere, in a reducing atmosphere containing hydrogen, or An example is annealing in a vacuum. That is, as a method of increasing the crystal grain size of the copper seed layer 4 by annealing the copper seed layer 4, there is a method of annealing at a temperature of 500 ° C. or less in a nitrogen atmosphere after the copper seed layer 4 is formed. The typical annealing temperature is desirably 200 ° C. to 450 ° C. If it is less than 200 ° C., it takes a long time for crystal growth, and if it exceeds 450 ° C., the surface unevenness tends to increase.

  After forming a copper plating layer on the copper seed layer 4, annealing is performed to increase the crystal grain size of the copper wiring layer. The copper seed layer 4 is formed, and the copper seed layer 4 is formed into a desired shape. There is a method in which after patterning, copper is electrolessly plated to form a copper wiring layer, and then annealed in a non-oxidizing atmosphere. The annealing conditions are preferably 500 ° C. or less, and industrially 200 ° C. to 450 ° C. in a non-oxidizing atmosphere.

  Next, in order to improve the copper diffusion preventing property from the copper wiring layer 7, an embodiment in which a layer having a copper diffusion preventing property is formed on the surface of the copper wiring layer 7 will be described with reference to FIG. I will explain. The same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted because it is duplicated. Since the above embodiment and the steps up to FIG. 2D are the same, the steps after FIG. 2D are shown.

  FIG. 4A is the same as FIG. 2D and is a cross-sectional view showing a state in which the copper wiring layer 7 is formed. After removing the underlying barrier layer 3 exposed using the copper wiring layer 7 as a mask to form a barrier layer pattern 3a, a copper diffusion preventing layer 9 is formed. The copper diffusion preventing layer 9 is a layer formed on the surface (including side surfaces) of the underlying barrier layer 3 for suppressing copper from diffusing from the copper wiring layer 7, for example, a capping metal layer. 9 (FIG. 4B). As the capping metal layer 9, it is desirable to form a layer (for example, CoB, NiB, etc.) 9 mainly composed of cobalt or nickel by an electroless plating method. The copper diffusion prevention layer 9 desirably covers at least the exposed surface of the copper wiring layer 7.

  On the capping metal layer 9, as shown in FIG. 4C, in order to improve the barrier property that suppresses the diffusion of copper from the copper wiring layer 7, a barrier layer such as SiN, SiC, An interlayer insulating layer 8 such as BCB is formed.

  Next, an embodiment in which the adhesion between the base insulating layer 2 and the copper seed layer 4 is increased without using the base barrier layer 3 will be described with reference to FIGS. The same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted because it is duplicated.

First, as shown in FIG. 5 (a), a base insulating film layer 2 is formed on a substrate, for example, a glass substrate 1, and then, as shown in FIG. 5 (b), on the base insulating film layer 2, Although the copper seed layer 4 is mainly composed of copper, a copper alloy seed layer 12 containing at least one metal of Mg, Ta, Ti, Ta, Mo, Mn, Al, W, and Zr is formed. At the interface between the copper alloy seed layer 12 and the base insulating layer 2, an oxide layer of an additive metal having at least a barrier property, such as MgO, TiO ₂ , Ta ₂ O _5, or the like by heat treatment, for example, about 400 ° C. It is desirable to form a layer to improve the adhesion between the base insulating layer 2 and the copper alloy seed layer 12.

  On the copper alloy seed layer 12 thus formed, the copper wiring layer 7 can be formed using a process similar to that of the embodiment shown in FIGS. That is, as shown in FIG. 5C, a photoresist layer 5 is provided on the copper alloy seed layer 12, and then, as shown in FIG. 5D, the photoresist layer 5 is formed into a wiring pattern. Processed.

  Next, the copper alloy seed layer 12 exposed through the opening 6 is etched using the photoresist pattern 5a formed in the wiring pattern as a mask, and the wiring is formed on the base insulating film 2 as shown in FIG. A patterned copper alloy seed layer 12a is formed, and the photoresist pattern 5a is removed by etching as shown in FIG. 6B.

  Thereafter, as shown in FIG. 6C, the copper wiring layer 7 is formed on the copper alloy seed layer pattern 12a having the above wiring pattern by an electroless plating method. That is, an electroless plating film constituting the copper wiring layer 7 is formed on the copper alloy seed layer pattern 12a. The thickness of this electroless plating film is, for example, 400 nm.

  Further, as shown in FIG. 6 (d), an interlayer insulating layer 8 made of a material having a barrier property against copper diffusion from the copper wiring layer 7 is formed on and between the copper wiring layers 7. In this way, the copper wiring layer 7 is formed.

  The means for suppressing the diffusion of copper from the copper wiring element 7 is not limited to one layer of the interlayer insulating layer 8, and two layers may be provided. An embodiment relating to diffusion suppression by two layers is as shown in FIG. 4 described above. That is, after the copper wiring layer 7 is formed as shown in FIG. 4A, the exposed surface including the side surface of the copper wiring layer 7 is made of copper as shown in FIG. A first layer is formed by coating a material layer that suppresses diffusion. The material layer that suppresses copper diffusion is, for example, the capping metal layer 9. The capping metal layer 9 is made of, for example, CoB, CoWB, NiB, NiWB or the like mainly containing cobalt or nickel by an electroless plating method. On the first capping metal layer 9 thus formed, as shown in FIG. 4C, a second interlayer insulating layer 8 is formed to form a two-layer copper diffusion prevention layer. To do.

  A second interlayer insulating layer 8 such as SiN, SiC, or BCB may be formed on the capping metal layer 9.

  The copper wiring layer 7 thus formed is not only a semiconductor integrated circuit and an LCD, but also a signal line, a power line, a scanning line and a TFT formed on a substrate of an organic LED, for example, an active matrix organic LED. Needless to say, the present invention can be applied to electrodes, peripheral wiring, and wiring in a peripheral driving circuit formed on the same substrate. According to the wiring formation method of the above embodiment, a metal wiring mainly composed of copper can be selectively formed, and a fine wiring pattern required for the wiring of the peripheral drive circuit can be formed.

  The method for forming a copper wiring layer according to the embodiment includes a step of forming a copper seed layer in a predetermined pattern on a substrate, and a step of forming a copper wiring layer on the copper seed layer by an electroless plating method. It comprises. According to this method, since the copper wiring layer is formed by an electroless plating method, an electrode for plating is not required, and therefore a copper plating layer can be formed on the copper seed layer even when the plating range is wide. In addition, it is not necessary to separate the copper wirings in a later process. Since the copper plating layer is formed only on the copper seed layer, a copper film is not formed in an unnecessary region, and the utilization efficiency of copper is improved. A copper wiring layer can be formed in the entire conductive region over a wide range.

  Furthermore, the step of forming the copper seed layer in the pattern includes a step of forming a copper seed layer on the substrate and a step of forming the copper seed layer by removing it in a predetermined wiring pattern. According to this method, since the copper wiring layer is electrolessly plated after patterning the copper seed layer as compared with the case where the plating film is formed in the groove, the variation in the film thickness due to the pattern width is small, and disconnection is caused. There is little outbreak. Furthermore, the wiring end face shape is not vertical, and the wiring cross-sectional shape is vertical, so that the coverage property of the upper interlayer insulating layer is good, and the occurrence of leakage current with the upper wiring layer is small.

  Next, an embodiment in which the present invention is applied to a method for manufacturing a semiconductor device will be described with reference to FIGS. The same reference numerals are given to the same parts as those in FIGS. This embodiment relates to a method of manufacturing a semiconductor device having TFTs (thin film transistors) and wirings on an insulating substrate.

  First, the manufacturing process S of the crystallization substrate 18 shown in FIG. 8 will be described with reference to the flowchart shown in FIG. A glass substrate 21 made of a substrate such as quartz or non-alkali glass is transported and positioned at a predetermined position in the plasma CVD apparatus chamber (step-1). Next, a base insulating layer 22 such as a silicon nitride layer is vapor-phase grown on the glass substrate 21 by a plasma CVD method (step-2). Next, on the silicon nitride film 22, a non-single crystal semiconductor layer made of an amorphous silicon layer or a polycrystalline silicon layer to be crystallized, for example, an amorphous silicon layer 23 is plasma to a thickness of 30 nm to 300 nm, for example, about 200 nm. Vapor phase growth is performed by CVD (step-3). Thereafter, in order to form a large grain size crystallized region on the amorphous silicon layer 23, a cap layer having transparency and a heat storage function with respect to incident light, for example, a silicon oxide layer 24 is formed by plasma CVD to have a thickness of 10 nm to 1000 nm. For example, the film is formed to a thickness of 260 nm. The cap layer 24 is made of an insulating layer, has a heat storage function, and is a film for relaxing the temperature drop rate of the non-single-crystal semiconductor layer when crystallizing by irradiation with laser light. In this way, the crystallization substrate 18 is manufactured (step-4).

  Next, the crystallization step T is performed. First, the manufactured substrate 18 to be crystallized is placed at a predetermined position on the substrate sample stage 19 of the crystallization apparatus 26. An excimer laser beam having a light intensity distribution with a reverse peak pattern is transmitted through the silicon oxide layer 24 serving as a cap layer at a predetermined crystallization position of the substrate 18 to be crystallized conveyed to the crystallization apparatus 26 to be amorphous. The porous silicon layer 23 is irradiated (step-5), and a crystallized region having a large grain size is formed in the irradiated region (step-6). The irradiation region in such an irradiation process is sequentially moved to a predetermined position while moving the amorphous silicon layer 23, and the crystallization process is performed.

The excimer laser light is, for example, a KrF excimer laser having an energy density of 500 mJ / cm ² . Position information for crystallization is stored in advance in the computer of the crystallization apparatus 26. This computer is automatically positioned at a crystallization position in the non-crystallized substrate 18 according to a command, irradiates laser light for crystallization, sequentially moves the irradiation position, sequentially performs crystallization, and crystallizes. Step T ends.

  That is, in the crystallization step T, the surface of the cap layer 24 is irradiated with excimer pulse laser light having a reverse peak light intensity distribution R using a phase modulation excimer laser crystallization method. By the laser irradiation with the pulse laser beam, the irradiated region of the amorphous silicon layer 23 becomes high temperature and melts. The high temperature at this time heats the base insulating layer 22 and the cap layer 24 and accumulates heat in the base insulating layer 22 and the cap layer 24. The melted region is cooled during the pulsed laser beam blocking period, and the solidification position slowly moves in the lateral direction (horizontal direction) due to the heat accumulation, so that the crystal grows to form a large grain size crystallized region.

  As a result, part or the entire region of the amorphous silicon layer 23 is crystallized and converted into a crystalline silicon layer. Irradiation with pulsed laser light having a reverse peak-like high intensity distribution R may be performed once, but may be performed several times so that the same part or a part of the region overlap, and irradiation with pulsed laser light and a flash lamp Light irradiation may be combined. In this specification, the amorphous silicon layer 23 crystallized in this way is defined as a crystalline silicon layer.

Next, a process U for forming a semiconductor device such as a TFT on the semiconductor thin film after the crystallization process T will be described. A silicon oxide layer (SiO ₂ ) that is the cap layer 24 is formed on the surface of the substrate 18 to be crystallized after the crystallization step T has been completed.

  In this embodiment, the cap layer 24 provided for forming the TFT in the large grain crystallized region in the previous step is removed by etching (step-7). The crystalline silicon layer after the crystallization step T is exposed on the surface of the non-crystallized substrate 18 from which the cap layer 24 has been removed.

  Next, a semiconductor device, for example, a TFT (thin film transistor) is formed on the glass substrate 21 after the crystallization step T is completed. First, the glass substrate 21 is transferred into a plasma CVD reaction chamber, and a gate insulating layer 30 is formed on the exposed surface of the crystalline silicon layer 27 of the transferred glass substrate 21 as shown in FIG. A silicon oxide film is formed for this purpose (step-8). The gate insulating layer 30 is a silicon oxide film having a thickness of 30 nm, for example.

  Thereafter, a gate electrode 31 made of MoW is formed at a predetermined wiring pattern position of the gate insulating layer 30 (step-9).

  Impurity ions are ion-implanted at a high concentration in the crystallization region using the formed gate electrode 31 as a mask. Impurity ions are ion-implanted, for example, for phosphorus in the case of an N-channel transistor, and boron, for example, for a P-channel transistor. Thereafter, annealing is performed in a nitrogen atmosphere (for example, at 550 ° C. for 1 hour) to activate the impurities and form the source region S and the drain region D in the crystallization region. As a result, a channel region C in which carriers move is formed between the formed source region S and drain region D (step -10).

Next, an interlayer insulating layer 32 having a laminated structure of SiO ₂ and SiN or BCB is formed on the gate insulating layer 30 and the gate electrode 31, respectively. Contact holes for forming the source electrode 33, the drain electrode 34, and the wirings 35 and 36 connected to the electrodes 33 and 34 are formed in the interlayer insulating layer 32 (step 11).

  Next, the stacked structure of the base barrier layer 3, the copper seed layer 4, and the copper wiring layer 7 that constitutes the source electrode 33 and the drain electrode 34 in the formed contact hole, as described with reference to FIGS. 1 to 3. Is deposited. Further, wirings 35 and 36 including a base barrier layer 3, a copper seed layer 4 and a copper wiring layer 7 having a predetermined pattern are formed on the interlayer insulating layer 32 using a photolithography technique, and a thin film transistor ( TFT) 39 and a semiconductor device 40 including the thin film transistor (TFT) 39 are manufactured (Step-12).

  Next, on the TFT 39, for example, SiN or a stacked body of SiN and BCB is formed as the passivation layer 41. Next, a contact hole is formed at a predetermined desired position such as an electrode pad of the passivation layer 41 (step -13). This electrode pad can also be formed by the laminated structure of the base barrier layer 3, the copper seed layer 4, and the copper wiring layer 7 described with reference to FIGS.

  In the above embodiment, the example using the MoW layer as the gate electrode has been described. However, the laminated structure of the base barrier layer 3, the copper seed layer 4, and the copper wiring layer 7 described with reference to FIGS. Can be formed. The wiring pattern is in the form of an electrode, a pad, a wiring or the like.

  Next, the crystallization apparatus 26 in the crystallization step T described in the above embodiment will be specifically described with reference to FIGS. The crystallization apparatus 26 includes an illumination system 51, a phase modulation element 52 provided on the optical axis of the illumination system 51, a crystal optical system 53 provided on the optical axis of the phase modulation element 52, and this connection. It comprises a substrate sample stage 19 that supports the crystallized substrate 18 provided on the optical axis of the image optical system 53.

  The illumination system 51 is an optical system shown in FIG. 9 and includes, for example, a light source 56 and a homogenizer 57. The light source 56 includes a XeCl excimer laser light source that supplies light having a wavelength of 308 nm. The light source 56 may be an excimer laser such as a KrF excimer laser light source that emits pulsed light having a wavelength of 248 nm or an ArF laser that emits pulsed light having a wavelength of 193 nm. Further, the light source 56 may be a YAG laser light source. As the light source 56, another appropriate light source that outputs energy for melting the non-single-crystal semiconductor film, for example, the amorphous silicon layer 23 can be used. A homogenizer 57 is provided on the optical axis of the laser light emitted from the light source 56.

  The homogenizer 57 includes, for example, a beam expander 58, a first fly-eye lens 59, a first condenser optical system 60, a second fly-eye lens 61, and a second fly on the optical axis of the laser light from the light source 56. A condenser optical system 62 is sequentially provided. The homogenizer 57 equalizes the intensity of the laser beam emitted from the light source 56 and the incident angle to the phase modulation element 52 within the cross section of the light beam.

  That is, in the illumination system 51, the laser light incident from the light source 56 is magnified by the beam expander 58 and then enters the first fly-eye lens 59. A plurality of light sources are formed on the rear focal plane of the first fly-eye lens 59, and light beams from these plurality of light sources pass through the incident surface of the second fly-eye lens 61 via the first condenser optical system 60. Illuminate in a superimposed manner. As a result, more light sources are formed on the rear focal plane of the second fly-eye lens 61 than on the rear focal plane of the first fly-eye lens 59. Light beams from a large number of light sources formed on the rear focal plane of the second fly-eye lens 61 are incident on the phase modulation element 52 via the second condenser optical system 62 and are illuminated in a superimposed manner.

  As a result, the first fly-eye lens 59 and the first condenser optical system 60 of the homogenizer 57 constitute a first homogenizer, and perform a uniformization process on the incident angle of the laser light incident on the phase modulation element 52. Further, the second fly-eye lens 61 and the second condenser optical system 62 constitute a second homogenizer, and the laser beam whose incident angle from the first homogenizer is made uniform by the second homogenizer on the phase modulation element 52. The light intensity is uniformized at each position in the plane. Thus, the illumination system 57 forms laser light having a substantially uniform light intensity distribution, and this laser light enters the phase modulation element 52.

  The phase modulation element 52, for example, a phase shifter, is an optical element that phase-modulates the light emitted from the homogenizer 57 and emits a laser beam with a reverse peak-shaped minimum light intensity distribution. In the inverse peak-shaped light intensity minimum distribution, the horizontal axis is the place (position on the irradiated surface), and the vertical axis is the light intensity (energy). An optical system for obtaining a reverse peak light intensity minimum distribution includes a concavo-convex pattern formed on a transparent substrate, for example, quartz glass, and a line and space pattern and an area modulation pattern.

  The phase shifter adds a step (unevenness) to a transparent body, for example, a quartz substrate, causes diffraction and interference of laser light at the boundary of the step, and imparts a periodic spatial distribution to the laser light intensity. The phase shifter is, for example, a case where a phase difference of 180 degrees is added on the left and right with the stepped portion x = 0 as a boundary. In general, when the wavelength of the laser beam is λ, a transparent medium having a refractive index n is formed on a transparent substrate to give a phase difference of 180 degrees. The film thickness t of the transparent medium is t = λ / 2 (n -1). If the refractive index of the quartz substrate is 1.46, the wavelength of the XeCl excimer laser light is 308 nm. Therefore, in order to add a phase difference of 180 degrees, a step of 334.8 nm is formed by a method such as photoetching. .

In addition, when the SiN _x film is formed as a transparent medium by PECVD, LPCVD, etc., if the refractive index of the SiN _x film is 2.0, the SiN _x film is formed on the quartz substrate at 154 nm and photoetched. Just add a step. For example, the intensity of laser light that has passed through a phase shifter with a phase difference of 180 degrees shows a pattern of periodic strength (line and space).

  In this embodiment, the mask in which the steps themselves are formed periodically is a periodic phase shifter. Both the width of the phase shift pattern and the distance between patterns are, for example, 3 μm. The phase difference does not necessarily need to be 180 degrees, and may be a phase difference that can realize the strength and weakness of the laser beam.

  The laser light phase-modulated by the phase modulation element 52 is incident on the crystallized substrate 18 via the imaging optical system 53. Here, the imaging optical system 53 optically conjugates the pattern surface of the phase modulation element 52 and the crystallized substrate 18. In other words, the height position of the substrate sample stage 19 is set so that the crystallized substrate 18 is set to a surface optically conjugate with the pattern surface of the phase modulation element 52 (image surface of the imaging optical system 53). It is corrected. The imaging optical system 53 includes an aperture stop 67 between the positive lens group 65 and the positive lens group 66. The imaging optical system 53 is an optical lens that forms an image on the crystallized substrate 18 by reducing the image of the phase modulation element 52 at the same magnification or reduction, for example, 1/5.

  The aperture stop 67 has a plurality of aperture stops having different sizes of openings (light transmission portions). The plurality of aperture stops 67 may be configured to be replaceable with respect to the optical path. Alternatively, the aperture stop 67 may have an iris diaphragm that can continuously change the size of the opening. In any case, the size of the aperture of the aperture stop 67 (and consequently the image-side numerical aperture NA of the imaging optical system 4) is a required light intensity distribution on the semiconductor film of the crystallized substrate 18, as will be described later. Is set to generate. The imaging optical system 53 may be a refractive optical system, a reflective optical system, or a refractive / reflective optical system.

  In addition, as shown in FIG. 8, the crystallized substrate 18 is a silicon oxide layer, an object to be crystallized, as a base insulating layer 22 on a plate glass 21 for liquid crystal display, for example, by chemical vapor deposition (CVD) or sputtering. An amorphous silicon layer 23 is formed as a layer, and a silicon oxide layer is sequentially formed as a cap layer 24.

The amorphous silicon layer 23 is a film to be crystallized, and is selected to have a thickness of, for example, 30 to 250 nm. The cap layer 24 stores heat generated when the amorphous silicon layer 23 is melted during the crystallization process, and this heat storage action contributes to the formation of a crystallized region having a large particle size. The cap layer 24 is an insulating film such as a silicon oxide film (SiO ₂ ) and has a thickness of 100 nm to 400 nm, for example, 300 nm.

  The substrate 18 to be crystallized is automatically transferred onto the substrate sample stage 19 of the crystallization apparatus 26, positioned and placed at a predetermined position, and held by a vacuum chuck, an electrostatic chuck or the like. .

  Next, the crystallization process will be described with reference to FIGS. The pulsed laser light emitted from the laser light source 56 enters the homogenizer 57, and the light intensity is made uniform and the incident angle to the phase modulation element 52 is made uniform within the beam diameter of the laser light. That is, the homogenizer 57 spreads the laser beam incident from the light source 56 in the horizontal direction to form a linear (for example, a line length of 200 mm) laser beam, and makes the light intensity distribution uniform. For example, a plurality of X direction cylindrical lenses are arranged in the Y direction to form a plurality of light beams arranged in the Y direction, each light beam is redistributed by another X direction cylindrical lens, and similarly, a plurality of Y direction cylindrical lenses are A plurality of light beams arranged in the direction and in the X direction are formed, and each light beam is redistributed by another Y-direction cylindrical lens.

  The laser beam is a XeCl excimer laser beam with a wavelength of 308 nm, and the pulse duration of one shot is 20 to 200 ns. When the phase modulation element 52 is irradiated with pulsed laser light under the above conditions, the pulsed laser light incident on the periodically formed phase modulation element 52 causes diffraction and interference at the stepped portion. As a result, the phase modulation element 52 generates a strong and weak light intensity distribution in a reverse peak pattern that changes periodically.

  The intensity distribution of the intensity in the reverse peak pattern outputs a laser beam intensity that melts the amorphous silicon layer 23 from the minimum light intensity to the maximum light intensity. The pulse laser beam that has passed through the phase modulation element 52 is focused on the crystallized substrate 18 by the imaging optical system 53 and is incident on the amorphous silicon layer 23.

  That is, the incident pulse laser beam is almost transmitted through the cap layer 24 and absorbed by the amorphous silicon layer 23. As a result, the irradiated region of the amorphous silicon layer 23 is heated and melted. The heat at the time of melting is stored in the silicon oxide film of the cap layer 24 and the base insulating layer 22.

  When the pulsed laser beam irradiation is in the cut-off period, the irradiated region tries to cool down at a high speed, but heat is stored in the cap layer 24 provided on the front and back surfaces and the silicon oxide film of the base insulating layer 22. The temperature drop rate becomes extremely gradual. At this time, the temperature of the irradiated region is lowered according to the light intensity distribution of the reverse peak pattern generated by the phase modulation element 52, and crystals are sequentially grown in the lateral direction.

  In other words, the solidification position in the melted region in the irradiated region gradually moves from the low temperature side to the high temperature side. That is, the crystal grows laterally from the crystal growth start position toward the crystal growth end position. In this way, the crystallization process using one-pulse laser light is completed. The crystallized region thus crystal-grown is large enough to form one or a plurality of TFTs.

  The crystallization device 26 automatically irradiates the next crystallization region of the amorphous silicon layer 23 with pulsed laser light according to a program stored in advance to form a crystallization region. The movement to the next crystallization position can be performed by relatively moving the crystallized substrate 18 and the light source 56, for example, by moving the substrate sample stage 19.

  When the region to be crystallized is selected and alignment is completed, the next pulse laser beam is emitted. By repeating such a shot of laser light, the crystallized substrate 18 can be crystallized over a wide range. In this way, the crystallization process is completed.

In this embodiment, not only a semiconductor device but also an LCD, an organic RL display device (OLED), for example, a signal line, a power line, a scanning line and an electrode in a TFT formed on a substrate of an active matrix type organic OLED, and the periphery The present invention can also be easily applied to wiring, wiring in a peripheral drive circuit formed on the same substrate, and the like. In the above embodiment, a transistor having a crystalline silicon semiconductor layer has been described. Of course, the transistor also has a polycrystalline silicon semiconductor layer, an amorphous silicon transistor having a gate electrode under the semiconductor layer, and peripheral wiring. It is also easy to do. When applied to a gate electrode of an amorphous silicon transistor having a lower gate structure, a gate insulating film formed thereon has a laminated structure of a silicon nitride layer having a barrier property, hafnium oxide (HfO ₂ ), and silicon oxide. It is desirable to do.

  As described above, according to the embodiment, a low resistance copper wiring having a specific resistance of, for example, 2.5 μΩcm or less can be realized. In particular, a semiconductor device such as a thin film transistor or a thin film transistor circuit can be formed. Furthermore, a copper wiring having a desired cross-sectional area can be formed. Furthermore, even if it is a large sized board | substrate, a copper plating layer can be formed in the whole electroconductive area | region desired over a wide range.

It is sectional drawing explaining an example of the formation method of the copper wiring layer which concerns on one Embodiment of this invention to process order. It is sectional drawing explaining an example of the formation method of the copper wiring layer which concerns on one Embodiment of this invention to process order. It is sectional drawing explaining 1 process of the formation method of the copper wiring layer which concerns on one Embodiment of this invention. It is sectional drawing explaining other examples of the formation method of the copper wiring layer which concerns on one Embodiment of this invention to process order. It is sectional drawing explaining further another example of the formation method of the copper wiring layer which concerns on one Embodiment of this invention to process order. It is sectional drawing explaining further another example of the formation method of the copper wiring layer which concerns on one Embodiment of this invention to process order. It is a process flow figure explaining the manufacturing method of the semiconductor device concerning other embodiments of the present invention in order of a process. It is a figure which shows the structure of the crystallization apparatus for demonstrating the crystallization process in FIG. It is a figure for demonstrating the structure of the illumination system in FIG. It is sectional drawing explaining the structure of the semiconductor device manufactured by the method shown in FIG.

Explanation of symbols

  1, 21 ... Substrate, 2, 22 ... Underlying insulating layer, 3 ... Underlying barrier layer, 4,12 ... Copper seed layer, 4a, 12a ... Copper seed layer pattern, 5 .... Photoresist layer, 5a ... Photoresist layer pattern, 6 ... Photoresist opening, 7 ... Copper wiring layer, 8 ... Interlayer insulating layer, 9 ... Capping metal layer, 12 ... -Copper alloy seed layer, 18 ... substrate to be crystallized, 19 ... substrate sample table, 23 ... amorphous silicon layer, 24 ... cap layer, 26 ... crystallizer, 27 ... Crystalline silicon layer, 30 ... gate insulating layer, 31 ... gate electrode, 32 ... interlayer insulating layer, 33 ... source electrode, 34 ... drain electrode, 35, 36 ... Wiring 39 ... Thin film transistor (TFT) 40 ... Semiconductor device 51 Illumination system 52: phase modulation element 53 ... crystal optical system 56 ... light source 57 ... homogenizer 58 ... beam expander 59 ... first fly eye lens 60 ... 1st condenser optical system, 61 ... 2nd fly eye lens, 62 ... 2nd condenser optical system.

Claims (10)

A method of forming a copper wiring layer, comprising: forming a copper seed layer pattern on a substrate; and forming a copper wiring layer on the copper seed layer pattern by an electroless plating method.   The method of claim 1, wherein forming the copper seed layer pattern comprises forming a copper seed layer on a substrate and etching the copper seed layer into a wiring pattern. .   The step of forming a pattern of the copper seed layer includes forming at least one wiring pattern layer of a resist layer, an insulating layer, and a metal layer on the copper seed layer, and using the wiring pattern layer as a mask. The method of claim 2 including etching the copper seed layer.   The method according to claim 1, wherein the copper seed layer is mainly oriented in (111).   The method according to claim 1, wherein the copper wiring layer has one shape selected from the group consisting of an electrode, a pad, and a wiring.   6. The method according to claim 1, further comprising: forming a base barrier layer between the substrate and the copper seed layer; and etching the base barrier layer using the copper wiring layer as a mask. The method according to any one.   The method according to claim 1, further comprising a step of forming a capping metal layer for preventing copper diffusion on the surface of the copper wiring layer. On a substrate, a source region, a drain region, a channel region sandwiched between the source region and the drain region, a gate insulating film and a gate electrode formed on the channel region, a source electrode connected to the source region, And a method of manufacturing a semiconductor device comprising: a transistor including a drain electrode connected to the drain region; and a wiring layer connected to the gate electrode, the source electrode, and the drain electrode.
At least one selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected to at least one of them, a step of forming a copper seed layer pattern, and a pattern of the copper seed layer A method of manufacturing a semiconductor device, comprising: forming a copper wiring layer on the substrate by an electroless plating method.   A copper wiring layer comprising: a copper seed layer pattern formed on a substrate; and a copper wiring layer formed on the copper seed layer pattern by an electroless plating method.   On a substrate, a source region, a drain region, a channel region sandwiched between the source region and the drain region, a gate insulating film and a gate electrode formed on the channel region, a source electrode connected to the source region, And a transistor including a drain electrode connected to the drain region, and a wiring layer connected to the gate electrode, the source electrode, and the drain electrode, the gate electrode, the source electrode, the drain electrode, And at least one selected from the group consisting of wiring connected to at least one of them includes a copper seed layer pattern, and a copper wiring layer formed on the copper seed layer pattern by an electroless plating method. A semiconductor device comprising:

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