KR101061763B1 - Manufacturing method of array substrate for liquid crystal display device using polysilicon - Google Patents

Abstract

An array substrate for a liquid crystal display device using a conventional polysilicon, particularly an array substrate of a PMOS type, is manufactured by a six-mask process using a top gate method. However, since the mask process proceeds with the application, exposure, development, and etching of the photoresist, it is advantageous to reduce the manufacturing cost and improve the yield by performing the mask process with fewer times.

The present invention is characterized by forming a thin film transistor as a bottom gate structure, by performing a back exposure using a gate electrode as a mask without a mask having a special pattern in the progress of a mask process for forming a doping blocking mask for p + doping. The doped ohmic contact layer is prevented from shifting with respect to the gate electrode to prevent defects caused by misalignment of the mask, to form a thin film transistor having excellent characteristics. The present invention provides a method of manufacturing an array substrate for a liquid crystal display device using polysilicon, which can reduce manufacturing time and reduce manufacturing cost by reducing the number of times or four times.

Poly Silicon, Process Simplification, Mask Reduction, Diffraction Exposure, Bottom Gate

Description

Method of fabricating array substrate for liquid crystal display device using poly-silicon}             

1 is a plan view schematically showing an array substrate for a liquid crystal display device using a general polysilicon.

2 to 7 are cross-sectional views of manufacturing processes of a thin film transistor forming unit of a PMOS type array substrate using conventional polysilicon.

8 to 19 are cross-sectional views of manufacturing processes of an array substrate for a liquid crystal display device using polysilicon according to a first embodiment of the present invention.

20 to 22 are cross-sectional views of manufacturing processes of an array substrate for a liquid crystal display device using polysilicon according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101 substrate 103 buffer layer

113: gate electrode 118: gate insulating film

123: polysilicon layer 130: photoresist layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing an array substrate for a liquid crystal display device using polysilicon as a semiconductor layer.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device may be classified into a passive matrix liquid crystal display device and an active matrix liquid crystal display device according to a method of driving pixels. Among them, an active matrix liquid crystal display device is driven by a thin film transistor in which one pixel is formed for each pixel.

The thin film transistor is composed of a gate electrode, a semiconductor layer, a gate and a source electrode, of which the semiconductor layer is a channel is formed to determine the characteristics of the thin film transistor.

Such semiconductor layers generally use amorphous silicon or polysilicon, and recently, semiconductor layers of thin film transistors have been replaced with amorphous silicon and polysilicon. This is because polysilicon has the advantages of higher electric field mobility, little light leakage current, and fabrication of a driving circuit on a substrate, compared to amorphous silicon.

FIG. 1 is a plan view schematically illustrating an array substrate for a liquid crystal display device using general polysilicon.

As shown in the drawing, an array substrate for a liquid crystal display device using a conventional polysilicon is formed on a substrate together with a display portion 3 and a driving circuit portion 5 for displaying an image. The display unit 3 is positioned at the center of the substrate 1, and gate and data driving circuit units 5a and 5b are positioned at one side of the display unit 3 and the other side not parallel thereto. In the display unit 3, a plurality of gate lines 7 connected to the gate driving circuit unit 5a and a plurality of data lines 9 connected to the data driving circuit unit 5b cross each other. The pixel electrode 10 is formed in the defined pixel region P, and the thin film transistor Tr, which is a switching element connected to the pixel electrode 10, is positioned at the intersection of the two wires.

In addition, the gate and data driving circuit units 5a and 5b are connected to an external signal input terminal 12, and the gate and data driving circuit units 5a and 5b are external signals input through the external signal input terminal 12. Is internally adjusted to supply the display control signal and the data signal to the display unit 3 through the gate and data lines 7 and 9, respectively. Therefore, a complementary metal-oxide semiconductor (CMOS) or a p channel metal-oxide semiconductor (PMOS) inverter is formed in the gate and data driving circuit units 5a and 5b to appropriately output an input signal.

The above-described array substrate for a liquid crystal display device using polysilicon can be divided into CMOS or PMOS type depending on whether CMOS is configured as an inverter or PMOS in the driving circuit unit. PMOS type array substrates that can be fabricated as steps have been widely used.                         

An array substrate constituted of a PMOS type element can be produced by performing p + doping on a semiconductor layer of polysilicon in a thin film transistor constituting a driving element of a driving circuit portion and a switching element in a pixel.

 Hereinafter, a method of manufacturing a PMOS type array substrate using general polysilicon will be described with reference to the drawings.

2 to 7 are cross-sectional views of a thin film transistor forming unit of a PMOS type array substrate using polysilicon.

As shown in FIG. 2, an inorganic insulating material is deposited on the transparent substrate 20 to form a buffer layer 25. Next, amorphous silicon (a-Si) is deposited on the entire surface of the substrate 20 on which the buffer layer 25 is formed, dehydrogenation is performed, and laser crystallization is performed to convert the amorphous silicon layer into a polysilicon layer. Crystallize. Thereafter, the polysilicon layer is patterned by performing a first mask process to form the semiconductor layer 30.

Next, as shown in FIG. 3, an inorganic insulating material is deposited on the entire surface of the substrate 20 on which the semiconductor layer 30 is formed to form the gate insulating layer 45. Subsequently, a metal material is deposited on the entire surface of the gate insulating layer 45, and then a second mask process is performed to overlap the semiconductor layer 30 to form the gate electrode 50. At this time, although not shown in the drawing, a plurality of gate wires (not shown) are formed in the display unit (not shown) on the substrate 20. Next, by using the gate electrode 50 as a mask, a high dose p + doping by ion implantation is performed on the entire surface of the substrate 20 to exclude the semiconductor layer in the region corresponding to the gate electrode 50. The p-type doped ohmic contact layer 30b is formed over the entire region. At this time, the semiconductor layer 30a which is not doped with p + by the gate electrode 50 forms the active layer 30a. Thereafter, an activation process for activating the ohmic contact layer 30b in which the p + doping is performed is performed.

Next, as shown in FIG. 4, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the semiconductor layer 30 on the substrate 20 on which the activation process is completed. The semiconductor layer contact holes 73a and 73b exposing a portion of the ohmic contact layer 30b to the outside by forming the insulating film 70 and performing a third mask process to collectively or continuously etch the interlayer insulating film and a portion of the gate insulating film below. ).

Next, as shown in FIG. 5, a metal material is deposited on the substrate 20 on which the interlayer insulating film 70 having the semiconductor layer contact holes 73a and 73b is formed, and a fourth mask process is performed to perform the fourth mask process. Source and drain electrodes 80a and 80b contacting the ohmic contact layer 30b are formed through the contact holes 73a and 73b, respectively. At this time, although not shown in the drawing, a data line (not shown) intersecting with a lower gate line (not shown) is formed on the display unit (not shown) on the substrate 20.

Next, as shown in FIG. 6, silicon nitride (SiNx), which is an inorganic insulating material, is deposited on the entire surface of the substrate 20 on which the source and drain electrodes 80a and 80b are formed, and the silicon nitride (SiNx) is deposited. After the hydrogenation heat treatment is performed, the fifth mask process is performed to form a protective layer 90 having a drain contact hole 95 exposing a portion of the drain electrode below.

Next, as illustrated in FIG. 7, a transparent conductive material is deposited on the entire surface of the substrate on which the protective layer 90 having the drain contact hole is formed, and the sixth mask process is performed to form the drain contact hole 95. By forming the pixel electrode 97 in contact with the drain electrode 90b, a PMOS type array substrate using polysilicon is completed.

However, in the manufacturing of the array substrate for a liquid crystal display device using the polysilicon described above, the manufacturing of the array substrate may be completed by performing a total of six mask processes. The mask process may include photoresist coating and photoresist coating. Since the coated photoresist is a complicated process of exposing and developing the coated photoresist, the more the masking process is performed, the more the manufacturing cost and processing time of the array substrate are increased, thereby lowering the production yield, and moreover, the mask. As the process proceeds more, the probability of generating a defect in the thin film transistor device increases.

The present invention has been made to solve the above problems, by reducing the number of process masks in the manufacturing of the array substrate for a liquid crystal display device of polysilicon, shorten the number of processes and the process time to improve the production yield and further reduce the manufacturing cost For that purpose.

In addition, another object of the present invention is to prevent defects due to misalignment of the exposure by performing different exposure methods.

In order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device using a polysilicon according to an embodiment of the present invention comprises the steps of forming a first metal layer on the front surface; Patterning the first metal layer to form a gate wiring including a gate electrode; Forming a gate insulating film and an amorphous silicon layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Crystallizing the amorphous silicon layer into a polysilicon layer by performing a crystallization process; Forming a first photoresist layer on the entire surface of the polysilicon layer, and performing back exposure using the gate electrode as a mask to form a first photoresist pattern on the polysilicon layer in a region corresponding to the gate electrode; Steps; Performing p + doping using the first photoresist pattern as a blocking mask; Forming a second metal layer on an entire surface of the doped polysilicon layer; Forming a second photoresist layer on the entire surface of the second metal layer and performing diffraction exposure to form a source and drain electrode, an ohmic contact layer and an active layer below the data line; Forming a protective layer on a front surface of the source and drain electrodes; Forming a third photoresist layer over the passivation layer, and performing a mask process to form a second photoresist pattern in regions corresponding to the source and drain electrodes; Patterning a protective layer exposed to the outside of the second photoresist pattern to expose a portion of the drain electrode and the gate insulating layer; Forming a transparent conductive film by depositing a transparent conductive material on the entire surface including the exposed gate insulating layer and a part of the drain electrode; Forming a pixel electrode connected to one end of the drain electrode by stripping and removing the second photoresist pattern under the transparent conductive layer.

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In this case, the protective layer is formed by applying an organic insulating material.

In addition, the step of crystallizing the amorphous silicon layer to a polysilicon layer is characterized in that formed by irradiating the laser beam to the amorphous silicon layer.

In addition, the first photoresist layer is characterized in that the positive type that is removed when the portion receiving the light.

The method may further include forming a buffer layer before forming the metal layer on the substrate.

In addition, forming a second photoresist layer on the entire surface over the second metal layer and performing diffraction exposure to form a source and drain electrode, an ohmic contact layer and an active layer thereunder, including a data line, may include the second metal layer. Applying a photoresist over to form the second photoresist layer on the entire surface; Positioning a mask having a transmissive region, a blocking region, and a transflective region over the second photoresist layer, and performing diffraction exposure; The exposed second photoresist layer is developed to form a third photoresist pattern having a first thickness on the upper polysilicon layer of the gate electrode corresponding to the transflective region of the mask, wherein the third photoresist pattern corresponds to the blocking region of the mask. Forming a fourth photoresist pattern having a second thickness thicker than the first thickness in a region at a predetermined interval around a third photoresist pattern of a first thickness and in a region where data wirings are to be formed; Etching and removing the second metal layer exposed below the third and fourth photoresist patterns and the polysilicon layer thereunder to form a source drain metal layer connected to a data line, an active layer and an ohmic contact layer thereunder. Making a step; Removing the third photoresist pattern to expose a portion of the source drain metal layer in the connected state; Etching the exposed source drain metal layer to expose a lower active layer, and forming source and drain electrodes spaced a predetermined distance apart; And removing a fourth photoresist pattern remaining on the source and drain electrodes.

In addition, the first metal layer or the second metal layer is characterized in that each formed of a double layer of different metal materials.

In addition, the metal material is preferably selected from aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), copper (Cu), copper alloy.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device using polysilicon according to an embodiment of the present invention will be described with reference to the drawings.

<First Embodiment>

8 to 16 illustrate cross-sectional views of a process of manufacturing an array substrate for a liquid crystal display device using polysilicon according to a first embodiment of the present invention. In particular, the drawing according to the manufacturing step is shown by cutting the thin film transistor forming portion that is the switching element in the display portion of the array substrate. Since the inverter provided in the driving circuit portion outside the display portion is also formed as a thin film transistor having the same structure, a cross-sectional view according to manufacturing steps thereof is omitted.

First, as shown in FIG. 8, one selected from silicon nitride (SiNx) or silicon oxide (SiO ₂ ), which is an inorganic insulating material, is deposited on the entire surface of the substrate 101 including the display unit and the driving circuit unit (not shown). The buffer layer 103 is formed. When the amorphous silicon layer formed on top of the buffer layer 103 is crystallized with a polysilicon layer, alkali ions, for example, potassium ions (K +), present in the substrate 101 due to heat generated by laser irradiation or the like, Sodium ions (Na +) and the like may be generated, which is formed in order to prevent the film properties of the polysilicon layer from being degraded by such alkali ions.

Next, one or two metal materials, for example, aluminum (Al), aluminum alloy (AlNd), chromium (Cr), molybdenum (Mo), copper (Cu), or copper alloy, are formed on the buffer layer 103 formed on the front surface of the substrate. The metal material is continuously deposited to form a single layer or a double layer of metal layers. As an example of a metal layer having a double layer, a structure of aluminum alloy / molybdenum, that is, a double layer metal layer made of aluminum alloy in the lower layer and molybdenum in the upper layer is formed. In the drawings, a single layer is shown for convenience.

Next, after the photoresist is formed on the entire surface of the metal layer 107 to form the photoresist layer 108, the transmission area TA for transmitting light over the photoresist layer 108 and the blocking area for blocking light ( The mask 170 having the BA is positioned so that the transmission area TA corresponds to the portion GA where the gate electrode is to be formed and the area where the gate wiring is to be formed, and the blocking area BA in the other area. Let's do it. Thereafter, an exposure process of irradiating light (UV light) onto the photoresist layer 108 formed on the substrate 101 through the mask is performed.

At this time, in the present embodiment, a negative type photoresist having a characteristic in which a region to which light is irradiated is left during development is shown. However, by changing the pattern of the mask, that is, a transmission region and a blocking region on the mask. If the pattern is changed, the same result can be obtained even if the exposure process is performed using a positive type photoresist having the opposite characteristics.

Next, as shown in FIG. 9, when the development process is performed on the photoresist layer 108 (FIG. 8) exposed through the mask (170 of FIG. 8), the blocking region (BA of FIG. 8) of the mask (170 of FIG. 8) is performed. ), The photoresist layer (108b of FIG. 8) of the portion where light is blocked is removed to expose the lower metal layer 107, and at the same time to the transmissive region (TA of FIG. 8) of the mask (170 of FIG. 8). The photoresist layer (108a in FIG. 8) of the correspondingly irradiated region, that is, the portion where the gate wiring and the gate electrode are to be formed (GA, not shown), is left without being removed by the developer and the photoresist pattern 109 is maintained. Will form.

Next, as shown in FIG. 10, a gate wiring (not shown) and a gate are formed on the buffer layer 103 by performing an etching process on the metal layer (107 of FIG. 9) exposed to the outside of the photoresist pattern (109 of FIG. 9). The electrode 113 is formed.

Here, the mask process is defined for convenience of the following description. As described above with reference to FIGS. 8 through 10, a series of processes of applying a photoresist, exposing using a mask, and developing the exposed photoresist are called a mask process, and the first mask process is performed to process the gate electrode. It describes what formed the gate wiring containing. Hereinafter, the above-described series of processes are simply referred to as a mask process.

Next, as illustrated in FIG. 11, an ashing or strip process is performed on the substrate 101 on which the gate wiring (not shown) and the gate electrode 113 are formed, thereby performing the gate wiring (not shown). ) And the photoresist pattern (109 of FIG. 10) remaining on the gate electrode 113 are removed.

Next, a gate insulating layer 118 is formed by depositing one of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), over the gate wiring (not shown) and the gate electrode 113. Subsequently, amorphous silicon (a-Si) is deposited on the gate insulating layer 118 to form an amorphous silicon layer (not shown).

Next, a polysilicon layer is formed by crystallizing an amorphous silicon layer (not shown) formed on the entire surface of the substrate 101. That is, when the amorphous silicon layer (not shown) is irradiated with a laser beam having an appropriate energy density or the like, the amorphous silicon layer (not shown) is melted, and the molten amorphous silicon layer (not shown) is recrystallized in the process of solidifying. In this case, the polysilicon layer 123 is formed. In this case, the crystallization of the amorphous silicon layer (not shown) is crystallization of the polysilicon layer 123 using an Excimer Laser Annealing (ELA) or Sequential Lateral Solidification (SLS) crystallization method using an excimer laser having a wavelength of 308 nm. desirable.

Next, as shown in FIG. 12, a photoresist is coated on the entire surface of the polysilicon layer (123 of FIG. 11) to form a photoresist layer 130. In this case, the photoresist layer 130 is characterized by using a photoresist having a positive (positive) property that has a characteristic that the light-receiving portion is removed during development.

Next, back exposure is performed on the polysilicon layer 123 to irradiate light (UV light) to the rear surface of the substrate 101 on which the photoresist layer 130 is formed. At this time, the back exposure is characterized by irradiating light (UV light) to the back surface of the substrate 101 without a mask having a transmission region and a blocking region. At this time, the light (UV light) irradiated to the rear surface of the substrate 101 is the light (UV) in the portion corresponding to the gate wiring (not shown) and the gate electrode 113 formed on the buffer layer 130 on the substrate 101. When light is blocked, the photoresist layer 130 having the upper positive characteristic is not irradiated, and light (UV light) irradiated from the rear surface is irradiated to the photoresist layer 130 in other regions.

Next, when a developing process is performed on the photoresist layer 130 on the substrate 101 subjected to the back exposure, as shown in FIG. 13, the photoresist layer (not shown) of the portion to which light (UV light) is irradiated is The photoresist layer of the portion where the light (UV light) is blocked by the lower gate wiring (not shown) and the gate electrode 113 is left to form the photoresist pattern 131 (second mask process). . In this case, it can be seen that the photoresist pattern 131 is formed only on the polysilicon layer 123 corresponding to the gate electrode 113 and the gate wiring (not shown).

Next, 10 ¹⁵ , which has a high concentration on the polysilicon layer 123 on the substrate 101, more precisely on the entire surface of the substrate 101 on which the photoresist pattern 131 is formed corresponding to the gate wiring (not shown) and the gate electrode 113. P + doping is performed by ion implantation having a dose of about / cm 2 to 9 * 10 ¹⁶ / cm 2.

At this time, the polysilicon layer 123a of the region where the photoresist pattern 131 is formed corresponding to a portion of the polysilicon layer 123 corresponding to the gate electrode 113 and the gate wiring (not shown) is formed in the photoresist pattern. Since p 131 is acted as a blocking mask and no p + doping is performed, the p dope is left as a pure poly silicon layer 123 a, and the poly silicon layer 123 b exposed to the outside of the photoresist pattern 131 is p + doped. The p-type ohmic contact layer 123b is formed.

As described above, when the photoresist pattern 131 is formed on the gate electrode 113 through the back exposure, the photoresist pattern is formed on the entire surface of the substrate 101 by using a mask to more accurately than the photoresist pattern. The photoresist pattern 131 is formed on the polysilicon layer 123a corresponding to the gate electrode 113. In other words, the mask process, which proceeds to the front surface of the substrate using the mask, is performed to align the mask so that the transparent region and the blocking region in the exposure mask are exactly matched on the substrate. However, the mask alignment in the exposure apparatus has an error range due to the characteristics of the device, and the fact that the correct mask alignment is made means that the degree of mask alignment is within the error range. . Therefore, it is impossible to form a photoresist pattern that exactly corresponds to the gate electrode. Therefore, the photoresist pattern formed at a portion corresponding to the gate electrode is shifted to the left and right sides of the gate electrode within the error range, and when p + doping is performed, the p + doped polysilicon layer on the gate electrode, that is, ohmic The contact layer is formed to be shifted left or right with respect to the lower gate wiring, thereby degrading the characteristics of the thin film transistor. In addition, when the alignment degree is out of the error range, a defect due to misalignment occurs.

However, in the first exemplary embodiment of the present invention, the back exposure is performed using the gate electrode 113 as a mask to form the photoresist pattern 131 that exactly corresponds to the gate electrode 113 to form the ohmic contact layer 123b. Deterioration of the thin film transistors due to the shift does not occur, and defects due to misalignment do not occur.

Next, as shown in FIG. 14, a strip or ashing process is performed on the photoresist pattern (131 of FIG. 13) formed on the gate wiring (not shown) and the gate electrode 113. After removal, a metal material is deposited on the entire surface of the polysilicon layer 123 to form the metal layer 140. In this case, the metal layer 140 may also be formed as a double layer by continuously depositing a metal material in a double, in the present invention is shown as being formed as a single layer for convenience.

Next, a photoresist of positive type is coated on the metal layer to form a photoresist layer 183.

Next, a mask 190 having a transmissive area TA, a blocking area BA, and a transflective area HTA is disposed on the photoresist layer 183 at a predetermined interval, and a mask alignment is performed. Conduct. In this case, the positional relationship between each region in the mask 190 and the substrate 101 will be described. The blocking region BA in the mask 190 is a portion where source and drain electrodes including data wirings are to be formed. , DA), the transflective area HTA on the mask 190 corresponds to the undoped pure polysilicon layer 123a, and the transmissive area TA corresponds to the other substrate 101 areas. The mask 190 is aligned on the substrate 101 as much as possible.

Thereafter, as described above, the photoresist layer 183 on the substrate 101 is exposed through the aligned mask 190. At this time, the diffraction exposure is characterized in that through the transflective area (HTA) on the mask 190. The diffraction exposure is a semi-transmissive region (HTA) in the mask 190 is formed of a plurality of slits having a predetermined width and a predetermined interval, the exposure method using a phenomenon that the light irradiated by the slit is diffracted to be. By adjusting the width and spacing of the slits, the amount of light passing through the semi-transmissive region HTA of the mask 190 is finally adjusted to thereby control the amount of light irradiated onto the photoresist layer 183 to form a photoresist layer having a different thickness. can do.

Therefore, when the exposure is performed through the above-described mask 190 and developed, as shown in FIG. 15, the partial region corresponding to the blocking region (BA of FIG. 14) of the mask (190 of FIG. 14), that is, data A thick photoresist pattern 184a is formed in a region corresponding to the wiring and the region where the source and drain electrodes are to be formed (not shown, SA and DA), and the semi-transmissive region of the mask 190 (FIG. 14). A thin photoresist pattern 184b is formed to correspond to the region corresponding to the HTA, that is, the region where the pure polysilicon layer 123a is formed, and the transmissive region of the other mask (190 of FIG. 14) (see FIG. 14). The photoresist layer is removed in the region corresponding to TA to expose the lower metal layer 140. (Third mask process)

Next, as shown in FIG. 16, the metal layer (140 in FIG. 15) exposed to the outside of the photoresist patterns (184a and 184b in FIG. 15) and the polysilicon layer (123 in FIG. 15) underneath are sequentially etched. And the lower gate insulating film 118 is exposed, and at the same time, the source drain metal layer 141 in a state connected to the data line (not shown) is formed.

Next, dry etching is performed on the substrate 101 on which the source drain metal layer 141 is connected to the drain wiring (not shown) to remove the thin photoresist pattern (184b of FIG. 15). A portion of the source drain metal layer 141, that is, the region corresponding to the pure polysilicon layer 123a is exposed. At this time, the thickness of the photoresist pattern 184a formed thick by the dry etching is reduced.

Next, as illustrated in FIG. 17, the exposed pure polysilicon layer 123a is exposed by etching the exposed source drain metal layer 141 of FIG. 16, and the exposed pure polysilicon layer 123a is interposed therebetween. Source and drain electrodes 145a and 145b spaced a predetermined distance apart are formed. In this case, the exposed pure polysilicon layer 123a becomes the active layer 123a forming a channel.

Next, the thin photoresist pattern (184a in FIG. 16) remaining on the data line (not shown) and the source and drain electrodes 145a and 145b is removed by stripping or ashing.

Next, as illustrated in FIG. 18, silicon oxide (SiO ₂ ) or nitride, which is an inorganic insulating material, is formed on the entire surface of the source and drain electrodes 145a and 145b, the data line (not shown), and the exposed gate insulating layer 118. A protective layer 150 is formed by depositing one selected from silicon (SiNx) on the entire surface. In this case, the protective layer 150 is formed of a single layer of silicon oxide (SiO ₂ ) or silicon nitride (SiNx), but the silicon oxide (SiO ₂ ) layer is a lower layer and the silicon nitride (SiNx) layer is an upper layer. A double layer may be formed, or a protective layer made of an organic material may be formed by applying any one of an organic insulating material, benzocyclobutene (BCB) or photo acryl. The drawing shows that a single layer protective layer 150 made of an inorganic insulating material is formed.

The above steps have described the manufacturing process of the thin film transistor in the PMOS type inverter in the switching element of the display unit in the array substrate and the driving circuit unit outside the display unit. Hereinafter, the steps of forming the switching element in the display unit and the pixel electrode connected to the element except for the inverter thin film transistor in the driving circuit unit will be described.

Next, a fourth mask process is performed on the passivation layer 150 to pattern a portion of the passivation layer 150 to form a drain contact hole 151 exposing a part of the drain electrode 145b.

Next, as shown in FIG. 19, one of the indium tin oxide (ITO) or the indium zinc oxide (IZO), which is a transparent conductive material, is disposed on the protective layer 150 on which the drain contact hole 151 is formed. The gate electrode (not shown) and the data wire (not shown) form the pixel electrode 160 in contact with the drain electrode 145b through the drain contact hole 151 by depositing the same, and then patterning by performing a fifth mask process. The array substrate is completed by forming each of the pixel regions PA formed to cross each other.

The array substrate for a liquid crystal display device using polysilicon according to the first embodiment described above was fabricated by a total of five mask processes by forming a thin film transistor having a bottom gate structure. Therefore, the manufacturing cost is reduced by omitting one mask process as compared with the conventional art.

In addition, a mask process for forming a photoresist pattern used as a p + doping blocking mask among five mask processes is performed by exposing the back surface of the substrate using a gate electrode as a mask, thereby resulting in poor exposure due to misalignment of the mask. In addition, the ohmic contact layer on the gate electrode is shifted by the alignment error, thereby preventing the thin film transistor from deteriorating.

&Lt; Embodiment 2 >

A method of manufacturing an array substrate for a liquid crystal display device using polysilicon according to a second embodiment of the present invention proposes to manufacture the array substrate through a total of four mask processes. In the case of the second embodiment, the process of forming the thin film transistor including the source and drain electrodes formed by going to the third mask process of the first embodiment is performed in the same manner, and thus the description of the above step is omitted, and the protective layer on the thin film transistor is omitted. It will be described from the forming step.

20 to 22 are cross-sectional views of manufacturing processes of an array substrate for a liquid crystal display device using polysilicon according to a second embodiment of the present invention. At this time, the figure shows a cross section of the same portion as in the first embodiment.

First, as shown in FIG. 20, an organic insulating material such as benzocyclobutene (BCB) or photo acryl is formed on the entire surface of the substrate 201 where the thin film transistor including the source and drain electrodes 245a and 245b is formed. ) To form a protective layer 250 made of an organic material. The protective layer 250 may be formed by depositing any one of silicon oxide (SiO ₂ ) and silicon nitride (SiNx), which are inorganic insulating materials other than the organic insulating material described above. However, it is preferable that the protective layer 250 is thickly formed of an organic insulating material due to the nature of a later process.

Next, a photoresist layer 267 is formed by applying a photoresist on the entire surface of the protective layer 250, and the photoresist layer is patterned by performing a fourth mask process to display the photoresist layer 267 in each pixel area PA. The protective layer 250 is exposed by forming and removing the photoresist pattern 267 corresponding to the portion TrA and each wiring (not shown) in which the thin film transistors are formed, and developing and removing the pixel region P in the other display portion. . In this case, although not shown, a photoresist pattern is formed on the entire surface of the driving circuit unit other than the display unit. In this case, the photoresist pattern 267 formed to correspond to the portion TrA in which the thin film transistors are formed in the display unit may more accurately face the source electrode 245a of the drain electrode 245b among the elements forming the lower thin film transistor. It is characterized in that a part of the other end other than one end is not formed.

Next, the gate insulating layer 118 is exposed by etching the protective layer 250 exposed to the outside of the photoresist pattern 267, including one end of the drain electrode 245b disposed under the protective layer 250. In this case, an area where the gate insulating layer 118 is exposed is an area having a smaller area than the pixel inside the pixel formed by the intersection of the gate line (not shown) and the data line (not shown).

Next, as shown in FIG. 21, a transparent conductive material such as indium tin oxide (ITO) or indium zinc may be disposed on the entire surface of the substrate 201 where the drain electrode 245b and the gate insulating layer 118 are exposed. One of oxides (IZO) is deposited on the entire surface to form transparent conductive films 255a and 255b. In this case, the transparent conductive films 255a and 255b are formed to have a thin thickness, so that the transparent conductive films 255a and 255b are hardly formed on the side of the portion having the high step or the thickness thereof is thin. In particular, since the thickness of the photoresist pattern 267 formed on the thin film transistor is generally 2 μm or more, the transparent conductive film 255 is hardly formed on the side surface of the photoresist pattern 267, and the organic insulating material As a result, the transparent conductive films 255a and 255b are hardly formed or have a very thin thickness on the side surface of the protective layer 250 having a relatively high thickness of 1 μm or more.

Next, as shown in FIG. 22, an array is formed by stripping and removing the photoresist pattern (267 of FIG. 21) remaining on the substrate 201 where the transparent conductive films (255a and 255b of FIG. 21) are formed on the entire surface. Complete the substrate. In this case, the photoresist pattern 267 of FIG. 21 is removed to simultaneously remove the transparent conductive film (255a of FIG. 21) formed on the photoresist pattern 267 of FIG. 21. Accordingly, the transparent conductive film (255b in FIG. 21) that is not removed and remains on the substrate 201 forms the pixel electrode 260, wherein the pixel electrode 260 is patterned by the protective layer 250 in the previous step. Since it is formed by being directly deposited with one end of the drain electrode 245b formed to be exposed to the outside of the protective layer 250, the photoresist pattern (267 of FIG. 21) on the protective layer 250 is removed and at the same time, a part of the transparent conductive film (FIG. 21). Although 255a) is removed, it is still in contact with one end of the drain electrode 245b exposed to the outside of the protective layer 250.

The method of removing the film using the photoresist pattern described above in FIG. 21 is called a lift-off method, which uses the characteristics of the photoresist and the thin film deposition. The photoresist is partially dissolved in the strip liquid during the strip process, but the strip liquid penetrates into the interface between the photoresist layer and the substrate or film to which the photoresist layer is adhered so that the photoresist layer is separated from the substrate or film. Thereby removing the photoresist. In addition, when a metal material is deposited on a substrate or a specific film formed on the substrate by using a sputtering apparatus, deposition is well performed on a surface parallel to the substrate, but deposition is almost performed on the side of the step in a region having a high step. There is a characteristic that does not lose.

Accordingly, in the method of manufacturing the array substrate for a liquid crystal display device using polysilicon according to the second embodiment of the present invention, the mask process is omitted one more time through the lift-off process using the photoresist and deposition characteristics described above. It has the characteristics manufactured by a total of four mask processes.

As described above, when fabricating an array substrate for a liquid crystal display device for a liquid crystal display device using polysilicon according to an embodiment of the present invention, a gate electrode is formed with a bottom gate structure, and the gate electrode is used as a mask to correspond to the gate electrode. By forming and doping the photoresist pattern on the polysilicon layer, the exposure defect due to the mask misalignment is improved, and at the same time, the doped ohmic contact layer is formed to be exactly symmetrical with respect to the gate electrode, thereby characteristic of the thin film transistor. Has the effect of improving.

In addition, by manufacturing the array substrate for a liquid crystal display using polysilicon by a total of five mask masks or four mask masks, the number of processes is reduced, thereby reducing manufacturing time and manufacturing cost.

Claims (10)

Forming a first metal layer on the front surface of the substrate; Patterning the first metal layer to form a gate wiring including a gate electrode; Forming a gate insulating film and an amorphous silicon layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Crystallizing the amorphous silicon layer into a polysilicon layer by performing a crystallization process; Forming a first photoresist layer on the entire surface of the polysilicon layer, and performing back exposure using the gate electrode as a mask to form a first photoresist pattern on the polysilicon layer in a region corresponding to the gate electrode; Steps; Performing p + doping using the first photoresist pattern as a blocking mask; Forming a second metal layer on an entire surface of the doped polysilicon layer; Forming a second photoresist layer on the entire surface of the second metal layer and performing diffraction exposure to form a source and drain electrode, an ohmic contact layer and an active layer below the data line; Forming a protective layer on a front surface of the source and drain electrodes; Forming a third photoresist layer over the passivation layer, and performing a mask process to form a second photoresist pattern in regions corresponding to the source and drain electrodes; Patterning a protective layer exposed to the outside of the second photoresist pattern to expose a portion of the drain electrode and the gate insulating layer; Forming a transparent conductive film by depositing a transparent conductive material on the entire surface including the exposed gate insulating layer and a part of the drain electrode; Forming a pixel electrode connected to one end of the drain electrode by stripping and removing the second photoresist pattern under the transparent conductive layer; Method of manufacturing an array substrate for a liquid crystal display using polysilicon comprising a. delete delete The method of claim 1, And crystallizing the amorphous silicon layer to a polysilicon layer by irradiating a laser beam to the amorphous silicon layer. The method of claim 1, And the first photoresist layer is a positive type in which light-receiving portions are removed during development. The method of claim 1, A method of manufacturing an array substrate for a liquid crystal display device using polysilicon, further comprising forming a buffer layer before forming the first metal layer on the substrate. The method of claim 1, Forming a second photoresist layer on the entire surface over the second metal layer and performing diffraction exposure to form a source and drain electrode, an ohmic contact layer and an active layer below the data line, including a data line. Applying a photoresist over the second metal layer to form the second photoresist layer on the entire surface; Positioning a mask having a transmissive region, a blocking region, and a transflective region over the second photoresist layer, and performing diffraction exposure; The exposed second photoresist layer is developed to form a third photoresist pattern having a first thickness on the upper polysilicon layer of the gate electrode corresponding to the transflective region of the mask, wherein the third photoresist pattern corresponds to the blocking region of the mask. Forming a fourth photoresist pattern having a second thickness thicker than the first thickness in a region at a predetermined interval around a third photoresist pattern of a first thickness and in a region where data wirings are to be formed; Etching and removing the second metal layer exposed below the third and fourth photoresist patterns and the polysilicon layer thereunder to form a source drain metal layer connected to a data line, an active layer and an ohmic contact layer thereunder. Making a step; Removing the third photoresist pattern to expose a portion of the source drain metal layer in the connected state; Etching the exposed source drain metal layer to expose a lower active layer, and forming source and drain electrodes spaced a predetermined distance apart; Removing a fourth photoresist pattern remaining over the source and drain electrodes A method of manufacturing an array substrate for a liquid crystal display device using polysilicon, comprising: The method of claim 1, The protective layer is a method of manufacturing an array substrate for a liquid crystal display device using a polysilicon, characterized in that formed by applying an organic insulating material. The method of claim 1, The first metal layer or the second metal layer is a method of manufacturing an array substrate for a liquid crystal display device using a polysilicon, characterized in that each formed of a double layer of a different metal material. The method of claim 9, The metal material may be selected from among aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), copper (Cu), and copper alloy. Way.

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