JPH10261663A - Semiconductor device and manufacture therefor - Google Patents
Semiconductor device and manufacture thereforInfo
- Publication number
- JPH10261663A JPH10261663A JP6577897A JP6577897A JPH10261663A JP H10261663 A JPH10261663 A JP H10261663A JP 6577897 A JP6577897 A JP 6577897A JP 6577897 A JP6577897 A JP 6577897A JP H10261663 A JPH10261663 A JP H10261663A
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- Prior art keywords
- semiconductor device
- insulating film
- pad
- layer
- wiring
- Prior art date
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- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、より詳しくは、半導体チップのパッ
ドを再配置する構造を有する半導体装置と、その半導体
装置の製造方法に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a structure for rearranging pads of a semiconductor chip and a method of manufacturing the semiconductor device.
【０００２】[0002]
【従来の技術】ＬＳＩチップは、ワイヤーボンディング
による基板への実装方法が多く用いられ、ワイヤーが接
続される電子デバイスのパッドはアルミニウムを主成分
としたもので形成されている。その他のＬＳＩチップの
実装には、いわゆるＴＡＢ方式やフリップチップ法など
が用いられ、これらは、突起電極をＬＳＩチップ上のパ
ッド又は基板上の配線に形成している点で共通してい
る。2. Description of the Related Art An LSI chip is often mounted on a substrate by wire bonding, and a pad of an electronic device to which a wire is connected is formed mainly of aluminum. For mounting other LSI chips, a so-called TAB method, a flip chip method, or the like is used. These methods are common in that projecting electrodes are formed on pads on the LSI chip or wiring on a substrate.
【０００３】以上の電子デバイスは、外部の配線との電
気的接続のためのパッドが形成されているが、そのパッ
ドの形成位置は実装方法の違いによって異なるので、パ
ッドの形成位置やレイアウトは実装方法に適した位置に
予め定めることが一般的である。つまり、同じ性能、基
本構造を有するＬＳＩチップを配線接続する場合でも、
実装方法が違うことによって別の品種のデバイスとして
別に設計にする必要がある。このことは、製品の多品種
化の原因になり、製品の管理が煩雑化し、経費が増加
し、ひいては製品の価格が高くなる。In the above electronic devices, pads for electrical connection to external wiring are formed. However, since the pads are formed at different positions depending on the mounting method, the pads are formed at different positions and layouts. It is common to predetermine a position suitable for the method. That is, even when wiring LSI chips having the same performance and basic structure,
Due to the different mounting methods, it is necessary to separately design as a device of a different type. This leads to diversification of products, which complicates product management, increases costs, and increases product prices.
【０００４】したがって、ＬＳＩチップの実装方法が異
なっても同じＬＳＩチップで賄える技術があれば、製品
の管理が簡素化され且つ経費削減に有効である。そこ
で、ＬＳＩチップのパッドを所定の位置に形成した後
に、パッド位置を再配置するという、いわゆるパッド再
配置技術が特開平2-121333号、特開平5-218042号公報に
記載されている。Therefore, if there is a technology that can be covered by the same LSI chip even if the mounting method of the LSI chip is different, product management is simplified and it is effective for cost reduction. Therefore, a so-called pad rearrangement technique in which pads of an LSI chip are formed at predetermined positions and then the pad positions are rearranged is described in JP-A-2-121333 and JP-A-5-218042.
【０００５】そのパッド再配置は、具体的にいえば、パ
ッドを露出する開口部を有する保護絶縁層の上に引出配
線を形成し、その引出配線に別なパッドを形成する技術
である。それら２つの公知例では、引出配線に多層構造
を採用しており、その層構造としてはチタン（Ti）、ニ
ッケル（Ni）、金（Au）を順に積層してなる三層構造、
或いは、チタン、銅（Cu）を順に積層してなる二層構造
が記載されている。Specifically, the pad rearrangement is a technique of forming a lead wiring on a protective insulating layer having an opening exposing a pad, and forming another pad on the lead wiring. In these two known examples, a multilayer structure is adopted for the lead wiring, and the layer structure includes a three-layer structure in which titanium (Ti), nickel (Ni), and gold (Au) are sequentially laminated.
Alternatively, a two-layer structure in which titanium and copper (Cu) are sequentially stacked is described.
【０００６】また、その他の引出配線として、チタン、
銅、ニッケルの三層構造が特開昭60-136339 号公報に記
載され、チタン、銅、チタンの三層構造が特開昭57-122
542号公報に記載され、チタン、パラジウム（Pd）、チ
タンを順に形成した三層構造が特開昭 62-183134号公報
に記載され、また、アルミニウム（Al）、バナジウム
（V)、アルミニウムの三層構造とアルミニウム、チタ
ン、アルミニウムの三層構造が特開平1 ─290232号公報
に記載されている。Further, titanium, titanium,
A three-layer structure of copper and nickel is described in JP-A-60-136339, and a three-layer structure of titanium, copper and titanium is described in JP-A-57-122.
No. 542, a three-layer structure in which titanium, palladium (Pd), and titanium are formed in this order is described in JP-A-62-183134, and a three-layer structure of aluminum (Al), vanadium (V), and aluminum is described. A layer structure and a three-layer structure of aluminum, titanium, and aluminum are described in JP-A No. 290232/1990.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、パッド
再配置を行う場合には、ほぼ必然的に能動素子領域の上
にパッドを配置せざるを得ず、パッドと外部配線を接続
する際に加えられる荷重から能動素子を保護する必要が
ある。また、複数のパッドの配置間隔を考慮して、その
配線の引出が長くなる場合があるので、配線のシート抵
抗は下げなければならない。However, when rearranging the pads, it is almost inevitable to arrange the pads on the active element region, and this is added when connecting the pads to the external wiring. There is a need to protect the active device from loads. Also, taking into account the arrangement interval of a plurality of pads, the lead out of the wiring may be long, so that the sheet resistance of the wiring must be reduced.
【０００８】しかも、パッドにバンプを接続する場合に
備えて、バンプ材料との密着性のよいパッド材料を採用
する必要がある。さらに、ＬＳＩの高集積化に伴いパッ
ド数が増加し且つ配線幅が狭くなる傾向にあるために、
配線のエレクトロマイグレーションに耐えられる配線構
造が必要になるが、例えば配線を銅、金又は銀を含む層
はマイグレーションの発生を防止できる構造にする必要
がある。In addition, it is necessary to employ a pad material having good adhesion to the bump material in preparation for connecting a bump to the pad. Further, the number of pads tends to increase and the wiring width tends to decrease with the increase in the degree of integration of the LSI.
A wiring structure that can withstand the electromigration of the wiring is required. For example, the wiring needs to have a structure that can prevent the occurrence of migration in a layer containing copper, gold, or silver.
【０００９】このような要求に対して、上記した配線構
造は、それらの要求を十分に満たしてはおらず、新たな
配線構造が必要となる。本発明の目的は、低抵抗で、能
動素子を保護し、バンプとの密着性が良好で、しかも、
エレクトロマイグレーションを防止する半導体装置又は
その製造方法を提供することにある。[0009] In response to such requirements, the above-mentioned wiring structure does not sufficiently satisfy those requirements, and a new wiring structure is required. An object of the present invention is to protect an active element with low resistance, to have good adhesion to bumps,
An object of the present invention is to provide a semiconductor device for preventing electromigration or a method for manufacturing the same.
【００１０】[0010]
【課題を解決するための手段】上記した課題は、図２、
図４(d) 又は図６(d) に例示するように、半導体基板１
に形成された半導体素子２と、前記半導体素子２を囲む
領域の上方で、導電材により形成された複数の第一のパ
ッド４と、前記第一のパッド４を覆う第一の保護絶縁膜
５と、前記第一の保護絶縁膜５に形成されて前記第一の
パッド４を露出させる複数の第一の開口部６と、前記第
一の開口部６を通して前記第一のパッド４に一端が接続
され、前記第一の開口部４に囲まれた領域に他端が配置
され、かつ銅から形成された主導体層１５と、白金属の
金属から形成され且つバンプとの密着性の良好な材料か
らなる最上層１６とを有する引出配線７と、前記引出配
線７の上面のうち前記他端の近傍部分を第二のパッド１
７として露出する第二の開口部９を有する第二の保護絶
縁膜８とを有することを特徴とする半導体装置によって
解決する。Means for Solving the Problems The above-mentioned problems are shown in FIG.
As illustrated in FIG. 4D or FIG.
Element 2, a plurality of first pads 4 formed of a conductive material above a region surrounding the semiconductor element 2, and a first protective insulating film 5 covering the first pad 4. A plurality of first openings 6 formed in the first protective insulating film 5 to expose the first pads 4; one ends of the first pads 4 are provided through the first openings 6; Connected to the main conductor layer 15 made of copper, the other end of which is arranged in a region surrounded by the first opening 4 and made of a white metal and has good adhesion to the bumps. A lead wire 7 having an uppermost layer 16 made of a material, and a portion of the upper surface of the lead wire 7 near the other end is connected to a second pad 1.
And a second protective insulating film (8) having a second opening (9) exposed as (7).
【００１１】上記した半導体装置において、図６(d) に
示すように、前記最上層１６は、前記主導体層１５の上
面及び側面の上に形成されていることを特徴とする。上
記した半導体装置において、前記最上層１６は、パラジ
ウム、プラチナ、ロジウムのような白金族元素を少なく
とも１つ含む合金から形成されていることを特徴とす
る。In the above-described semiconductor device, as shown in FIG. 6D, the uppermost layer 16 is formed on the upper surface and side surfaces of the main conductor layer 15. In the above-described semiconductor device, the uppermost layer 16 is formed of an alloy containing at least one platinum group element such as palladium, platinum, and rhodium.
【００１２】上記した半導体装置において、前記第二の
開口部９を通して前記引出配線７の前記最上層１６に接
続される導電性の突起１０を有し、前記最上層１６は該
突起１０との濡れが良い金属から構成されていることを
特徴とする。上記した半導体装置において、前記主導体
層１５の下には、前記主導体層１５及び前記第一の保護
絶縁膜５と密着性の良い下地金属層１３が形成されてい
ることを特徴とする。この場合、前記下地金属層１３
は、チタン、クロム、モリブデン、タングステン又はこ
れらいずれかの合金から形成されていることを特徴とす
る。また、前記第一の保護絶縁膜は、酸化シリコン、窒
化シリコン又はポリイミドのいずれかから形成されてい
ることを特徴とする。In the above-described semiconductor device, there is provided a conductive projection 10 connected to the uppermost layer 16 of the lead-out wiring 7 through the second opening 9, and the uppermost layer 16 wets the projection 10. Is made of a good metal. In the above-described semiconductor device, a base metal layer 13 having good adhesion to the main conductor layer 15 and the first protective insulating film 5 is formed below the main conductor layer 15. In this case, the base metal layer 13
Is characterized by being formed from titanium, chromium, molybdenum, tungsten or any alloy thereof. Further, the first protective insulating film is formed of one of silicon oxide, silicon nitride, and polyimide.
【００１３】上記した課題は、図２及び図４に例示する
ように、半導体基板１に形成された半導体素子２を囲む
領域の上方で、導電材により複数の第一のパッド４を形
成する工程と、前記第一のパッド４を覆う第一の保護絶
縁膜５を形成する工程と、前記第一のパッド４を露出さ
せる複数の第一の開口部６を前記第一の保護絶縁膜６に
形成する工程と、前記第一の開口部６を含む領域にスト
ライプ状の窓１４ａを有するレジスト１４を形成する工
程と、前記窓１４ａの中で、配線７の主導体層１５を銅
から形成する工程と、前記レジスト１４と前記主導体層
１５との間にギャップを形成する工程と、前記窓１４ａ
の中であって前記主導体層１５の上面及び側面の上に、
白金族金属からなる最上層１６を形成する工程と、前記
レジスト１４を除去する工程と、前記配線７の上面のう
ち前記他端の近傍部分を第二のパッド１７として露出す
る第二の開口部９を有する第二の保護絶縁膜８を形成す
る工程とを有することを特徴とする半導体装置の製造方
法によって解決する。The above-mentioned problem is solved by forming a plurality of first pads 4 of a conductive material above a region surrounding a semiconductor element 2 formed on a semiconductor substrate 1 as illustrated in FIGS. Forming a first protective insulating film 5 covering the first pad 4, and forming a plurality of first openings 6 exposing the first pad 4 in the first protective insulating film 6. Forming, forming a resist 14 having a striped window 14a in a region including the first opening 6, and forming a main conductor layer 15 of the wiring 7 from copper in the window 14a. Forming a gap between the resist 14 and the main conductor layer 15;
And on the upper surface and side surfaces of the main conductor layer 15,
A step of forming an uppermost layer 16 made of a platinum group metal, a step of removing the resist 14, and a second opening for exposing a portion of the upper surface of the wiring 7 near the other end as a second pad 17. Forming a second protective insulating film 8 having a second insulating film 9.
【００１４】上記した半導体装置の製造方法において、
前記ギャップは、前記レジスト１４を加熱して収縮させ
て形成されることを特徴とする。次に、本発明の作用に
ついて説明する。本発明によれば、パッド再配置される
半導体装置において、配線を構成する主導体層を銅から
形成するとともに、主導体層の上の導電性の最上層を白
金族金属よりなる硬い材料から形成し、その一部をパッ
ド領域として使用している。In the method of manufacturing a semiconductor device described above,
The gap is formed by heating and shrinking the resist. Next, the operation of the present invention will be described. According to the present invention, in a semiconductor device in which pads are rearranged, a main conductor layer forming wiring is formed from copper, and a conductive uppermost layer on the main conductor layer is formed from a hard material made of a platinum group metal. And a part thereof is used as a pad area.
【００１５】このように、パッド再配置に使用される配
線の際上層を硬度の大きな材料によって形成すると、Ｔ
ＡＢ、ワイヤボンディグの際に加えられる荷重程度によ
る配線の変形はないので、最上層のパッド領域に大きな
荷重を加えても、最上層の全体で荷重が分散されて主導
体層に加わる単位面積当たりの荷重が低減し、さらにそ
の下方にある能動素子への荷重による損傷は生じない。As described above, when the upper layer is formed of a material having a high hardness at the time of the wiring used for the pad rearrangement, the T
AB, since there is no deformation of the wiring due to the load applied during wire bonding, even if a large load is applied to the pad region of the uppermost layer, the load is dispersed throughout the entire uppermost layer and the unit area applied to the main conductor layer The hit load is reduced, and no damage is caused by the load to the active element thereunder.
【００１６】また、銅よりなる主導体層のビッカース硬
度は３０程度であり比較的柔らかいので、主導体層に加
わった荷重の衝撃をある程度吸収することができ、その
下方にある能動素子への荷重衝撃による損傷を抑えるこ
とができる。また、その最上層を、突起（バンプ）が濡
れる材料から形成することによって配線の一部をパッド
として使用する場合に突起の取付けが容易になる。Further, since the Vickers hardness of the main conductor layer made of copper is about 30 and relatively soft, the impact of the load applied to the main conductor layer can be absorbed to some extent, and the load on the active element below the main conductor layer can be absorbed. Damage due to impact can be suppressed. Further, by forming the uppermost layer from a material that wets the projections (bumps), the projections can be easily attached when a part of the wiring is used as a pad.
【００１７】さらに、そのような配線の最上層を、配線
の主導体層の上面の上に形成したので、低抵抗の主導体
層にエレクトロマイグレーションが生じにくくなり、半
導体装置の信頼性が向上する。また、主導体層の側面の
少なくとも一部を併せても最上層で覆うことにより、マ
イグレーション耐性はさらに向上する。Further, since the uppermost layer of the wiring is formed on the upper surface of the main conductor layer of the wiring, electromigration hardly occurs in the low-resistance main conductor layer, and the reliability of the semiconductor device is improved. . In addition, by covering at least a part of the side surface of the main conductor layer with the uppermost layer, migration resistance is further improved.
【００１８】[0018]
【発明の実施の形態】そこで、以下に本発明の実施形態
を図面に基づいて説明する。 （第１の実施の形態）図１(a) は、本発明の実施形態に
係る半導体装置におけるパッド再配置構造の平面、図１
(b) はそのＩ−Ｉ線断面を示し、また、図２は、図１
(b) の一部を拡大した断面を示している。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. (First Embodiment) FIG. 1A is a plan view of a pad rearrangement structure in a semiconductor device according to an embodiment of the present invention.
FIG. 2 (b) shows a cross section taken along line II of FIG.
(b) shows an enlarged cross section of a part.
【００１９】図において、シリコン、化合物半導体等の
半導体基板１の上には、半導体素子２に接続される多層
配線構造３が形成されている。また、多層配線構造３の
上には、多層配線構造３に電気的に接続される第一のパ
ッド４が間隔をおいて複数個形成され、さらに、多層配
線構造３の上には第一の保護絶縁膜５が形成されてい
る。In FIG. 1, a multilayer wiring structure 3 connected to a semiconductor element 2 is formed on a semiconductor substrate 1 made of silicon, a compound semiconductor or the like. A plurality of first pads 4 electrically connected to the multilayer wiring structure 3 are formed on the multilayer wiring structure 3 at intervals, and a first pad 4 is further formed on the multilayer wiring structure 3. A protective insulating film 5 is formed.
【００２０】第一の保護膜５には、第一のパッド４を露
出するための第一の開口部６が形成されている。また、
第一の保護絶縁膜５の上にはパッド再配置によって複数
のストライプ状の引出配線７が形成されている。その引
出配線７の一端は、第一の開口部６を通して第一のパッ
ド４に接続されている。さらに、引出配線７は、互いに
接触しなように迂回して第一の開口部６に囲まれた領域
内に引き出され、さらに、それぞれの引出配線７の他端
は異なる位置になるように配置される。The first protective film 5 has a first opening 6 for exposing the first pad 4. Also,
A plurality of striped lead wires 7 are formed on the first protective insulating film 5 by pad rearrangement. One end of the lead wiring 7 is connected to the first pad 4 through the first opening 6. Further, the lead-out wires 7 are led out into a region surrounded by the first opening 6 so as not to contact with each other, and the other ends of the respective lead-out wires 7 are arranged at different positions. Is done.
【００２１】引出配線７は第二の保護絶縁膜８によって
覆われ、その第二の保護絶縁膜８には各引出配線７の他
端近傍の上面を露出するための第二の開口部９が形成さ
れている。そして、引出配線７には、第二の開口部９を
通してバンプ（突起）１０が接続され、このバンプ１０
は第二の開口部９よりも面積が大きくなるように形成さ
れている。バンプ１０の上から見た直径を大きくするこ
とにより、バンプ１０に加わる単位面積当たりの力を低
減するようになっている。The lead wiring 7 is covered with a second protective insulating film 8, and the second protective insulating film 8 has a second opening 9 for exposing the upper surface near the other end of each lead wiring 7. Is formed. A bump (projection) 10 is connected to the lead-out wiring 7 through the second opening 9.
Is formed so as to have a larger area than the second opening 9. By increasing the diameter of the bump 10 as viewed from above, the force applied to the bump 10 per unit area is reduced.
【００２２】なお、図２において符号１１は、絶縁性シ
ート１２に形成されたリード、１３は引出配線７の第一
の金属層、１５は引出配線７の第二の金属層（主導体
層）、１６は引出配線７の第三の金属層（最上層）を示
す、１７は、第二の開口部９から露出した引出配線７の
パッド部を示している。また、図１(a) において、第二
の保護膜８は、引出配線７の平面形状を明確にするため
に省略されている。In FIG. 2, reference numeral 11 denotes a lead formed on the insulating sheet 12, 13 denotes a first metal layer of the lead-out wiring 7, and 15 denotes a second metal layer (main conductor layer) of the lead-out wiring 7. , 16 indicate a third metal layer (uppermost layer) of the extraction wiring 7, and 17 indicates a pad portion of the extraction wiring 7 exposed from the second opening 9. In FIG. 1A, the second protective film 8 is omitted to clarify the planar shape of the lead-out wiring 7.
【００２３】以上のような引出配線７、第二の保護絶縁
膜８、第二の開口部９及びバンプ１０は、以下に述べる
ような工程に沿って形成される。図２(a) 〜(d) 、図３
(a) 〜(d) は、パッド再配置の工程を示す断面図で、そ
れらの図の左側の断面は図１のII−II線に沿った断面を
示し、それらの図の右側は図１の III-III線に沿った断
面図を示している。The lead wiring 7, the second protective insulating film 8, the second opening 9 and the bump 10 as described above are formed according to the following steps. 2 (a) to 2 (d), FIG.
1A to 1D are cross-sectional views showing a step of pad rearrangement. The cross sections on the left side of these figures show cross sections taken along the line II-II in FIG. 1, and the right sides of those figures show FIG. 3 shows a cross-sectional view along the line III-III.
【００２４】まず、図３(a) に示すように、多層配線構
造３の最上部にアルミニウムよりなる複数のパッド４が
形成された半導体基板１を用意し、その多層配線構造３
の上に、Si3N4 、SiO2、ＰＳＧなどの絶縁材よりなる無
機パッシベーション膜５ａを約１μｍの膜厚に形成、そ
の上にポリイミドなどの有機パッシベーション膜５ｂを
約２μｍの膜厚に形成する。無機パッシーベーヨン５ａ
又は有機パッシベーション膜５ｂは、図１(b) 、図２の
第一の保護絶縁膜５に該当する。First, as shown in FIG. 3A, a semiconductor substrate 1 having a plurality of pads 4 made of aluminum formed on the uppermost portion of a multilayer wiring structure 3 is prepared.
An inorganic passivation film 5a made of an insulating material such as Si 3 N 4 , SiO 2 or PSG is formed to a thickness of about 1 μm, and an organic passivation film 5b made of polyimide or the like is formed to a thickness of about 2 μm. I do. Inorganic Passive Bayon 5a
Alternatively, the organic passivation film 5b corresponds to the first protective insulating film 5 in FIG. 1B and FIG.
【００２５】そして、有機パッシベーション膜５ａと無
機パッシベーション膜５ｂをパターニングしてパッド４
の上に第一の開口部６を形成する。第一の開口部６の大
きさは、例えば７０μｍ×８０μｍ程度である。この状
態では、半導体装置のパッド４は、ワイヤボンディング
法によって外部端子との接続が可能な状態となってい
る。そして、これ以降の工程がパッド再配置工程とな
る。Then, the organic passivation film 5a and the inorganic passivation film 5b are patterned to
The first opening 6 is formed on the substrate. The size of the first opening 6 is, for example, about 70 μm × 80 μm. In this state, the pads 4 of the semiconductor device can be connected to external terminals by a wire bonding method. Then, the subsequent steps are the pad rearrangement steps.
【００２６】第一の開口部６の形成の後に、図３(b) に
示すように、第一の開口部６内及び有機パッシベーショ
ン膜５ｂの上に、第一の金属層１３をスパッタリング、
蒸着等によって形成する。この第一の金属層１３の材料
は、有機パッシベーション膜５ｂ上で剥がれない金属で
あればどのようなものでもよく、単層でも多層でもよ
い。有機パッシベーション膜５ｂに密着性のよい金属と
しては、例えばチタン、クロム（Cr）、モリブデン（M
o）、タングンテン（Ｗ）、又はそれらいずれかの合金
がある。その多層膜としては、例えばCrを１５０nm〜５
００nm、Cuを３００nm〜８００nmにしたものがある。After the formation of the first opening 6, a first metal layer 13 is sputtered in the first opening 6 and on the organic passivation film 5b, as shown in FIG.
It is formed by vapor deposition or the like. The material of the first metal layer 13 may be any metal as long as it does not peel off on the organic passivation film 5b, and may be a single layer or a multilayer. Examples of the metal having good adhesion to the organic passivation film 5b include titanium, chromium (Cr), molybdenum (M
o), tungsten (W), or an alloy of any of them. As the multilayer film, for example, Cr is 150 nm to 5 nm.
Some have a thickness of 00 nm and Cu of 300 nm to 800 nm.
【００２７】この後に、図３(c) に示すように、第一の
金属層１３の上にレジスト１４を塗布した後に、レジス
トを露光、現像して図１(a) に示した引出配線７の形成
位置に窓１４ａを形成する。この場合、その窓１４ａの
うちパッド４の上に存在する部分を、有機及び無機パッ
シベーション膜５ａ，５ｂの第一の開口部６の寸法より
も大きくする必要がある。Thereafter, as shown in FIG. 3C, a resist 14 is applied on the first metal layer 13, and then the resist is exposed and developed to form the lead-out wiring 7 shown in FIG. The window 14a is formed at the formation position of. In this case, the portion of the window 14a existing on the pad 4 needs to be larger than the size of the first opening 6 of the organic and inorganic passivation films 5a and 5b.
【００２８】続いて、図３(d) に示すように、電解メッ
キ、無電解メッキ、スパッタ又は蒸着によって膜厚３０
０nm〜８００nmの第二の金属層１５を２〜４μｍの厚さ
となるように窓１４ａの中に形成する。第二の金属層１
５の材料として、例えば銅、銀、ニッケルなどの導電率
の高い材料を選択する。第二の金属層１５を銅から形成
する場合には第一の金属層１３を多層構造とし、その最
上層を銅として第二の金属層１５と第一の金属層１３の
密着性を向上させてもよい。Subsequently, as shown in FIG. 3 (d), a film having a thickness of 30 mm is formed by electrolytic plating, electroless plating, sputtering or vapor deposition.
A second metal layer 15 having a thickness of 0 nm to 800 nm is formed in the window 14a so as to have a thickness of 2 to 4 μm. Second metal layer 1
As the material of No. 5, a material having high conductivity such as copper, silver, and nickel is selected. When the second metal layer 15 is formed of copper, the first metal layer 13 has a multilayer structure, and the uppermost layer is made of copper to improve the adhesion between the second metal layer 15 and the first metal layer 13. You may.
【００２９】さらに、図４(a) に示すように、第二の金
属層１５と同じ成膜法によって、第二の金属層１５の上
に膜厚０．５〜３．０μｍの第三の金属層１６を形成す
る。第三の金属層１６の材料としては、ビッカーズ硬度
が７０よりも大きな金属材料、例えばPd、プラチナ（P
t）、ロジウム（Rh）又はそれらいずれかの１つを含む
合金を選択する。合金の材料としては、ニッケル（N
i）、コバルト（Co）、銅（Cu）、金（Au）などがあ
る。Further, as shown in FIG. 4A, a third film having a thickness of 0.5 to 3.0 μm is formed on the second metal layer 15 by the same deposition method as that for the second metal layer 15. A metal layer 16 is formed. The material of the third metal layer 16 is a metal material having a Vickers hardness of more than 70, for example, Pd, platinum (P
Select t), rhodium (Rh), or an alloy containing any one of them. Nickel (N
i), cobalt (Co), copper (Cu), gold (Au) and the like.
【００３０】この後に、溶剤によってレジスト１４を除
去すると、図４(b) に示すような状態となる。なお、第
二及び第三の金属層１５、１６をスパッタ、蒸着によっ
て形成した場合には、レジスト１５の上に成長されたそ
れらの層はリフトオフされるので、結果的に、第二及び
第三の金属層１５，１６は窓１４ａの中にだけ残ること
になり、第二の金属層１５のパターンと第三の金属層１
６のパターンは窓１４ａと同じ平面形状となる。Thereafter, when the resist 14 is removed with a solvent, the state shown in FIG. When the second and third metal layers 15 and 16 are formed by sputtering or vapor deposition, those layers grown on the resist 15 are lifted off. Metal layers 15 and 16 remain only in the window 14a, and the pattern of the second metal layer 15 and the third metal layer 1
The pattern 6 has the same planar shape as the window 14a.
【００３１】この後に、酸又はアルカリのエッチング液
を用いて、図４(c) に示すように、第二及び第三の金属
層１５，１６をマスクに使用して第一の金属層１３を除
去する。これにより第一〜第三の金属層１３，１５，１
６は同じ平面形状になり、第一〜第三の金属層１３，１
５，１６を図１、図２に示した引出配線７として使用す
る。Thereafter, as shown in FIG. 4C, the first metal layer 13 is formed by using an acid or alkali etching solution and using the second and third metal layers 15 and 16 as masks. Remove. Thereby, the first to third metal layers 13, 15, 1
6 has the same planar shape, and the first to third metal layers 13, 1
5 and 16 are used as the extraction wiring 7 shown in FIGS.
【００３２】次に、図４(d) に示すように、全体に第二
の保護絶縁膜８としてポリイミドなどの有機パッシベー
ション膜、又は窒化シリコン、酸化シリコン等の無機パ
ッシベーシン膜を引出配線７よriも厚い約４μｍの厚さ
に形成した後に、これをパターニングして引出配線７の
上に第二の開口部９を形成する。第二の開口部９は、引
出配線７上面のうちパッド４から離れた部分を露出して
おり、しかも、引出配線７の縁部を露出させない大きさ
になっている。第二の開口部９の寸法は、例えば９０μ
ｍ×９０μｍ程度の大きさとする。Next, as shown in FIG. 4D, an organic passivation film such as polyimide or an inorganic passivation film such as silicon nitride or silicon oxide is entirely formed as a second protective insulating film 8 as a lead wiring 7. After being formed to a thickness of about 4 μm, the second opening 9 is formed on the lead-out wiring 7 by patterning. The second opening 9 has a size that exposes a portion of the upper surface of the lead-out wiring 7 away from the pad 4 and does not expose the edge of the lead-out wiring 7. The size of the second opening 9 is, for example, 90 μm.
The size is about mx90 μm.
【００３３】ここで、引出配線７のうち第二の開口部９
から露出した領域を最上のパッド１７として使用する。
以上によりパッド再配置は終了するが、ＴＡＢ技術によ
って最上のパッド１７を外部のリード１１に接続する場
合には、図２に示すように、パッド１７の上にPbSn半田
よりなるバンプ１０を形成する。この場合、引出配線７
の上面は、第三の金属層１６を構成するPd、Pt、Roのい
ずれかが露出しているので、PbSn半田は引出配線７の上
面に対して濡れ性が良いことになる。即ち、バンプ１０
は引出配線７の上面と密着性がよいことになる。Here, the second opening 9 of the lead wiring 7
The region exposed from is used as the uppermost pad 17.
The pad rearrangement is completed as described above. When the uppermost pad 17 is connected to the external lead 11 by the TAB technique, the bump 10 made of PbSn solder is formed on the pad 17 as shown in FIG. . In this case, the extraction wiring 7
Since the upper surface of Pd, Pt, or Ro constituting the third metal layer 16 is exposed, the PbSn solder has good wettability with respect to the upper surface of the extraction wiring 7. That is, the bump 10
Has good adhesion to the upper surface of the extraction wiring 7.
【００３４】以上のような、パッド再配置によって最上
のパッド１７が、半導体装置の能動領域の上に位置する
ことになる。しかし、本実施形態では上記したような構
造を採用したので、第二の開口部９を通して最上のパッ
ド１７の上のバンプ１０に外部のリード１１を接続した
り、又は最上のパッド１７にワイヤ（不図示）を接続す
る際に、半導体基板への荷重がパッドに加わっても、硬
度の大きな第三の金属層１６の面積分だけ荷重が分散さ
れて、その下方への単位面積当たりの荷重を少なくして
いる。これにより、半導体基板１に形成された半導体素
子２を破壊するような荷重がかかり難くなる。By the pad rearrangement as described above, the uppermost pad 17 is located above the active region of the semiconductor device. However, in the present embodiment, since the above-described structure is adopted, the external lead 11 is connected to the bump 10 on the uppermost pad 17 through the second opening 9 or the wire ( (Not shown), even if a load on the semiconductor substrate is applied to the pad, the load is dispersed by the area of the third metal layer 16 having a large hardness, and the load per unit area below the third metal layer 16 is reduced. I have less. This makes it difficult to apply a load that breaks the semiconductor element 2 formed on the semiconductor substrate 1.
【００３５】即ち、第三の金属層１６はビッカーズ硬度
が７０以上と硬質であるためにそれ自体で変形し難くな
り、第三の金属層１６の一部に局所的に加わった荷重を
第三の金属層１６の全面積によって分散して、単位面積
当たりの荷重を小さくすることになる。その反対に、銅
のような低硬度の材料から引出配線を形成し、この引出
配線に局所的な荷重を加えると、その荷重部分の引出配
線が局所的に変形し易くなってその下の半導体素子に加
わる力が大きくなって素子破損の原因になる。銅のビッ
カーズ硬度は３０程度である。その銅により第二の金属
層１５を構成すると、第三の金属層１６によって分散さ
れた荷重は柔らかい銅によって吸収されるので、その下
方にある半導体素子２を破壊することが防止される。That is, the third metal layer 16 is hard to deform by itself because it has a Vickers hardness of 70 or more, and the load locally applied to a part of the third metal layer 16 is reduced by the third metal layer 16. And the load per unit area is reduced. Conversely, when a lead wire is formed from a low-hardness material such as copper and a local load is applied to the lead wire, the lead wire in the load portion is easily deformed locally, and a semiconductor under the lead wire is easily deformed. The force applied to the element is increased, causing element damage. The Vickers hardness of copper is about 30. When the second metal layer 15 is made of the copper, the load dispersed by the third metal layer 16 is absorbed by the soft copper, so that the semiconductor element 2 thereunder is prevented from being broken.
【００３６】また、第三の金属層１６は、PbSn半田より
なるバンプ１１が濡れる材料から形成されるのでバンプ
１１との密着性が良好になり、ＴＡＢに最適である。一
方、本実施形態の引出配線７の第二の金属層１５は、導
電率の高い銅、銀、ニッケルなどによって形成している
ので、引出配線７の抵抗は低く、パッド再配置によって
半導体装置の回路特性を損ねることはない。Further, since the third metal layer 16 is formed of a material that wets the bump 11 made of PbSn solder, the third metal layer 16 has good adhesion to the bump 11 and is optimal for TAB. On the other hand, since the second metal layer 15 of the lead-out wiring 7 of the present embodiment is formed of copper, silver, nickel, or the like having high conductivity, the resistance of the lead-out wiring 7 is low, and the rearrangement of the pad causes the semiconductor device of the semiconductor device to have low resistance. There is no loss of circuit characteristics.
【００３７】ところで、上記した説明では第二及び第三
の金属層１５，１６のパターンをマスクに使用して第一
の金属パターン１３をエッチングすることによって、第
一の金属パターン１３をパターニングするようにしてい
る。しかし、図５(a) に示すように、第二の金属層１５
を形成する前に、第一の金属層１３を予めパターニグし
ておいてもよい。この場合には、第一の金属層１３は電
解メッキの電極として機能しなくなるので、第二及び第
三の金属層１５，１６の形成には無電解メッキ、スパッ
タ又は蒸着法を用いる。In the above description, the first metal pattern 13 is patterned by etching the first metal pattern 13 using the patterns of the second and third metal layers 15 and 16 as a mask. I have to. However, as shown in FIG.
Before forming the first metal layer 13, the first metal layer 13 may be patterned in advance. In this case, since the first metal layer 13 does not function as an electrode for electrolytic plating, the second and third metal layers 15 and 16 are formed by electroless plating, sputtering or vapor deposition.
【００３８】その第一の金属層１３のパターニング後に
は、図５(b) に示すように、レジスト１４を塗布し、こ
れを露光、現像することによって第一の金属層１３のほ
ぼ全体を露出する窓１４ｂを形成する。その後に、図３
(d) 、図４(a) 〜図４(d) に示すような工程を経て図５
(c) に示すように第二の保護絶縁膜８を形成することに
なる。After the patterning of the first metal layer 13, as shown in FIG. 5 (b), a resist 14 is applied, and is exposed and developed to expose almost the entire first metal layer 13. The window 14b is formed. Then, FIG.
(d), through the steps shown in FIGS. 4 (a) to 4 (d), FIG.
As shown in (c), a second protective insulating film 8 is formed.
【００３９】なお、無機パッシベーション膜５ａ又は有
機パッシベーション膜５ｂのいずれか１つは省略しても
よい。 （第２の実施の形態）第１の実施の形態では、図３(c)
に示すように、レジスト１４の窓１４ａの側面を第一の
保護絶縁膜５の上面に対してほぼ垂直の状態にしてい
る。このためその窓１４ａの中に形成される第三の金属
層１６と第二の金属層１５の平面形状は実質的に同じに
なっている。Note that one of the inorganic passivation film 5a and the organic passivation film 5b may be omitted. (Second Embodiment) In the first embodiment, FIG.
As shown in FIG. 5, the side surface of the window 14a of the resist 14 is substantially perpendicular to the upper surface of the first protective insulating film 5. Therefore, the planar shapes of the third metal layer 16 and the second metal layer 15 formed in the window 14a are substantially the same.
【００４０】このような構造を変更して、第二の金属層
のマイグレーション耐性をさらに高めるためには次のよ
うなパッド再配置の工程を採用する。まず、図３(d) に
示すと同様にして、レジスト１４の窓１４ａを形成し、
その窓１４ａの中に電解メッキ、又は無電解メッキによ
って第二の金属層１５を形成する。In order to further improve the migration resistance of the second metal layer by changing such a structure, the following pad rearrangement step is employed. First, a window 14a of the resist 14 is formed in the same manner as shown in FIG.
A second metal layer 15 is formed in the window 14a by electrolytic plating or electroless plating.
【００４１】その後に、図６(a) に示すように、レジス
ト１４の窓１４ａの側壁と第二の金属層１５の側面の間
に最大で２μｍ程度のギャップｇが生じるような処理を
行う。例えば、第二の金属層１５をメッキによって形成
した後に、レジスト１４を１５０℃で加熱すると、レジ
スト１４は収縮して第二の金属層１５との間にギャップ
ｇが形成される。Thereafter, as shown in FIG. 6A, a process is performed so as to produce a gap g of about 2 μm at maximum between the side wall of the window 14a of the resist 14 and the side surface of the second metal layer 15. For example, if the resist 14 is heated at 150 ° C. after the second metal layer 15 is formed by plating, the resist 14 shrinks to form a gap g between the resist 14 and the second metal layer 15.
【００４２】この後に、図６(b) に示すように、電解メ
ッキ、無電解メッキ、スパッタリング又は蒸着によって
第二の金属層１５の上に第三の金属層１６を形成すると
ともに、レジスト１４と第二の金属層１５の間のギャッ
プｇまで第三の金属層１６を拡張成する。この結果、第
二の金属層１５のパターンは、高硬度の第三の金属層１
６により上面だけでなくその側面も覆われることにな
る。Thereafter, as shown in FIG. 6B, a third metal layer 16 is formed on the second metal layer 15 by electrolytic plating, electroless plating, sputtering or vapor deposition, and the resist 14 The third metal layer 16 is extended to the gap g between the second metal layers 15. As a result, the pattern of the second metal layer 15 is the third metal layer 1 having high hardness.
6, not only the upper surface but also the side surfaces are covered.
【００４３】そのような第三の金属層１６の形成を終え
た後に、第１の実施の形態で説明した工程を経て、レジ
スト１４を剥離し、第一の金属層１３をパターニングす
ると図６(c) に示すような引出配線７Ａの構造が得られ
る。その後に、第６(d) に示すように、第二の保護絶縁
膜８を形成し、第二の開口部９を形成する。After the formation of the third metal layer 16 is completed, the resist 14 is peeled off through the steps described in the first embodiment, and the first metal layer 13 is patterned. The structure of the extraction wiring 7A as shown in c) is obtained. Thereafter, as shown in FIG. 6D, a second protective insulating film 8 is formed, and a second opening 9 is formed.
【００４４】以上のように、導電率の高い、ビッカース
硬度が３０程度の比較的柔らかい金属材料により形成さ
れた第二の金属層１５の上面及び側面が、高硬度の第三
の金属層１６により接合して覆われることにより、エレ
クトロマイグレーション、ストレスマイグレーションが
生じにくくなる。例えば、図４(d) に示す構造の引出配
線では、プレッシャークッカー（ＰＣＴ）試験において
引出配線間のギャップが６μｍ程度の場合にエレクトロ
マイグレーションによる配線ショートが生じる場合がま
れにあった。これに対して図６(d) に示す構造の引出配
線では、同じＰＣＴ試験において引出配線間のギャップ
が６μｍ以下の場合にマイグレーションによる配線ショ
ートが全く生じなかった。As described above, the upper surface and the side surfaces of the second metal layer 15 made of a relatively soft metal material having a high conductivity and a Vickers hardness of about 30 are formed by the third metal layer 16 having a high hardness. By being joined and covered, electromigration and stress migration hardly occur. For example, in the case of the lead wiring having the structure shown in FIG. 4D, a short circuit due to electromigration rarely occurs when the gap between the lead wirings is about 6 μm in a pressure cooker (PCT) test. On the other hand, in the lead wiring having the structure shown in FIG. 6 (d), no wiring short circuit occurred due to migration when the gap between the lead wirings was 6 μm or less in the same PCT test.
【００４５】ＰＣＴ試験に使用した試料の引出配線７
は、第一の金属層１３をクロムから形成し、第二の金属
層１５を膜厚２μｍの銅から形成し、第三の金属層１６
を膜厚０．５μｍのパラジウムから形成し、第二の保護
絶縁膜８としてポリイミドを用いたものである。したが
って、図６(a) 〜(d) に示すような工程を経て得られた
引出配線７Ａは低抵抗で、マイグレーションに強く、外
部配線の際の加重から半導体素子を保護し、しかも、半
田との密着性もよくなり、半導体装置の信頼性が向上す
る。Extraction wiring of sample used for PCT test 7
The first metal layer 13 is formed of chromium, the second metal layer 15 is formed of copper having a thickness of 2 μm, and the third metal layer 16 is formed of chromium.
Is formed from palladium having a thickness of 0.5 μm, and polyimide is used as the second protective insulating film 8. Therefore, the lead wiring 7A obtained through the steps shown in FIGS. 6A to 6D has a low resistance, is resistant to migration, protects the semiconductor element from the load in the case of the external wiring, and furthermore, has a good connection with the solder. And the reliability of the semiconductor device is improved.
【００４６】[0046]
【発明の効果】以上述べたように本発明によれば、パッ
ド再配置に使用される配線の際上層を硬度の大きな材料
によって形成したので、ＴＡＢ、ワイヤボンディグの際
に加えられる荷重程度による配線の変形はないので、最
上層のパッド領域に大きな荷重が加わっても、最上層全
体によって荷重が分散されて主導体層に加わる単位面積
当たりの荷重を低減し、さらにその下方にある能動素子
への荷重による損傷を防止できる。As described above, according to the present invention, since the upper layer is formed of a material having a high hardness in the wiring used for the rearrangement of the pads, it depends on the degree of the load applied during TAB and wire bonding. Since there is no deformation of the wiring, even if a large load is applied to the pad area of the uppermost layer, the load is dispersed by the entire uppermost layer to reduce the load per unit area applied to the main conductor layer, and furthermore, the active element below Can be prevented from being damaged by the load on the
【００４７】また、銅よりなる主導体層は比較的柔らか
いので、主導体層に加わった荷重の衝撃をある程度吸収
することができ、その下方にある能動素子への荷重衝撃
による損傷を抑えることができる。また、その最上層
を、突起が濡れる材料から形成することによって配線の
一部をパッドとして使用する場合に突起の取付けが容易
になる。Further, since the main conductor layer made of copper is relatively soft, the impact of the load applied to the main conductor layer can be absorbed to some extent, and the damage to the active element below it by the load impact can be suppressed. it can. Also, by forming the uppermost layer from a material that wets the projection, the projection can be easily attached when a part of the wiring is used as a pad.
【００４８】さらに、そのような配線の最上層を、配線
の主導体層の上面及び側面の上に形成するようにしたの
で、低抵抗の主導体層にマイグレーションが生じにくく
なり、半導体装置の信頼性を向上できる。Further, since the uppermost layer of the wiring is formed on the upper surface and side surfaces of the main conductor layer of the wiring, migration is less likely to occur in the low-resistance main conductor layer, and the reliability of the semiconductor device is reduced. Performance can be improved.
【図１】図１(a) は、本発明の半導体装置の最上の絶縁
膜を除いた状態を示す平面図であり、図１(b) は、図１
(a) のＩ−Ｉ線断面図である。FIG. 1 (a) is a plan view showing a state in which an uppermost insulating film of a semiconductor device of the present invention has been removed, and FIG.
FIG. 3A is a cross-sectional view taken along line II of FIG.
【図２】図２は、図１(b) の一部を拡大した断面図であ
る。FIG. 2 is an enlarged sectional view of a part of FIG. 1 (b).
【図３】図３(a) 〜(d) は、本発明の第１実施形態に係
るパッド再配置工程を示す断面図（その１）である。FIGS. 3A to 3D are cross-sectional views (part 1) illustrating a pad rearrangement step according to the first embodiment of the present invention.
【図４】図４(a) 〜(d) は、本発明の第１実施形態に係
るパッド再配置工程を示す断面図（その２）である。FIGS. 4A to 4D are cross-sectional views (part 2) illustrating a pad rearrangement step according to the first embodiment of the present invention.
【図５】図５(a) 〜(c) は、本発明の第１実施形態に係
るパッド再配置工程の変形例を示す断面図である。FIGS. 5A to 5C are cross-sectional views showing a modification of the pad rearrangement step according to the first embodiment of the present invention.
【図６】図６(a) 〜(d) は、本発明の第２実施形態に係
るパッド再配置工程を示す断面図である。FIGS. 6A to 6D are cross-sectional views showing a pad rearrangement step according to a second embodiment of the present invention.
１ 半導体基板 ２ 半導体素子 ３ 多層配線構造 ４ パッド ５ 第一の保護絶縁膜 ６ 第一の開口部 ７ 引出配線 ８ 第二の保護膜 ９ 第二の開口部 １０ バンプ １１ リード １３ 第一の金属層 １４ レジスト １５ 第二の金属層 １６ 第三の金属層 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor element 3 Multilayer wiring structure 4 Pad 5 First protective insulating film 6 First opening 7 Lead-out wiring 8 Second protective film 9 Second opening 10 Bump 11 Lead 13 First metal layer 14 resist 15 second metal layer 16 third metal layer
Claims (9)
された複数の第一のパッドと、 前記第一のパッドを覆う第一の保護絶縁膜と、 前記第一の保護絶縁膜に形成されて前記第一のパッドを
露出させる複数の第一の開口部と、 前記第一の開口部を通して前記第一のパッドに一端が接
続され、前記第一の開口部に囲まれた領域に他端が配置
され、かつ銅から形成された主導体層と、白金族の金属
から形成された最上層とを有する引出配線と、 前記引出配線の上面のうち前記他端の近傍部分を第二の
パッドとして露出する第二の開口部を有する第二の保護
絶縁膜とを有することを特徴とする半導体装置。A semiconductor device formed on a semiconductor substrate; a plurality of first pads formed of a conductive material above a region surrounding the semiconductor device; and a first protection covering the first pad. An insulating film; a plurality of first openings formed in the first protective insulating film to expose the first pad; one end is connected to the first pad through the first opening; The other end is arranged in a region surrounded by the first opening, and a lead wire having a main conductor layer formed of copper and an uppermost layer formed of a platinum group metal, And a second protective insulating film having a second opening exposing a portion of the upper surface near the other end as a second pad.
面の上に形成されていることを特徴とする請求項１記載
の半導体装置。2. The semiconductor device according to claim 1, wherein said uppermost layer is formed on an upper surface and side surfaces of said main conductor layer.
ジウムを少なくとも１つ含む合金から形成されているこ
とを特徴とする請求項１又は２記載の半導体装置。3. The semiconductor device according to claim 1, wherein said uppermost layer is formed of an alloy containing at least one of palladium, platinum, and rhodium.
前記最上層に接続される導電性の突起を有し、前記最上
層は該突起との濡れが良い金属から構成されていること
を特徴とする請求項１又は２記載の半導体装置。4. The semiconductor device according to claim 1, further comprising a conductive protrusion connected to said uppermost layer of said lead-out wiring through said second opening, said uppermost layer being made of a metal having good wettability with said protrusion. 3. The semiconductor device according to claim 1, wherein:
前記第一の保護絶縁膜と密着性の良い下地金属層が形成
されていることを特徴とする請求項１又は２記載の半導
体装置。5. A base metal layer having good adhesion to said main conductor layer and said first protective insulating film is formed under said main conductor layer. Semiconductor device.
ブデン、タングステン又はこれらいずれかの合金から形
成されていることを特徴とする請求項５記載の半導体装
置。6. The semiconductor device according to claim 5, wherein said base metal layer is made of titanium, chromium, molybdenum, tungsten, or any alloy thereof.
窒化シリコン又はポリイミドのいずれかから形成されて
いることを特徴とする請求項１又は２記載の半導体装
置。7. The first protective insulating film comprises silicon oxide,
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed of one of silicon nitride and polyimide.
領域の上方で、導電材により複数の第一のパッドを形成
する工程と、 前記第一のパッドを覆う第一の保護絶縁膜を形成する工
程と、 前記第一のパッドを露出させる複数の第一の開口部を前
記第一の保護絶縁膜に形成する工程と、 前記第一の開口部を含む領域にストライプ状の窓を有す
るレジストを形成する工程と、 前記窓の中で、配線の主導体層を銅から形成する工程
と、 前記レジストと前記主導体層との間にギャップを形成す
る工程と、 前記窓の中であって前記主導体層の上面及び側面の上
に、白金族の金属を含む金属材料からなる最上層を形成
する工程と、 前記レジストを除去する工程と、 前記配線の上面のうち前記他端の近傍部分を第二のパッ
ドとして露出する第二の開口部を有する第二の保護絶縁
膜を形成する工程とを有することを特徴とする半導体装
置の製造方法。8. A step of forming a plurality of first pads with a conductive material above a region surrounding a semiconductor element formed on a semiconductor substrate; and forming a first protective insulating film covering the first pads. Forming a plurality of first openings exposing the first pad in the first protective insulating film; and a resist having a stripe-shaped window in a region including the first opening. Forming a main conductor layer of wiring from copper in the window; forming a gap between the resist and the main conductor layer; and forming a gap between the resist and the main conductor layer in the window. A step of forming an uppermost layer made of a metal material containing a platinum group metal on the upper surface and side surfaces of the main conductor layer; a step of removing the resist; and a portion of the upper surface of the wiring near the other end The second opening exposing the second pad The method of manufacturing a semiconductor device characterized by a step of forming a second protective insulating film having.
収縮させて形成されることを特徴とする請求項８記載の
半導体装置の製造方法。9. The method according to claim 8, wherein the gap is formed by heating and shrinking the resist.
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| JP6577897A JP3481415B2 (en) | 1997-03-19 | 1997-03-19 | Semiconductor device and manufacturing method thereof |
| US08/999,115 US5969424A (en) | 1997-03-19 | 1997-12-29 | Semiconductor device with pad structure |
| US09/365,413 US6232147B1 (en) | 1997-03-19 | 1999-08-02 | Method for manufacturing semiconductor device with pad structure |
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| JP6577897A JP3481415B2 (en) | 1997-03-19 | 1997-03-19 | Semiconductor device and manufacturing method thereof |
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|---|---|
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005038979A (en) * | 2003-07-18 | 2005-02-10 | Casio Comput Co Ltd | Manufacturing method of semiconductor device |
| KR100567225B1 (en) * | 2001-07-10 | 2006-04-04 | 삼성전자주식회사 | Integrated Circuit chip and manufacturing method thereof and multi chip package |
| US7091616B2 (en) | 2001-08-01 | 2006-08-15 | Sharp Kabushiki Kaisha | Semiconductor device having a leading wiring layer |
| JP2006344850A (en) * | 2005-06-10 | 2006-12-21 | Murata Mfg Co Ltd | Electronic component |
| US7545037B2 (en) | 2005-03-18 | 2009-06-09 | Samsung Electronics Co., Ltd. | Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same |
| JP2010251687A (en) * | 2009-03-26 | 2010-11-04 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2012160595A (en) * | 2011-02-01 | 2012-08-23 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| WO2015097979A1 (en) * | 2013-12-27 | 2015-07-02 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| JP2015220347A (en) * | 2014-05-19 | 2015-12-07 | サンケン電気株式会社 | Semiconductor device |
| JP2020516050A (en) * | 2017-01-19 | 2020-05-28 | 日本テキサス・インスツルメンツ合同会社 | Sacrificial layer for platinum patterning |
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1997
- 1997-03-19 JP JP6577897A patent/JP3481415B2/en not_active Expired - Lifetime
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567225B1 (en) * | 2001-07-10 | 2006-04-04 | 삼성전자주식회사 | Integrated Circuit chip and manufacturing method thereof and multi chip package |
| US7091616B2 (en) | 2001-08-01 | 2006-08-15 | Sharp Kabushiki Kaisha | Semiconductor device having a leading wiring layer |
| US7445958B2 (en) | 2001-08-01 | 2008-11-04 | Sharp Kabushiki Kaisha | Semiconductor device having a leading wiring layer |
| JP4686962B2 (en) * | 2003-07-18 | 2011-05-25 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| JP2005038979A (en) * | 2003-07-18 | 2005-02-10 | Casio Comput Co Ltd | Manufacturing method of semiconductor device |
| US8643178B2 (en) | 2005-03-18 | 2014-02-04 | Samsung Electronics Co., Ltd. | Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same |
| US7545037B2 (en) | 2005-03-18 | 2009-06-09 | Samsung Electronics Co., Ltd. | Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same |
| US8410611B2 (en) | 2005-03-18 | 2013-04-02 | Samsung Electronics Co., Ltd. | Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same |
| JP2006344850A (en) * | 2005-06-10 | 2006-12-21 | Murata Mfg Co Ltd | Electronic component |
| JP2010251687A (en) * | 2009-03-26 | 2010-11-04 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2012160595A (en) * | 2011-02-01 | 2012-08-23 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| WO2015097979A1 (en) * | 2013-12-27 | 2015-07-02 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| JPWO2015097979A1 (en) * | 2013-12-27 | 2017-03-23 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| US9673139B2 (en) | 2013-12-27 | 2017-06-06 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
| JP2015220347A (en) * | 2014-05-19 | 2015-12-07 | サンケン電気株式会社 | Semiconductor device |
| JP2020516050A (en) * | 2017-01-19 | 2020-05-28 | 日本テキサス・インスツルメンツ合同会社 | Sacrificial layer for platinum patterning |
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| Publication number | Publication date |
|---|---|
| JP3481415B2 (en) | 2003-12-22 |
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