TWI672781B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI672781B
TWI672781B TW105117628A TW105117628A TWI672781B TW I672781 B TWI672781 B TW I672781B TW 105117628 A TW105117628 A TW 105117628A TW 105117628 A TW105117628 A TW 105117628A TW I672781 B TWI672781 B TW I672781B
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bonding pad
passivation film
wiring layer
semiconductor device
film
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TW201705411A (zh
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島崎洸一
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日商艾普凌科有限公司
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract

在接合墊(301)的周圍隔著空隙(601)來配置配線層(303)，鈍化膜(401)是比形成接合墊(301)的配線層(303)的膜厚薄，空隙(601)的寬是設為鈍化膜厚的2倍以下，提供一種鈍化膜比配線層薄，對於接合時的壓力耐性高的半導體裝置。

Description

半導體裝置
本發明是有關具備接合墊的半導體裝置。
以往的半導體裝置的接合墊周邊的構造是如圖6所示般，在半導體基板101上設置絕緣膜201，在絕緣膜201上藉由最上層的配線層來形成接合墊301，在接合墊301的周邊隔著空隙來設置虛擬配線302。設有用以保護半導體裝置的鈍化膜401，鈍化膜401是具有接合墊301的膜厚以上的膜厚。成為以能夠將接合線連接至接合墊301的方式，在接合墊301上設有用以使接合墊301的表面露出的開口部501之構造(例如參照專利文獻1)。
為了防止因打線接合時的壓力或熱應力而在鈍化膜中產生龜裂，藉由提高接合墊的周邊的鈍化膜的強度，可抑制鈍化龜裂為人所知。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開平5-226339號公報
然而，當鈍化膜的膜厚比接合墊的膜厚薄時，鈍化膜的強度降低，會有因打線接合或熱應力而產生鈍化龜裂的情形。
本發明是有鑑於上述不良情況，而以提供一種即使是鈍化膜比接合墊膜厚薄的情況，照樣接合時的壓力或熱應力耐性高之半導體裝置為課題。
本發明為了解決上述課題，其半導體裝置的特徵為：在接合墊的周邊隔著空隙配置配線層，鈍化膜是比形成前述接合墊的配線層的膜厚薄，前述空隙的寬是前述鈍化膜厚以上且前述鈍化膜厚的2倍以下，被充填於前述鈍化膜堆積後的前述空隙的部分的前述鈍化膜厚是形成比前述接合墊上部的部分的鈍化膜厚。
本發明是使接合墊側壁部分的鈍化膜形成比堆積於接合墊的上部的鈍化膜還厚，藉此接合時的壓力耐性會變高。
101‧‧‧半導體基板
201‧‧‧絕緣膜
301‧‧‧接合墊
302‧‧‧虛擬配線
303‧‧‧最上層的配線層
401‧‧‧鈍化膜
501‧‧‧開口部
601‧‧‧配線層之間的空隙
701‧‧‧設在鈍化膜的縫隙
圖1是表示本發明的半導體裝置的第1實施形態的剖面圖。
圖2是表示本發明的半導體裝置的第2實施形態的剖面圖。
圖3是表示本發明的半導體裝置的第3實施形態的剖面圖。
圖4是表示本發明的半導體裝置的第4實施形態的平面圖。
圖5是表示本發明的半導體裝置的第5實施形態的平面圖。
圖6是以往的半導體裝置的接合墊的剖面圖。
以下，參照圖1來說明有關本發明的半導體裝置的第1實施形態。
如圖1所示般，第1實施形態之接合墊及其周邊是成為具有：設在半導體基板101的表面的絕緣膜201、及形成於絕緣膜201上的接合墊301、及在接合墊301的周圍隔著空隙601來配置的最上層的配線層303、及被設置在接合墊301與配線層303上之用以保護半導體基板101的鈍化膜401、及為了連接接合線而使接合墊301露出的開口部501之構造。
最上層的配線層303是亦可沿著接合墊301的一邊來部分地配置1列，或包圍接合墊301的周圍一層而配置。 圖1是表示沿著接合墊301的對向的2邊來分別配置最上層的配線層303之狀態。
在此，最上層的配線層303及接合墊301的厚度是比最上層的配線層上的鈍化膜401的縱方向厚度厚為特徵，接合墊301與最上層的配線層303的空隙601的寬是最上層的配線層上的鈍化膜401的縱方向的厚度以上，為該鈍化膜之被堆積於由最上層的配線層303所成的孤立的圖案的側壁之部分的厚度的側壁厚的2倍以下。藉由設為如此的設定，在接合墊301與最上層的配線層的空隙601埋入鈍化膜401，覆蓋接合墊301的側壁之部分的鈍化膜401的厚度是藉由配置有最上層的配線層303，形成比接合墊301的上部的部分的鈍化膜401厚。而且，覆蓋接合墊301的側壁之部分的鈍化膜401的縱方向的厚度是成為比接合墊301的縱方向的厚度更厚。
另外，即使在絕緣膜201內含有其他的配線層也無妨。並且，最上層的配線層的電位即使與接合墊301同電位，或不同的電位，或浮遊電位也無妨。
又，一般接合墊301是包含正方形的矩形，但即使為其他的形狀也無妨。而且，即使在鈍化膜401上更堆積有聚醯亞胺等的樹脂也無妨。
打線接合在接合墊301上進行時，接合墊301變形，從接合墊301的側壁施加將鈍化膜401推入的壓力於水平方向，但由於覆蓋接合墊301的側壁之部分的鈍化膜401的膜厚厚，因此接合時的壓力耐性高，可抑制鈍化膜401 的龜裂發生。又，由於覆蓋接合墊的側壁之部分的鈍化膜的高度一樣，因此在鈍化膜的上部容易被破壞的以往缺點也可解消。
圖2是表示本發明的第2實施形態的半導體裝置的剖面圖。第1實施形態是將最上層的配線層303鄰接於接合墊301而配置成1列或1層。相對的，第2實施形態是將最上層的配線層303至少設置2列或2層以上。藉由如此形成，覆蓋接合墊301的側壁之部分的鈍化膜401及最上層的配線層303的橫方向的厚度是形成比第一實施形態更厚，可更有效地抑制鈍化膜401的龜裂發生。
圖3是表示本發明的第3實施形態的半導體裝置的剖面圖。在第1實施形態中，最上層的配線層303上的鈍化膜401是未被分斷，覆蓋最上層的配線層303。相對於此，第3實施形態是在最上層的配線層303上的一部分，鈍化膜401會藉由縫隙701而被分斷。亦即，在與接合墊不同的配線層303上設有鈍化膜401被除去的領域之縫隙。由於分斷鈍化膜401的領域之縫隙會緩和變形的壓力，因此在本構造中亦可與第一實施形態同樣抑制鈍化膜401的龜裂發生。
圖4是表示本發明的第4實施形態的半導體裝置的平面圖。在接合墊301的周圍是隔著空隙601來設置的最上層的配線層303不為1層被分斷的情形，為被配置成環狀。可抑制鈍化膜401的龜裂發生。
圖5是本發明的第5實施形態的半導體裝置的平面 圖。在接合墊301的周圍是隔著空隙601而設置的最上層的配線層303為1層分斷設置。即使最上層的配線層303被分斷，還是可抑制鈍化膜401的龜裂發生。
藉由圖1~圖5所示的實施形態的組合而形成的半導體裝置也可同樣抑制鈍化膜401的龜裂發生。

Claims (3)

  1. 一種半導體裝置，其特徵係具有：半導體基板；絕緣膜，其係設在前述半導體基板的表面；接合墊，其係設在前述絕緣膜上；鈍化膜，其係覆蓋前述接合墊，膜厚比前述接合墊的膜厚更薄；及最上層的配線層，其係隔著空隙來環狀地配置於前述接合墊的周圍，前述空隙的寬為前述鈍化膜的膜厚以上，前述鈍化膜的側壁厚的2倍以下，在被配置於前述接合墊的周圍的最上層的配線層上設有前述鈍化膜被部分地除去的縫隙。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述最上層的配線層係2層以上被配置於前述接合墊的周圍。
  3. 如申請專利範圍第1或2項之半導體裝置，其中，被充填於前述空隙的部分的鈍化膜的縱方向膜厚比前述接合墊上的部分的鈍化膜的縱方向膜厚還厚。
TW105117628A 2015-06-30 2016-06-03 半導體裝置 TWI672781B (zh)

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CN109422234B (zh) * 2017-09-01 2021-04-09 中芯国际集成电路制造(上海)有限公司 测试结构及其制造方法
JP2019152625A (ja) * 2018-03-06 2019-09-12 株式会社デンソー 電子装置
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