JP6571414B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6571414B2 JP6571414B2 JP2015131484A JP2015131484A JP6571414B2 JP 6571414 B2 JP6571414 B2 JP 6571414B2 JP 2015131484 A JP2015131484 A JP 2015131484A JP 2015131484 A JP2015131484 A JP 2015131484A JP 6571414 B2 JP6571414 B2 JP 6571414B2
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- Prior art keywords
- bonding pad
- passivation film
- wiring layer
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000002161 passivation Methods 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011800 void material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 27
- 230000035882 stress Effects 0.000 description 5
- 239000002356 single layer Substances 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29006—Layer connector larger than the underlying bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29012—Shape in top view
- H01L2224/29013—Shape in top view being rectangular or square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
図1に示すように、第1の実施形態によるボンディングパッドとその周辺は、半導体基板101の表面に設けられた絶縁膜201と、絶縁膜201上に形成されたボンディングパッド301と、ボンディングパッド301の脇の空隙601を介して配置された最上層の配線層303と、ボンディングパッド301と配線層303上に設置された半導体基板101を保護するためのパッシベーション膜401と、ボンディングワイヤを接続するためにボンディングパッド301を露出させている開口部501とを有する構造となっている。
図1から図5に示した実施形態の組み合わせによって形成される半導体装置も、同様にパッシベーション膜401のクラック発生を抑制することができる。
201 絶縁膜
301 ボンディングパッド
302 ダミー配線
303 最上層の配線層
401 パッシベーション膜
501 開口部
601 配線層の間の空隙
701 パッシベーション膜に設けられたスリット
Claims (3)
- 半導体基板の表面に設けられた絶縁膜の上に設けられたボンディングパッドを覆うパッシベーション膜の膜厚が前記ボンディングパッドの膜厚よりも薄い半導体装置であって、前記ボンディングパッドの周囲に空隙を介して最上層の配線層が配置され、前記空隙の幅が、前記パッシベーション膜の膜厚以上であり前記パッシベーション膜の側壁厚の2倍以下であり、前記最上層の配線層が前記ボンディングパッドの周囲に環状に配置され、前記最上層の配線層の上に前記パッシベーション膜が除去されたスリットが前記ボンディングパッドの周囲に環状に設けられていることを特徴とする半導体装置。
- 前記最上層の配線層が前記ボンディングパッドの周囲に2重以上に配置されていることを特徴とする請求項1記載の半導体装置。
- 前記空隙上のパッシベーション膜の縦方向膜厚が前記ボンディングパッド上のパッシベーション膜の縦方向膜厚より厚いことを特徴とする特徴とする請求項1または2記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015131484A JP6571414B2 (ja) | 2015-06-30 | 2015-06-30 | 半導体装置 |
TW105117628A TWI672781B (zh) | 2015-06-30 | 2016-06-03 | 半導體裝置 |
US15/193,386 US10504867B2 (en) | 2015-06-30 | 2016-06-27 | Semiconductor device having a bonding pad |
KR1020160081644A KR20170003453A (ko) | 2015-06-30 | 2016-06-29 | 반도체 장치 |
CN201610500365.XA CN106328626B (zh) | 2015-06-30 | 2016-06-30 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015131484A JP6571414B2 (ja) | 2015-06-30 | 2015-06-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017017152A JP2017017152A (ja) | 2017-01-19 |
JP6571414B2 true JP6571414B2 (ja) | 2019-09-04 |
Family
ID=57682952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015131484A Expired - Fee Related JP6571414B2 (ja) | 2015-06-30 | 2015-06-30 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10504867B2 (ja) |
JP (1) | JP6571414B2 (ja) |
KR (1) | KR20170003453A (ja) |
CN (1) | CN106328626B (ja) |
TW (1) | TWI672781B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109422234B (zh) * | 2017-09-01 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | 测试结构及其制造方法 |
JP2019152625A (ja) * | 2018-03-06 | 2019-09-12 | 株式会社デンソー | 電子装置 |
WO2020098470A1 (en) * | 2018-11-15 | 2020-05-22 | Changxin Memory Technologies, Inc. | Redistribution layer (rdl) structure, semiconductor device and manufacturing method thereof |
JP2020141100A (ja) * | 2019-03-01 | 2020-09-03 | キオクシア株式会社 | 半導体装置およびその製造方法 |
KR20210135052A (ko) | 2020-05-04 | 2021-11-12 | 삼성전자주식회사 | 반도체 패키지 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62214633A (ja) * | 1986-03-14 | 1987-09-21 | Nec Corp | 半導体集積回路装置 |
JPH0353843U (ja) * | 1989-09-29 | 1991-05-24 | ||
JP3053843B2 (ja) | 1990-05-25 | 2000-06-19 | ヤマハ発動機株式会社 | ヘリコプタの降着装置 |
JPH05226339A (ja) * | 1992-01-28 | 1993-09-03 | Nec Corp | 樹脂封止半導体装置 |
KR100280553B1 (ko) * | 1999-01-22 | 2001-01-15 | 김영환 | 반도체 장치 및 그 제조방법 |
JP5111878B2 (ja) * | 2007-01-31 | 2013-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5034740B2 (ja) * | 2007-07-23 | 2012-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
KR101185886B1 (ko) * | 2007-07-23 | 2012-09-25 | 삼성전자주식회사 | 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템 |
-
2015
- 2015-06-30 JP JP2015131484A patent/JP6571414B2/ja not_active Expired - Fee Related
-
2016
- 2016-06-03 TW TW105117628A patent/TWI672781B/zh not_active IP Right Cessation
- 2016-06-27 US US15/193,386 patent/US10504867B2/en not_active Expired - Fee Related
- 2016-06-29 KR KR1020160081644A patent/KR20170003453A/ko unknown
- 2016-06-30 CN CN201610500365.XA patent/CN106328626B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20170005024A1 (en) | 2017-01-05 |
TWI672781B (zh) | 2019-09-21 |
KR20170003453A (ko) | 2017-01-09 |
TW201705411A (zh) | 2017-02-01 |
JP2017017152A (ja) | 2017-01-19 |
CN106328626B (zh) | 2020-03-17 |
US10504867B2 (en) | 2019-12-10 |
CN106328626A (zh) | 2017-01-11 |
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