CN106328626B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN106328626B
CN106328626B CN201610500365.XA CN201610500365A CN106328626B CN 106328626 B CN106328626 B CN 106328626B CN 201610500365 A CN201610500365 A CN 201610500365A CN 106328626 B CN106328626 B CN 106328626B
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bonding pad
passivation film
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semiconductor device
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CN106328626A (zh
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岛崎洸一
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Ablic Inc
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Abstract

本发明提供一种提高针对接合时的应力的耐性的半导体装置，在接合焊盘（301）的周围隔着空隙（601）配置有布线层（303），钝化膜（401）比形成接合焊盘（301）的布线层（303）的膜厚更薄，空隙（601）的宽度为钝化膜厚的2倍以下，且钝化膜比布线层更薄。

Description

半导体装置
技术领域
本发明涉及具备接合焊盘的半导体装置。
背景技术
现有的半导体装置中的接合焊盘周边的构造，如图6所示，在半导体衬底101上设置绝缘膜201，并通过最上层的布线层在绝缘膜201上形成接合焊盘301，在接合焊盘301的周边隔着空隙设置虚设布线302。设有用于保护半导体装置的钝化膜401，钝化膜401具有接合焊盘301的膜厚以上的膜厚。以能将接合引线连接到接合焊盘301的方式，构造成为在接合焊盘301上设有用于露出接合焊盘301的表面的开口部501（例如，参照专利文献1）。
已知为了防止在引线接合时因应力或热应力而在钝化膜出现龟裂的情况，能够通过提高接合焊盘的周边的钝化膜的强度来抑制钝化龟裂。
现有技术文献
专利文献
专利文献1：日本特开平5－226339号公报。
发明内容
发明要解决的课题
然而，在钝化膜的膜厚比接合焊盘的膜厚更薄的情况下，钝化膜的强度会下降，因引线接合、热应力而会发生钝化龟裂。
本发明鉴于上述不良情况而构思，课题在于提供一种半导体装置，即便钝化膜比接合焊盘膜厚更薄的情况下，接合时的应力、热应力耐性也高。
用于解决课题的方案
本发明为了解决上述课题，采用一种半导体装置，其特征在于，在接合焊盘的周边隔着空隙配置布线层，钝化膜比形成所述接合焊盘的布线层的膜厚更薄，所述空隙的宽度为所述钝化膜厚以上且所述钝化膜厚的2倍以下，所述钝化膜沉积后填充到所述空隙的部分的所述钝化膜厚会比所述接合焊盘上部的部分的钝化膜更厚。
发明效果
在本发明中，通过使接合焊盘侧壁部分的钝化膜比沉积在接合焊盘的上部的钝化膜更厚，提高接合时的应力耐性。
附图说明
图1是示出本发明的半导体装置的第1实施方式的截面图。
图2是示出本发明的半导体装置的第2实施方式的截面图。
图3是示出本发明的半导体装置的第3实施方式的截面图。
图4是示出本发明的半导体装置的第4实施方式的平面图。
图5是示出本发明的半导体装置的第5实施方式的平面图。
图6是现有的半导体装置中的接合焊盘的截面图。
具体实施方式
以下，参照图1，对本发明的半导体装置的第1实施方式进行说明。
如图1所示，依据第1实施方式的接合焊盘及其周边构成为具有：设在半导体衬底101的表面的绝缘膜201；形成在绝缘膜201上的接合焊盘301；在接合焊盘301的周围隔着空隙601配置的最上层的布线层303；设置在接合焊盘301和布线层303上的用于保护半导体衬底101的钝化膜401；以及为连接接合引线而露出接合焊盘301的开口部501。
最上层的布线层303既可以沿着接合焊盘301的一边局部配置成1列，也可以将接合焊盘301的周围围成一圈地配置。图1示出沿着接合焊盘301的对置的2个边分别配置最上层的布线层303的状态。
在此，特征在于最上层的布线层303及接合焊盘301的厚度比最上层的布线层上的钝化膜401的纵向厚度更厚，接合焊盘301与最上层的布线层303的空隙601的宽度为最上层的布线层上的钝化膜401的纵向的厚度以上，且为该钝化膜的、沉积在由最上层的布线层303构成的孤立的图案的侧壁的部分的厚度即侧壁厚的2倍以下。通过这样的设定，在接合焊盘301与最上层的布线层的空隙601埋入有钝化膜401，覆盖接合焊盘301的侧壁的部分的钝化膜401的厚度因配置有最上层的布线层303而会比接合焊盘301的上部的部分的钝化膜401更厚。而且，覆盖接合焊盘301的侧壁的部分的钝化膜401的纵向的厚度会成为比接合焊盘301的纵向的厚度更厚。
此外，在绝缘膜201内含有其他布线层也无妨。另外，最上层的布线层的电位不管与接合焊盘301同电位、不同电位还是漂移电位都无妨。
另外，一般接合焊盘301为包括正方形的矩形，但是其他形状也无妨。进而，在钝化膜401上进一步沉积聚酰亚胺等的树脂也无妨。
当在接合焊盘301上进行了引线接合时，接合焊盘301变形，会施加从接合焊盘301的侧壁向水平方向按压钝化膜401的压力，但是，因为覆盖接合焊盘301的侧壁的部分的钝化膜401的膜厚较厚，接合时的应力耐性较高且能够抑制钝化膜401的龟裂发生。而且，由于覆盖接合焊盘的侧壁的部分的钝化膜的高度一样，所以也能消除容易在钝化膜的上部破坏的现有的缺点。
图2是示出本发明的第2实施方式的半导体装置的截面图。第1实施方式使最上层的布线层303邻接于接合焊盘301而配置1列或1圈。相对于此，第2实施方式将最上层的布线层303设置至少2列或2圈以上。通过这样构成，覆盖接合焊盘301的侧壁的部分的钝化膜401及最上层的布线层303的横向的厚度会比第一个实施方式更厚，能够进一步有效地抑制钝化膜401的龟裂发生。
图3是示出本发明的第3实施方式的半导体装置的截面图。第1实施方式中最上层的布线层303上的钝化膜401没有断开地覆盖最上层的布线层303。相对于此，第3实施方式在最上层的布线层303上的一部分使钝化膜401被狭缝701断开。即，在与接合焊盘不同的布线层303上设有除去了钝化膜401的区域即狭缝。断开钝化膜401的区域即狭缝缓和变形的应力，因此在本构造中也与第1实施方式同样能够抑制钝化膜401的龟裂发生。
图4是示出本发明的第4实施方式的半导体装置的平面图。在接合焊盘301的周围隔着空隙601设置的最上层的布线层303以1圈没有断开的环状设置。能够抑制钝化膜401的龟裂发生。
图5是示出本发明的第5实施方式的半导体装置的平面图。在接合焊盘301的周围隔着空隙601设置的最上层的布线层303以1圈断开而设置。即便最上层的布线层303断开也能抑制钝化膜401的龟裂发生。
通过图1至图5所示的实施方式的组合来形成的半导体装置，也能同样地抑制钝化膜401的龟裂发生。
标号说明
101 半导体衬底；201 绝缘膜；301 接合焊盘；302 虚设布线；303 最上层的布线层；401 钝化膜；501 开口部；601 布线层之间的空隙；701 设在钝化膜的狭缝。

Claims (7)

1.一种半导体装置，其特征在于，具有：
半导体衬底；
设在所述半导体衬底的表面的绝缘膜；
设在所述绝缘膜上的接合焊盘；
覆盖所述接合焊盘的、膜厚比所述接合焊盘的膜厚更薄的钝化膜；以及
在所述接合焊盘的周围隔着空隙而配置的最上层的布线层，
所述空隙的宽度为所述钝化膜的膜厚以上且所述钝化膜的、沉积在由所述最上层的布线层构成的孤立的图案的侧壁的部分的厚度即侧壁厚的2倍以下。
2.如权利要求1所述的半导体装置，其特征在于，所述最上层的布线层以环状配置在所述接合焊盘的周围。
3.如权利要求2所述的半导体装置，其特征在于，所述最上层的布线层断开了一部分。
4.如权利要求2所述的半导体装置，其特征在于，所述最上层的布线层以2圈以上配置在所述接合焊盘的周围。
5.如权利要求3所述的半导体装置，其特征在于，所述最上层的布线层以2圈以上配置在所述接合焊盘的周围。
6.如权利要求1至5的任一项所述的半导体装置，其特征在于，填充到所述空隙的部分的钝化膜的纵向膜厚比所述接合焊盘上的部分的钝化膜的纵向膜厚更厚。
7.如权利要求1至5的任一项所述的半导体装置，其特征在于，在所述接合焊盘的周围隔着空隙而配置的最上层的布线层上设有所述钝化膜被局部除去的狭缝。
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JP2019152625A (ja) * 2018-03-06 2019-09-12 株式会社デンソー 電子装置
WO2020098470A1 (en) 2018-11-15 2020-05-22 Changxin Memory Technologies, Inc. Redistribution layer (rdl) structure, semiconductor device and manufacturing method thereof
JP2020141100A (ja) 2019-03-01 2020-09-03 キオクシア株式会社 半導体装置およびその製造方法
US11444070B2 (en) 2020-05-04 2022-09-13 Samsung Electronics Co., Ltd. Semiconductor packages

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TWI672781B (zh) 2019-09-21
JP6571414B2 (ja) 2019-09-04
US20170005024A1 (en) 2017-01-05
KR20170003453A (ko) 2017-01-09
CN106328626A (zh) 2017-01-11
US10504867B2 (en) 2019-12-10

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