TWI679767B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI679767B
TWI679767B TW106135671A TW106135671A TWI679767B TW I679767 B TWI679767 B TW I679767B TW 106135671 A TW106135671 A TW 106135671A TW 106135671 A TW106135671 A TW 106135671A TW I679767 B TWI679767 B TW I679767B
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Taiwan
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feature
features
type
gate
etching process
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TW106135671A
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TW201914008A (zh
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劭銘 許
Shao-Ming Koh
李振銘
Chen Ming Lee
吳以雯
I Wen Wu
楊復凱
Fu Kai Yang
王嘉亨
Jia Heng Wang
王美勻
Mei Yun Wang
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

本揭露提供一種半導體裝置之形成方法，包括：提供一結構；蝕刻第一和第二介電層以暴露第一和第二S/D特徵；摻雜一p-型摻質至第一和第二S/D特徵；以及在摻雜p-型摻質之後，對第一和第二S/D特徵實施一選擇性蝕刻製程，其中比起使第二S/D特徵凹陷，選擇性蝕刻製程較快地使第一S/D特徵凹陷。上述結構包括：一基板；一第一閘極結構和一第二閘極結構，位於基板之上；一第一源極/汲極(S/D)特徵及一第二S/D特徵，位於基板之上，其中第一S/D特徵與第一閘極結構相鄰，第二S/D特徵與第二閘極結構相鄰，且第一和第二S/D特徵包括不同的材料；一第一介電層，位於第一和第二閘極結構的側壁之上且位於第一和第二S/D特徵之上；以及一第二介電層，位於第一介電層之上。

Description

半導體裝置及其形成方法
本揭露係關於半導體裝置及其形成方法，且特別是有關於一種鰭狀場效電晶體(FinFET)裝置中的S/D接觸及其形成方法。
半導體積體電路(IC)工業已歷經快速發展的階段。積體電路材料及設計在技術上的進步使得每一代生產的積體電路變得比先前生產的積體電路更小且其電路也變得更複雜。在積體電路發展的進程中，功能性密度(亦即，每一個晶片區域中內連線裝置的數目)已經普遍增加，而幾何尺寸(亦即，製程中所能創造出最小的元件或線路)則是普遍下降。這種微縮化的過程通常可藉由增加生產效率及降低相關支出提供許多利益。但此種微縮化也增加了積體電路加工和製造上的複雜度，且為了實現這樣的進展，積體電路加工和製造上也需要有相同的進步。
舉例而言，當要形成小型電晶體像是具有鰭狀通道的場效電晶體(FET，所謂的“FinFETs”)的源極/汲極(S/D)接觸時，有時候會期望以額外的摻質來摻雜S/D特徵以增加裝置的效能。由於n-型和p-型FET可能需要不同的摻質，因而創 造出摻雜罩幕以在摻雜製程遮蔽p-型裝置或n-型裝置。然而，在逐漸縮小的裝置中，圖案化和移除罩幕已經成為一種挑戰。舉例而言，當為了p-型裝置而創造此摻雜罩幕時，可能需要一些過蝕刻以確保沒有罩幕殘留在p-型S/D特徵上。這種過蝕刻時常造成n-型裝置的罩幕區域減少。因此，摻雜p-型S/D特徵可能不經意地將p-型摻質引入n-型裝置。
需要對S/D接觸的形成製程進行一些改良。
根據一實施例，本揭露提供一種半導體裝置的形成方法，包括：提供一結構；蝕刻第一和第二介電層以暴露第一和第二S/D特徵；摻雜一p-型摻質至第一和第二S/D特徵；以及在摻雜p-型摻質之後，對第一和第二S/D特徵實施一選擇性蝕刻製程，其中比起使第二S/D特徵凹陷，選擇性蝕刻製程較快地使第一S/D特徵凹陷。上述結構包括：一基板；一第一閘極結構和一第二閘極結構，位於基板之上；一第一源極/汲極(S/D)特徵及一第二S/D特徵，位於基板之上，其中第一S/D特徵與第一閘極結構相鄰，第二S/D特徵與第二閘極結構相鄰，且第一和第二S/D特徵包括不同的材料；一第一介電層，位於第一和第二閘極結構的側壁之上且位於第一和第二S/D特徵之上；以及一第二介電層，位於第一介電層之上。
根據另一實施例，本揭露提供一種半導體裝置的形成方法，包括：提供一結構；蝕刻一層或多層介電層以暴露第一和第二S/D特徵；藉由一相同的摻雜製程摻雜一p-型摻質至第一和第二S/D特徵以得到第一S/D特徵的一p-型摻雜部分 和第二S/D特徵的一p-型摻雜部分；以及在摻雜p-型摻質之後，藉由一相同的蝕刻製程部分地蝕刻第一和第二S/D特徵，其中比起使第二S/D特徵凹陷，選擇性蝕刻製程以一較快的速度使第一S/D特徵凹陷。上述結構包括：一基板；一第一閘極結構和一第二閘極結構，位於基板之上；一第一源極/汲極(S/D)特徵，包括n-型摻雜矽，與第一閘極結構相鄰；一第二S/D特徵，包括矽鍺，與第二閘極結構相鄰；以及一層或多層介電層，位於第一和第二閘極結構的側壁之上且位於第一和第二S/D特徵之上。
又根據另一實施例，本揭露提供一種半導體裝置，包括：一n-型FinFET區域；及一p-型FinFET區域。上述n-型FinFET區域包括：一第一閘極堆疊；一第一閘極間隔，位於第一閘極堆疊的側壁之上；以及一n-型磊晶特徵，位於n-型FinFET區域的一源極/汲極(S/D)區域中。上述p-型FinFET區域包括：一第二閘極堆疊；一第二閘極間隔，位於第二閘極堆疊的側壁之上；以及一p-型磊晶特徵，位於p-型FinFET區域的一源極/汲極(S/D)區域中。其中，第一閘極間隔的一底表面與n-型磊晶特徵的一上表面的一最低點之間的一第一垂直距離大於第二閘極間隔的一底表面與p-型磊晶特徵的一上表面的一最低點之間的一第二垂直距離。
10‧‧‧方法
12、14、16、18、20、22、24、26、28、30、32‧‧‧操作
100‧‧‧裝置
102‧‧‧基板
102A、102B‧‧‧區域
103‧‧‧鰭
104A、104A’、104B、104B’、122‧‧‧S/D特徵
104A-1、104B-1‧‧‧部分
105‧‧‧隔離結構
106A、106B‧‧‧閘極堆疊
108‧‧‧閘極間隔物
110‧‧‧蝕刻停止層(CESL)
112‧‧‧介電層
114‧‧‧罩幕
116‧‧‧開口
118‧‧‧保護側壁/介電層
120A、120B‧‧‧矽化物特徵
122‧‧‧S/D接觸
d1、d2‧‧‧深度
x、y、z‧‧‧方向
本揭露最好配合圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準實施，各個特徵並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個 特徵的尺寸。
第1A和1B圖為根據本揭露各實施例顯示半導體裝置之形成方法的流程圖。
第2A、3A、4A、5A、6A、7A、8A、9A、10A、及11A圖為根據一實施例及第1A和1B圖的方法所繪製之一部份的半導體裝置於各製程階段中的剖面圖(沿著鰭的長度方向)。
第2B、3B、4B、5B、6B、7B、8B、9B、10B、及11B圖為根據一實施例及第1A和1B圖的方法所繪製之一部份的半導體裝置於各製程階段中的剖面圖(沿著鰭的寬度方向)。
以下揭示提供許多不同的實施方法或是例子來實行本揭露之不同特徵。以下描述具體的元件及其排列的例子以簡化本揭露。當然這些僅是例子且不該以此限定本揭露的範圍。例如，在描述中提及第一個元件形成於第二個元件之上時，其可能包括第一個元件與第二個元件直接接觸的實施例，也可能包括兩者之間有其他元件形成而沒有直接接觸的實施例。此外，在不同實施例中可能使用重複的標號及/或符號，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖式中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖式中所 描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
本揭露係普遍關於半導體裝置及其形成方法。更特別地，本揭露係關於半導體裝置中，特別是鰭狀場效電晶體(FinFET)裝置中的S/D接觸的形成。本揭露的一目的是要降低形成S/D接觸之罩幕圖案化步驟的數目。更特別地，本揭露的一實施例未遮蔽n-型S/D特徵就摻雜p-型S/D特徵，並接著藉由一選擇性蝕刻製程移除n-型S/D特徵的相對摻雜部分。在此摻雜和蝕刻製程中，不包括罩幕圖案化，因此避免傳統製法中相關的議題並同時節省製造成本。
第1A和1B圖為根據本揭露各實施例顯示半導體裝置100之形成方法10的流程圖。方法10僅為一示例，且不用於將本揭露限制於申請專利範圍明確記載的內容之外。可在方法10之前、期間、及之後提供額外的操作，且在此方法的額外實施例中，一些所述的操作可被置換、移除、或移動。以下結合第2A~11B圖描述方法10，第2A~11B圖為半導體裝置100在各製程階段的剖面圖。特別地，第2A、3A、4A、5A、6A、7A、8A、9A、10A、及11A圖為一部份的半導體裝置100於各製程階段中沿著鰭的長度方向的剖面圖；而第2B、3B、4B、5B、6B、7B、8B、9B、10B、及11B圖為一部份的半導體裝置100於各製程階段中沿著鰭的寬度方向的剖面圖。
半導體裝置100係提供以達到說明的目的，且不將本揭露之實施例限制為任何數量的裝置、任何數量的區域、或任何配置的結構或區域。此外，如第2A~11B所示的半導體裝 置100可為在積體電路製程期間所形成的一中間裝置、或其一部分，其可包括靜態隨機存取記憶體(SRAM)及/或邏輯電路、被動元件像是電阻器、電容器、及電感器、和主動元件像是p-型場效電晶體(PFETs)、n-型FETs(NFETs)、多閘極FETs像是FinFETs、金氧半導體場效電晶體(MOSFETs)、互補式金氧半導體(CMOS)電晶體、雙極電晶體、高壓電晶體、高頻電晶體、其他記憶體電池、及前述之組合。
參照第1A圖，於操作12，方法10提供裝置100的一前驅物結構，如第2A和2B圖所示。參照第2A和2B圖，裝置100包括一基板102及形成於其中或其上的各種特徵。基板102包括兩個基板區域102A和102B。於本實施例中，基板區域102A用於形成一或多個n-型FinFET裝置，且基板區域102B用於形成一或多個p-型FinFET裝置。因此，基板區域102A也被稱為NFET區域102A，且基板區域102B也被稱為PFET區域102B。每一個NFET區域102A和PFET區域102B包括由隔離結構105(第2B圖)隔開的一或多個半導體鰭103。特別地，第2A圖顯示裝置100的S/D區域中裝置100沿著鰭103的長度(“x”方向)的剖面圖，且第2B圖顯示裝置100的S/D區域中裝置100沿著鰭103的寬度(“y”方向)的剖面圖。於NFET區域102A中，裝置100更包括位於鰭103之上的S/D特徵104A，及與鰭103的通道區域相鄰且被相鄰的S/D特徵104A夾住(sandwiched)的閘極堆疊106A。於PFET區域102B中，裝置100更包括位於鰭103之上的S/D特徵104B，及與鰭103的通道區域相鄰且被相鄰的S/D特徵104B夾住的閘極堆疊106B。裝置100更包括位於閘極堆疊106A和106B 的側壁上的一閘極間隔物108、位於閘極間隔物108和S/D特徵104A和104B之上的一接觸蝕刻停止層(CESL)110、以及位於CESL 110之上且填充於相鄰閘極間隔物108之間的間隙(gap)中的一介電層112。裝置100的各特徵(或元件)於以下進一步描述。
在本實施例中，基板102為一矽基板。在替代實施例中，基板102包括其他元素半導體，例如鍺；一化合物半導體，例如碳化矽、砷化鎵、砷化銦、及磷化銦；或一合金半導體，例如碳化矽鍺、磷化砷鎵、及磷化銦鎵。在一實施例中，基板102可包括絕緣體上矽(SOI)基板，經施加應變及/或應力以提高性能，包括磊晶區域、摻雜區域、及/或包括其他合適的特徵及層。
可藉由任何合適的方法圖案化鰭103。舉例而言，使用一或多種微影製程圖案化鰭103，包括雙圖案化或多重圖案化製程。一般而言，雙圖案化或多重圖案化製程結合微影和自對準製程，使得所創造的圖案具有例如小於利用單一、直接的微影製程所獲得的間距(pitches)。舉例而言，在一實施例中，於基板之上形成犧牲層並使用微影製程將其圖案化。使用自對準製程在圖案化犧牲層旁形成間隔物(spacer)。接著移除犧牲層，且可接著將剩餘的間隔物、或心軸(mandrel)用作罩幕元件以圖案化鰭103。舉例而言，可使用罩幕元件以在基板102中蝕刻出凹部，留下鰭103在基板102上。蝕刻製程可包括乾蝕刻、濕蝕刻、反應性離子蝕刻(RIE)、及/或其他合適的製程。舉例而言，乾蝕刻可實施一含氧氣體、一含氟氣體 (例如：CF4、SF6、CH2F2、CHF3、及/或C2F6)、一含氯氣體(例如：Cl2、CHCl3、CCl4、及/或BCl3)、一含硼氣體(例如：HBr及/或CHBR3)、一含碘氣體、其他合適的氣體及/或電漿、及/或前述之組合。舉例而言，濕蝕刻可包括在稀釋的氫氟酸(DHF)、氫氧化鉀(KOH)、氨、包含氟酸(HF)、硝酸(HNO3)、及/或醋酸(CH3COOH)的溶液、或其他合適的蝕刻液中蝕刻。許多其他方法的實施例也適用於形成鰭103。
S/D特徵104A和104B可包括像是磊晶半導體材料以施加適當的應力並增強裝置100的性能。舉例而言，S/D特徵104A可包括磊晶生長的矽或矽-碳，且S/D特徵104B可包括磊晶生長的矽鍺。此外，S/D特徵104A和104B可摻雜有適合於各自的n-型和p-型裝置的適當摻質。例如，S/D特徵104A可摻雜有像是磷或砷的n-型摻質，且S/D特徵104B可摻雜有像是硼或銦的p-型摻質。在一實施例中，藉由蝕刻鰭103而(分別地)形成S/D特徵104A和104B，在鰭103之上磊晶生長適當的半導體材料，並將適當的摻質(原位或非原位)摻雜到磊晶生長材料中。在一些實施例中，相鄰的S/D特徵104A可以彼此分隔(未顯示)或可以合併(例如，第2B圖中的兩個104A)。類似地，在一些實施例中，相鄰的S/D特徵104B可以彼此分隔(例如，第2B圖)或可以合併(未顯示)。此外，每一個S/D特徵104A和104B可以是多面形狀。
隔離結構105可包括氧化矽、氮化矽、氮氧化矽、氟化物摻雜的矽酸鹽玻璃(FSG)、低k介電材料、及/或其它合適的絕緣材料。在一實施例中，藉由蝕刻基板102中的溝槽 (例如，作為形成鰭103的過程的一部分)形成隔離結構105、用絕緣材料填充溝槽、並實施化學機械平坦化(CMP)製程至包含絕緣材料的基板102。其他類型的隔離結構也可以是合適的，例如場氧化物和局部氧化矽(LOCOS)。
每一個閘極堆疊106A和106B是多層結構。例如，閘極堆疊106A和106B中的每一個可包括介電界面層、位於介電界面層之上的閘極介電層、以及位於閘極介電層之上的閘極電極層。在一實施例中，閘極堆疊106A和106B是用於高k金屬閘極的佔位者(placeholder)(所謂的“虛擬閘極”)，其中閘極堆疊106A和106B中的一或多個層在隨後的製程中將被置換。在另一個實施例中，閘極堆疊106A和106B包括高k閘極介電層、位於高k閘極介電層之上的功函數層、以及位於功函數層上的金屬層。在各種實施例中，介電界面層可包括像是氧化矽(SiO2)或氮氧化矽(SiON)的介電材料，且可藉由化學氧化、熱氧化、原子層沉積(ALD)、化學氣相沉積、及/或其它合適的方法形成。閘極介質層可包括氧化矽(SiO2)。高k閘極介電層可包括氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)、其它合適的金屬氧化物、或前述之組合；且可藉由ALD及/或其他合適的方法形成。閘極電極層可包括多晶矽或像是鋁(Al)、鎢(W)、鈷(Co)、銅(Cu)、及/或其它合適材料的金屬。功函數層可為p-型(對於閘極堆疊106B)或n-型(對於閘極堆疊106A)。p-型功函數層包括具有足夠大的有效功函數的金屬，其選自但不限於氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、 鉬(Mo)、鎢(W)、鉑(Pt)、或前述之組合的群組。n-型功函數層包括具有足夠低的有效功函數的金屬，其選自但不限於鈦(Ti)、鋁(Al)、碳化鉭(TaC)、鉭碳氮化物(TaCN)、鉭氮化矽(TaSiN)、或前述之組合的群組。p-型或n-型功函數層可包括複數個層，且可藉由CVD、PVD、及/或其它合適的製程沉積。
閘極間隔物108可為單層或多層結構。在一些實施例中，閘極間隔物108包括一介電材料，像是氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、其它介電材料、或前述之組合。在一示例中，閘極間隔物108的形成是藉由在具有閘極堆疊106A和106B的裝置100之上毯覆式(blanket)沉積作為襯層的第一介電層(例如，具有均勻厚度的SiO2層)並在第一介電層之上毯式沉積作為主要D-形間隔物的第二介電層(例如，SiN層)，然後，藉由非等向性蝕刻移除部分的介電層以形成閘極間隔物108。
CESL 110可包括氮化矽、氮氧化矽、具有氧(O)或碳(C)元素的氮化矽、及/或其它材料。在一示例中，CESL 110包括具有大小為1GPa或更大的本質應力(intrinsic stress)的氮化矽(Si3N4)。本質應力對p-通道裝置是壓縮，對n-通道裝置是拉伸。可藉由PECVD製程及/或其他合適的沉積或氧化製程形成CESL 110。CESL 110覆蓋S/D特徵104A和104B的外表面、閘極間隔物108的側壁、和隔離結構105的頂表面。
介電層(或層間介電質)112可包括像是四乙氧基矽烷(TEOS)氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化 矽像是硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜矽玻璃(BSG)、及/或其它合適的介電材料。可藉由PECVD製程、流動式的CVD(FCVD)製程、或其他合適的沉積技術沉積介電層112。在一實施例中，CESL 110作為毯覆層(blanket layer)沉積在基板102之上並覆蓋其上的各種結構，且介電層112沉積在CESL層110之上以填充閘極堆疊106A和106B之間的溝槽。
在操作14中，方法10(第1A圖)蝕刻介電層112和CESL 110以暴露S/D特徵104A和104B，以準備在相應的S/D特徵之上形成S/D接觸。這可能涉及各種製程，包括沉積、微影、和蝕刻。參照第3A和3B圖，在裝置100之上形成蝕刻罩幕114，提供暴露裝置100的各個部分的開口116。開口116對應於將要形成S/D接觸的裝置100的區域。在各種實施例中，蝕刻罩幕114可包括硬罩幕層(例如，具有氮化矽或氧化矽)、光阻層、或前述之組合。參照第4A和4B圖，使用例如乾蝕刻製程、濕蝕刻製程、或反應性離子蝕刻製程，穿過開口116蝕刻裝置100以移除介電層112的暴露部分。在本實施例中，蝕刻製程對介電層112的材料是具有選擇性的，且不(或不顯著地)蝕刻閘極堆疊106A和106B、閘極間隔物108、及CESL 110。參照第5A和5B圖，使用例如乾蝕刻製程、濕蝕刻製程、或反應性離子蝕刻製程，再次穿過開口116蝕刻裝置100以移除開口116底部的一部分的CESL 110。特別地，此蝕刻製程是非等向性的。結果，在蝕刻製程完成之後，一部分的CESL 110保留在閘極堆疊106A和106B的側壁之上。此外，此蝕刻製程對CESL 110具有選擇 性，且不(或不顯著地)蝕刻閘極堆疊106A和106B以及閘極間隔物108。儘管在本實施例中使用兩個單獨的蝕刻製程來蝕刻介電層112和CESL 110，但是在各種實施例中，可替代地使用一個接合蝕刻製程或多於兩個的蝕刻製程。
在一些實施例中，在操作14完成之後，在閘極堆疊106A和106B的側壁(稱為CESL 110側壁)之上的CESL 110部分可能變得不合需要。舉例而言，CESL 110可具有薄的輪廓，其由蝕刻介電層112和CESL 110的蝕刻製程開始且部分地消耗。這種薄CESL 110側壁的一個問題是，閘極堆疊106A和106B以及S/D特徵104A和104B中的材料可能最終混合而造成裝置缺陷(例如：短路)。另一個問題是薄CESL的側壁將在電壓偏置期間擊穿(breakdown)，這最終將導致相應的S/D特徵和閘極堆疊的短路。在本實施例中，在CESL 110側壁之上形成保護側壁118以增加閘極堆疊106A和106B上的介電層的厚度。
在操作16中，方法10(第1A圖)藉由實施沉積製程和蝕刻製程形成保護側壁118。參考第6A和6B圖，方法10在裝置100之上沉積介電層118，特別是在開口116的側壁之上以及S/D特徵104A和104B的頂部上。在一實施例中，介電層118包括氮化矽。或者，介電層118可包括氮氧化矽、矽碳氮化物、或其它合適的材料。可藉由CVD、PVD、或ALD方法沉積介電層118。參考第7A和7B圖，方法10非等向性地蝕刻介電層118，留下一部分的介電質118於開口116的側壁之上，特別是在CESL 110側壁之上作為一保護層。保護側壁118有利地增加了閘極堆疊106A和106B側壁之上的介電層的厚度。在一實施例 中，蝕刻製程為乾蝕刻。在方法10的一些實施例中，其中CESL 110側壁在操作14完成之後具有足夠的厚度，而不實施操作16。在操作14和(視情況地)操作16的蝕刻製程之後，透過開口116而暴露S/D特徵104A和104B(或其一部分)，如第5A、5B、7A、和7B圖所示。
在一些實施例中，在上述各種蝕刻製程期間，可對S/D特徵104A和104B進行蝕刻，包括對CESL 110的蝕刻及對介電層118的視情況的蝕刻。例如，當蝕刻CESL 110以暴露S/D特徵104A和104B時，可實施一些過蝕刻以確保沒有介電質殘留在相應的S/D特徵上。否則，S/D接觸電阻可能會不符合期望地高、或可能會出現開路缺陷。然而，這種過蝕刻可能不經意地蝕刻S/D特徵104A和104B。在一些實施例中，可有意地蝕刻S/D特徵104A和104B以增加S/D接觸形成的界面面積。不經意的過蝕刻或有意的蝕刻可能改變S/D特徵的結構並影響裝置性能。在特定示例中，S/D特徵104B包括用來向p-型FinFET施加應變(或應力)的矽鍺，而蝕刻S/D特徵104B通常會不符期望地鬆弛應變。為了加強或增加S/D特徵104B中的應變，根據本實施例，方法10將p-型摻質摻雜至S/D特徵104B中。
在操作18中，方法10(第1A圖)將p-型摻質摻雜至S/D特徵104B(第8A和8B圖)中。特別地，方法10將p-型摻質摻雜至S/D特徵104B和S/D特徵104A中。如第8A和8B圖所示，S/D特徵104A的部分104A-1摻雜有p-型摻質，且S/D特徵104B的部分104B-1也摻雜有p-型摻質。在一實施例中，S/D特徵104A在操作18之前是n-型摻雜的(例如，具有磷摻雜矽或磷摻雜矽 -碳)。因此，藉由操作18對部分104A-1相對摻雜以具有n-型和p-型摻質。避免這種相對摻雜的一種方法是在將p-型摻質摻雜至S/D特徵104B時，形成遮蔽S/D特徵104A的摻雜罩幕。然而，形成此摻雜罩幕不僅涉及額外的材料成本和製造時間，而且還將其它問題引入製程中。例如，創造此摻雜罩幕可能需要在PFET區域102B中進行一些過蝕刻，以確保沒有罩幕殘留在S/D特徵104B上。這種過蝕刻時常會導致S/D特徵104A之上的罩幕面積減小。因此，摻雜S/D特徵104B可能意外地將p-型摻質引入S/D特徵104A。在本實施例中，方法10將p-型摻質摻雜至S/D特徵104A和104B兩者中，並接著選擇性蝕刻S/D特徵104A和104B以移除經相對摻雜的部分104A-1。這免除了創造摻雜罩幕的需要。
在一實施例中，S/D特徵104A包括磷摻雜矽或矽-碳，且S/D特徵104B可包括摻雜或未摻雜的矽鍺。為了進一步實施本實施例，操作18將硼摻雜到S/D特徵104A和104B中。操作18控制摻雜能量的水平，以確保摻質在各自S/D特徵中到達一定的深度。在一些實施例中，摻雜能量的範圍為1keV至5keV。操作18也控制摻質劑量的水平，以確保p-型FinFET的適當性能。在一些實施例中，摻質劑量的範圍為1E15cm-2至1E16cm-2。
在操作20中，方法10(第1A圖)藉由實施退火製程來活化p-型S/D特徵104B中的p-型摻質。由於p-型摻質也被引入到n-型S/D特徵104A中，所以仔細選擇退火製程以將p-型摻質在n-型S/D特徵104A中的擴散最小化。例如，操作20可使用在毫秒內上下升降溫度的動態尖峰退火(DSA)，或在奈米 秒內上下升降溫度的熔融雷射退火(MLA)。也可使用具有非常快的升溫速率的其它類型的退火。在方法10的實施例中不實施操作20，而是在移除經相對摻雜的部分104A-1之後，實施p-型摻質的活化(討論如下)。
在操作22中，方法10(第1B圖)對S/D特徵104A和104B實施選擇性蝕刻製程。在本實施例中，選擇性蝕刻製程被調整以比蝕刻S/D特徵104B更快的速率蝕刻S/D特徵104A。如第9A和9B圖所示，當其完成時，操作22完全移除經相對摻雜的部分104A-1，並且僅部分地去除摻雜部分104B-1。此外，NFET區域102A和PFET區域102B中的不同蝕刻速率導致S/D特徵104A和104B中的蝕刻深度不同。更具體地，S/D特徵104A被蝕刻(或部分移除)了深度d1，S/D特徵104B被蝕刻(或部分移除)了深度d2，並且d1大於d2。在一實施例中，可從經蝕刻的S/D特徵104A的上表面的最低點到相鄰閘極間隔物108的底表面測量d1，如第9A圖所示。或者，可以從經蝕刻的S/D特徵104A的上表面的最低點到相鄰的未經蝕刻的S/D特徵104A的上表面的相應點測量d1，其中兩個點具有相同的“y”坐標，但不同的“x”坐標，如第9B圖所示。第9B圖顯示(在前方之)經蝕刻的S/D特徵104A的“y-z”剖面重疊未經蝕刻的S/D特徵104A’的另一個“y-z”剖面。沿著“z”方向的兩點之間的差表示在S/D特徵104A中的蝕刻深度。可類似地測量深度d2。特別地，第9圖顯示(在前方之)經蝕刻的S/D特徵104B的“y-z”剖面重疊未經蝕刻的S/D特徵104B’的另一個“y-z”剖面。沿著“z”方向的兩點之間的差表示在S/D特徵104B中的蝕刻深度。 在各個實施例中，深度d1大於深度d2至少5nm。在NFET區域102A中，S/D特徵104A中較大的蝕刻深度通常導致用於S/D接觸的界面面積增加，從而降低S/D接觸電阻。在PFET區域102B中，S/D特徵104B中較小的蝕刻深度有助於維持建造於S/D特徵104B中的應力/應變。此外，蝕刻製程被調整為不蝕刻閘極堆疊106A和106B、閘極間隔物108、CESL 110、以及介電層118。蝕刻製程可包括乾蝕刻或濕蝕刻。在一實施例中，蝕刻製程是使用SF6、H2、和CF4的氣體混合物作為蝕刻劑的乾蝕刻。這些氣體的組合導致在S/D特徵104A和104B的半導體材料之上形成含碳和硫的鈍化層。比起在具有矽的S/D特徵104A之上，此鈍化層更可能產生在具有矽鍺的S/D特徵104B之上，這有效地降低了蝕刻製程中S/D特徵104B的蝕刻速率。在另一個實施例中，蝕刻製程是使用具有氫氧化銨(NH4OH)或四甲基氫氧化銨(TMAH)的蝕刻劑的濕蝕刻，其對於矽比起對於矽鍺具有較快的蝕刻速率。
應注意的是，同時對S/D特徵104A和104B實施p-型摻雜(操作18)和選擇性蝕刻製程(操作22)，而不需要遮蔽任何一種類型的S/D特徵。這有利於節省材料成本和製造時間。
在操作24中，方法10(第1B圖)藉由實施退火製程活化S/D特徵104B中的p-型摻質。由於經相對摻雜的部分104A-1已經被移除，所以操作24可從各種退火製程中進行選擇，而不需考慮使S/D特徵104A中的p-型摻質擴散最小化的問題。例如，操作24可使用一或多個退火製程，例如：微波退火(MWA) 製程、微秒退火(μ SSA)製程、快速熱退火(RTA)製程、動態尖峰退火(DSA)製程、熔融雷射退火(MLA)製程、及/或其它合適的退火製程。然而，操作24的溫度預算可以考慮閘極堆疊106A和106B的材料，以不傷害閘極堆疊。應注意的是，如果已經實施了操作20，則可以省略操作24。
在操作26中，方法10(第1B圖)清潔S/D特徵104A和104B的表面，並使其準備好用於隨後的矽化製程。操作26可使用乾式清洗製程或濕式清洗製程。例如，乾式清洗製程可使用SiConi蝕刻，SiConi蝕刻是遠端電漿輔助乾蝕刻製程，其涉及將物體同時暴露於H2、NF3、和NH3電漿副產物。例如，濕式清洗製程可使用稀釋的氫氟酸(DHF)溶液來清潔S/D特徵104A和104B的表面。
在操作28中，方法10(第1B圖)分別在S/D特徵104A和104B之上形成矽化物特徵120A和120B，以減少S/D接觸電阻。在示例性實施例中，方法10在S/D特徵104A和104B之上沉積金屬膜，實施退火製程以引起金屬膜和其下的半導體材料之間的反應，並且移除過量的未反應金屬。剩餘的金屬半導體材料變成矽化物特徵120A和120B，如第10A和10B圖所示。例如，金屬膜的厚度可約為10nm或以下，例如5nm或以下。在一實施例中，相同的金屬膜可用於n-型和p-型S/D特徵兩者的矽化。或者，用於n-型S/D特徵104A的矽化的金屬膜可不同於用於p-型S/D特徵104B的矽化的金屬膜。在各種實施例中，金屬膜可包括鈦(Ti)、鎳(Ni)、鈷(Co)、鉭(Ta)、鉺(Er)、釔(Y)、鐿(Yb)、鉑(Pt)、或前述之組合。
在操作30中，方法10(第1B圖)藉由在開口116中沉積金屬而於矽化物特徵120A和120B之上形成S/D接觸122。如第11A和11B圖所示，S/D接觸122填充開口116並分別透過矽化物特徵120A和120B覆蓋S/D特徵104A和104B的頂表面和側表面。在一些實施例中，S/D接觸122可包括鎢(W)、鈷(Co)、銅(Cu)、其它元素金屬、金屬氮化物(像是氮化鈦(TiN)、氮化鋁鈦(TiAlN)、氮化鎢WN)、氮化鉭(TaN)、或前述之組合)，且可藉由CVD、PVD、鍍覆、及/或其它合適的製程形成。在一實施例中，在沉積用於S/D接觸122的金屬之前，移除罩幕元件114。此外，可實施CMP製程以將裝置100的頂表面平坦化，以獲得如第11A和11B圖所示的結構。
參考第11A和11B圖，NFET區域102A中S/D接觸122的底表面比PFET區域102B中S/D接觸122的底表面低。這是操作22的選擇性蝕刻製程造成的結果。在PFET區域102B中，S/D接觸122設置在包括p-型S/D特徵104B、摻雜有額外的p-型摻質的部分104B-1、和矽化物特徵120B的多層結構之上。此外，S/D接觸122的側壁夾在保護介電層118、CESL 110、閘極間隔物108、和閘極堆疊106A(NFET區域102A中)和106B(PFET區102B中)之間。
在操作32中，方法10(第1B圖)實施進一步的步驟以完成裝置100的製造。例如，操作32可形成電性連接閘極堆疊106A和106B的閘極接觸，且可形成連接FinFET以及裝置100其他部分的金屬內連接以形成完整的積體電路。
儘管不用於限制，本揭露的一或多個實施例為半導體裝置及其形成製程提供了許多益處。例如，當形成用於FINFET裝置的S/D接觸時，本揭露的實施例將額外的p-型摻質摻雜至p-型S/D特徵中以降低其中的電阻。此摻雜在沒有用於n-型S/D特徵的摻雜罩幕的情況下實施，從而簡化了製造製程並降低了製造成本。隨後透過選擇性蝕刻製程移除n-型S/D特徵中經相對摻雜的部分，而不需要用於p-型裝置的蝕刻罩幕，這再次簡化了製造製程並降低了製造成本。本揭露所提供的請求物可輕易地被整合到現有的IC製造流程中，並且可應用於許多不同的製程節點。
在一示例性方面，本揭露涉及一種半導體裝置之形成方法。此方法包括提供一種結構，包括：基板；在基板之上的第一閘極結構和第二閘極結構；在基板之上的第一源極/汲極(S/D)特徵和第二S/D特徵，其中第一S/D特徵與第一閘極結構相鄰，第二S/D特徵與第二閘極結構相鄰，且第一和第二S/D特徵包括不同的材料；在第一和第二閘極結構的側壁之上及第一和第二S/D特徵之上的第一介電層；以及在第一介電層之上的第二介電層。此方法還包括蝕刻第一和第二介電層以暴露第一和第二S/D特徵；摻雜p-型摻質至第一和第二S/D特徵；以及在摻雜p-型摻質之後，對第一和第二S/D特徵實施選擇性蝕刻製程。比使第二S/D特徵凹陷，所述選擇性蝕刻製程較快地使第一S/D特徵凹陷。
在此方法的一實施例中，第一S/D特徵包括摻雜有n-型摻質的矽或矽-碳，且第二S/D特徵包括矽鍺。在此方法的另一實施例中，n-型摻質是磷或砷且p-型摻質是硼。在此方法 的另一實施例中，選擇性蝕刻製程包括使用SF6、H2和CF4的氣體混合物的乾蝕刻製程，或使用NH4OH或TMAH的濕蝕刻製程。
在該方法的一實施例中，p-型摻質的摻雜使用的摻雜能量範圍為1keV至5keV，且p-型摻質的摻質量範圍為1E15cm-2至1E16cm-2。
在另一實施例中，在蝕刻第一和第二介電層之後及在摻雜p-型摻質之前，此方法還包括在結構之上沉積第三介電層，並對第三介電層實施非等向性蝕刻製程以暴露第一和第二S/D特徵且保留第三介電層的一部分於第一和第二閘極結構的側壁之上。
在一實施例中，在實施選擇性蝕刻製程之後，此方法還包括對位於第二S/D特徵中的p-型摻質進行退火。在一替代實施例中，在實施選擇性蝕刻製程之前，此方法還包括對位於至少第二S/D特徵中的p-型摻質進行退火。
在一實施例中，在實施選擇性蝕刻處理之後，此方法還包括在第一和第二S/D特徵的剩餘部分之上沉積金屬。在另一實施例中，在實施選擇性蝕刻製程之後及沉積金屬之前，此方法還包括在第一S/D特徵的剩餘部分之上形成第一矽化物特徵，並在第二S/D特徵的剩餘部分之上形成第二矽化物特徵。
在另一示例性方面，本揭露涉及一種半導體裝置的形成方法。此方法包括提供一種結構，包括：基板；在基板之上的第一閘極結構和第二閘極結構；與第一閘極結構相鄰且 包括n-型摻雜矽的第一源極/汲極(S/D)特徵；與第二閘極結構相鄰且包括矽鍺的第二S/D特徵；以及在第一和第二閘極結構的側壁之上及第一和第二S/D特徵之上的一層或多層介電層。此方法還包括蝕刻一層或多層介電層以暴露第一和第二S/D特徵，藉由相同的摻雜製程摻雜p-型摻質至第一和第二S/D特徵，以得到第一S/D特徵的p-型摻雜部分和第二S/D特徵的p-型摻雜部分；以及在摻雜p-型摻質之後，藉由相同的蝕刻製程部分地蝕刻第一和第二S/D特徵，其中比起使第二S/D特徵凹陷，選擇性蝕刻製程以較快的速度使第一S/D特徵凹陷。
在此方法的一實施例中，p-型摻質包含硼且摻雜製程使用範圍為1keV至5keV的摻雜能量及範圍為1E15cm-2至1E16cm-2的摻質劑量。在此方法的另一實施例中，相同的蝕刻製程完全地移除第一S/D特徵的p-型摻雜部分，且部分地移除第二S/D特徵的p-型摻雜部分。在此方法的一實施例中，相同的蝕刻製程包括具有SF6、H2、及CF4的氣體混合物的乾蝕刻。在此方法的另一實施例中，相同的蝕刻製程包括具有NH4OH或TMAH的濕蝕刻。
在一實施例中，在部分蝕刻第一和第二S/D特徵之後，此方法還包括活化位於第二S/D特徵中的p-型摻質。在另一實施例中，在活化p-型摻質之後，此方法還包括使用乾式清洗製程或濕式清洗製程來清潔第一和第二S/D特徵的頂表面，從而形成第一矽化物特徵於第一S/D特徵之上，並形成第二矽化物特徵於第二S/D特徵之上。
在另一示例性方面，本揭露涉及一種半導體裝置 的形成方法。此方法包括提供一種結構，包括：基板；於基板之上的第一閘極結構；夾著第一閘極結構的包括磷摻雜矽的兩個第一源極/汲極(S/D)特徵；在基板之上的第二閘極結構；夾著第二閘極結構的包括矽鍺的兩個第二S/D特徵；在第一和第二閘極結構的側壁之上的閘極間隔層；以及閘極間隔層之上及第一和第二S/D特徵之上的一層或多層介電層。此方法還包括蝕刻一層或多層介電層以形成暴露出第一和第二S/D特徵的開口；在開口中形成保護側壁；藉由相同的摻雜製程將硼摻雜到第一和第二S/D特徵，以得到第一S/D特徵的硼摻雜部分和第二S/D特徵的摻硼部分；並且在摻雜硼之後，藉由相同的蝕刻製程蝕刻第一和第二S/D特徵，其中蝕刻製程完全移除第一S/D特徵的硼摻雜部分且部分移除第二S/D特徵的硼摻雜部分。在一實施例中，在蝕刻第一和第二S/D特徵之後，此方法還包括對第一和第二S/D特徵進行退火。
在一示例性方面，本揭露涉及一種方法。此方法包括提供一種結構，其包括：基板；在基板上的第一閘極結構和第二閘極結構；在第一和第二閘極結構的側壁之上的間隔層；在基板上的第一源極/汲極(S/D)特徵和第二S/D特徵，其中第一S/D特徵與第一閘極結構相鄰，第二S/D特徵與第二閘極結構相鄰，且第一和第二S/D特徵包括不同的材料；在間隔層的側壁之上及第一和第二S/D特徵之上的蝕刻停止層；以及在蝕刻停止層之上的氧化物層。此方法還包括在結構之上形成罩幕層，此罩幕層具有直接位於第一和第二S/D特徵上的開口；透過開口蝕刻氧化物層和蝕刻停止層以暴露第一和第二S/D特徵； 透過開口摻雜p-型摻質至第一和第二S/D特徵；以及在摻雜p-型摻質之後，對第一和第二S/D特徵實施蝕刻製程，其中比起使第二S/D特徵凹陷，蝕刻製程更快地使第一S/D特徵凹陷。
在一實施例中，在蝕刻氧化物層和蝕刻停止層之後及在摻雜p-型摻質之前，此方法還包括在第一和第二S/D特徵之上及在開口的側壁上沉積包括氮化矽的介電層；以及蝕刻介電層以暴露第一和第二S/D特徵，且保留一部分的介電層於開口的側壁上。在另一實施例中，在對第一和第二S/D特徵實施蝕刻製程之後，此方法還包括活化位於第二S/D特徵中的p-型摻質。在另一實施例中，在活化之後，此方法還包括在第一和第二S/D特徵的剩餘部分之上沉積金屬。
在另一示例性方面，本揭露涉及一種方法。此方法包括提供一種結構，包括：基板；在基板之上的第一磊晶特徵和第二磊晶特徵，其中第一和第二磊晶特徵包括不同的半導體材料；以及在第一和第二磊晶特徵之上的一層或多層介電層。此方法還包括在結構之上形成罩幕層，此罩幕層具有直接位於第一和第二磊晶特徵上的開口；透過開口蝕刻一層或多層介電層以暴露第一和第二磊晶特徵；在開口中形成保護側壁；透過開口摻雜p-型摻質至第一和第二磊晶特徵，以得到第一磊晶特徵中的第一摻雜部分和第二磊晶特徵中的第二摻雜部分；以及對第一和第二磊晶特徵實施選擇性蝕刻製程，其中選擇性蝕刻製程完全移除第一摻雜部分並部分地移除第二摻雜部分。
在此方法的一實施例中，第一磊晶特徵包括磷摻雜矽，第二磊晶特徵包括矽鍺，並且p-型摻質包括硼。在另一 實施例中，選擇性蝕刻製程包括使用SF6、H2和CF4的氣體混合物的乾蝕刻製程。在另一實施例中，選擇性蝕刻製程包括使用NH4OH或TMAH的濕蝕刻製程。
在另一示例性方面，本揭露涉及一種半導體裝置。半導體裝置包括n-型FinFET區域，包括：第一閘極堆疊；在第一閘極堆疊的側壁之上的第一閘極間隔；以及在n-型FinFET區域的源極/汲極(S/D)區域中的n-型磊晶特徵。半導體裝置還包括p-型FinFET區域，包括：第二閘極疊層；在第二閘極堆疊的側壁之上的第二閘極間隔；以及在p-型FinFET區域的S/D區域中的p-型磊晶特徵。第一閘極間隔物的底表面和n-型磊晶特徵的上表面的最低點之間的第一垂直距離大於第二閘極間隔物的底表面和p-型磊晶特徵上表面的最低點之間的第二垂直距離。在半導體裝置的一實施例中，第一垂直距離大於第二垂直距離至少5奈米。
前述內文概述了許多實施例的特徵，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本揭露已以數個較佳實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者， 在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (11)

  1. 一種半導體裝置之形成方法，該方法包括：提供一結構，包括：一基板；一第一閘極結構和一第二閘極結構，位於該基板之上；一第一源極/汲極(S/D)特徵和一第二S/D特徵，位於該基板之上，其中該第一S/D特徵與該第一閘極結構相鄰，該第二S/D特徵與該第二閘極結構相鄰，且該第一和第二S/D特徵包括不同的材料；一第一介電層，位於該第一和第二閘極結構的側壁之上且位於該第一和第二S/D特徵之上；一第二介電層，位於該第一介電層之上；蝕刻該第一和第二介電層以暴露該第一和第二S/D特徵；摻雜一p-型摻質至該第一和第二S/D特徵；以及在摻雜該p-型摻質之後，對該第一和第二S/D特徵實施一選擇性蝕刻製程，其中比起使該第二S/D特徵凹陷，該選擇性蝕刻製程較快地使該第一S/D特徵凹陷。
  2. 如申請專利範圍第1項所述之半導體裝置之形成方法，其中該第一S/D特徵包括摻雜有一n-型摻質的矽或矽-碳，且該第二S/D特徵包括矽鍺，其中該n-型摻質為磷或砷且該p-型摻質為硼。
  3. 如申請專利範圍第2項所述之半導體裝置之形成方法，其中該選擇性蝕刻製程包括使用SF6、H2、及CF4的一氣體混合物之一乾蝕刻製程，或者該選擇性蝕刻製程包括使用NH4OH或TMAH之一濕蝕刻製程。
  4. 如申請專利範圍第1項所述之半導體裝置之形成方法，在該蝕刻該第一和第二介電層之後及在該摻雜該p-型摻質之前，更包括：沉積一第三介電層於該結構之上；以及對該第三介電層實施一非等向性蝕刻製程以暴露該第一和第二S/D特徵並保留一部分的該第三介電層於該第一和第二閘極結構的側壁之上。
  5. 如申請專利範圍第1項所述之半導體裝置之形成方法，在實施該選擇性蝕刻製程之後，更包括：對位於該第二S/D特徵中的該p-型摻質進行退火；或者在實施該選擇性蝕刻製程之前，更包括：對位於至少該第二S/D特徵中的該p-型摻質進行退火。
  6. 如申請專利範圍第1項所述之半導體裝置之形成方法，在實施該選擇性蝕刻製程之後，更包括：沉積一金屬於該第一和第二S/D特徵的剩餘部分之上；以及在實施該選擇性蝕刻製程之後及在該沉積該金屬之前，更包括：形成一第一矽化物特徵於該第一S/D特徵的該剩餘部分之上；以及形成一第二矽化物特徵於該第二S/D特徵的該剩餘部分之上。
  7. 一種半導體裝置之形成方法，該方法包括：提供一結構，包括：一基板；一第一閘極結構和一第二閘極結構，位於該基板之上；一第一源極/汲極(S/D)特徵，包括n-型摻雜矽，與該第一閘極結構相鄰；一第二S/D特徵，包括矽鍺，該第二閘極結構相鄰；一層或多層介電層，位於該第一和第二閘極結構的側壁之上且位於該第一和第二S/D特徵之上；蝕刻該一層或多層介電層以暴露該第一和第二S/D特徵；藉由一相同的摻雜製程摻雜一p-型摻質至該第一和第二S/D特徵，以得到該第一S/D特徵的一p-型摻雜部分和該第二S/D特徵的一p-型摻雜部分；以及在摻雜該p-型摻質之後，藉由一相同的蝕刻製程部分地蝕刻該第一和第二S/D特徵，其中比起使該第二S/D特徵凹陷，該選擇性蝕刻製程以一較快的速度使該第一S/D特徵凹陷。
  8. 如申請專利範圍第7項所述之半導體裝置之形成方法，其中該相同的蝕刻製程完全地移除該第一S/D特徵的該p-型摻雜部分且部分地移除該第二S/D特徵的該p-型摻雜部分。
  9. 如申請專利範圍第7項所述之半導體裝置之形成方法，其中該相同的蝕刻製程包括具有SF6、H2、及CF4的一氣體混合物之一乾蝕刻，或者該相同的蝕刻製程包括具有NH4OH或TMAH之一濕蝕刻。
  10. 如申請專利範圍第7項所述之半導體裝置之形成方法，在該部分地蝕刻該第一和第二S/D特徵之後，更包括：活化位於該第二S/D特徵中的該p-型摻質；以及在該活化該p-型摻質之後，更包括：使用一乾式清洗製程或一濕式清洗製程來清潔該第一和第二S/D特徵的一頂表面；形成一第一矽化物特徵於該第一S/D特徵之上；以及形成一第二矽化物特徵於該第二S/D特徵之上。
  11. 一種半導體裝置，包括：一n-型FinFET區域，包括：一第一閘極堆疊；一第一閘極間隔，位於該第一閘極堆疊的側壁之上；一n-型磊晶特徵，位於該n-型FinFET區域的一源極/汲極(S/D)區域中；以及一p-型FinFET區域，包括：一第二閘極堆疊；一第二閘極間隔，位於該第二閘極堆疊的側壁之上；以及一p-型磊晶特徵，位於該p-型FinFET區域的一源極/汲極(S/D)區域中；其中該第一閘極間隔的一底表面與該n-型磊晶特徵的一凹陷上表面的一最低點之間的一第一垂直距離大於該第二閘極間隔的一底表面與該p-型磊晶特徵的一凹陷上表面的一最低點之間的一第二垂直距離。
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