TWI677097B - 具有多終端電晶體佈局的半導體元件 - Google Patents
具有多終端電晶體佈局的半導體元件 Download PDFInfo
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- TWI677097B TWI677097B TW106131487A TW106131487A TWI677097B TW I677097 B TWI677097 B TW I677097B TW 106131487 A TW106131487 A TW 106131487A TW 106131487 A TW106131487 A TW 106131487A TW I677097 B TWI677097 B TW I677097B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 239000000758 substrate Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 24
- 239000010409 thin film Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 1
Classifications
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Abstract
本揭露係關於一種半導體元件。該半導體元件包含一閘極區域、一源極/汲極區域、以及位於該閘極區域與該源極/汲極區域之間的一絕緣層。該源極/汲極區域包含延伸於一第一方向的一第一區段、延伸平行於該第一區段的一第二區段、以及連接於該第一區段與該第二區段之間的一第三區段。
Description
本揭露係關於一種具有多終端電晶體佈局的半導體元件。
大部分電晶體的簡化構造具有三個主要組件,稱為絕緣層、半導體層以及電極,電極包含源極、汲極與閘極電極。源極接點與汲極接點係直接與半導體層接觸,而閘極接點係藉由絕緣層而與半導體層分離。可使用許多不同的結構佈局製造電晶體。
本揭露的實施例提供一種半導體元件。該半導體元件包含一閘極區域、一源極/汲極區域以及位於該閘極區域與該源極/汲極區域之間的一絕緣層。該源極/汲極區域包含延伸於一第一方向的一第一區段、延伸平行於該第一區段的一第二區段、以及連接於該第一區段與該第二區段之間的一第三區段。 在一實施例中,該第三區段延伸於一第二方向,該第二方向不同於該第一方向。例如,該第二方向垂直於該第一方向。 在另一實施例中,該源極/汲極區域包含一第一源極/汲極終端、一第二源極/汲極終端以及一第三源極/汲極終端。這些終端未與該閘極區域重疊。 在另一實施例中,該第一源極/汲極終端與該閘極區域定義一第一電晶體,該第二源極/汲極終端與該閘極區域定義一第二電晶體,以及該第三源極/汲極終端與該閘極區域定義一第三電晶體。 在另一實施例中,該第三區段的一端部連接至該第二區段的一端部。 在另一實施例中,該半導體元件另包含一第四源極/汲極終端。再者,該第四源極/汲極終端與該閘極區域定義一第四電晶體。 在一實施例中,第三區段位置接近該第一區段與該第二區段上的源極/汲極終端,並與該第一區段與該第二區段上的該源極/汲極終端一起定義一充電電流路徑。 在另一實施例中,該第三區段具有一駝峰形狀。 本揭露的一些實施例亦提供一種半導體元件。該半導體元件包含一閘極區域與一源極/汲極區域。該源極/汲極區域另包含一第一源極/汲極終端、一第二源極/汲極終端以及一第三源極/汲極終端。該第一、第二與第三源極/汲極終端彼此分離,並且該第一、第二與第三源極/汲極終端各自未與該閘極區域重疊。 在一實施例中,該第一源極/汲極終端與該閘極區域定義一第一電晶體,該第二源極/汲極終端與該閘極區域定義一第二電晶體,以及該第三源極/汲極終端與該閘極區域定義一第三電晶體。 在另一實施例中,該源極/汲極區域包含一第一區段,該第一區段於一第一方向自該第一源極/汲極終端延伸至該第二源極/汲極終端。 在另一實施例中,該源極/汲汲區域包含延伸平行於該第一區段的一第二區段,以及連接於該第一區段與該第二區段之間的一第三區段。 在另一實施例中,該第三區段的一端部連接至該第二區段的一端部。 在另一實施例中,該半導體元件另包含一第四源極/汲極終端,其未與該閘極區域重疊。再者,該第四源極/汲極終端與該閘極區域定義一第四電晶體。甚者,該第二區段自該第三源極/汲極終端延伸至該第四源極/汲極終端。
本揭露提供了數個不同的實施方法或實施例,可用於實現本發明的不同特徵。為簡化說明起見,本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範,而非予以任何限制。舉例而言,在以下說明第一特徵如何在第二特徵上或上方的敘述中,可能會包括某些實施例,其中第一特徵與第二特徵為直接接觸,而敘述中也可能包括其他不同實施例,其中第一特徵與第二特徵中間另有其他特徵,以致於第一特徵與第二特徵並不直接接觸。此外,本揭露中的各種範例可能使用重複的參考數字和/或文字註記,以使文件更加簡單化和明確,這些重複的參考數字與註記不代表不同的實施例與/或配置之間的關聯性。 再者,應理解當稱元件「連接至」或「耦合至」另一元件時,其可直接連接或耦合至另一元件,或是可有其他中間元件存在。 圖1A為示意圖,例示本揭露實施例之半導體元件10的佈局。 參閱圖1A,半導體元件10包含第一區域11與第二區域12。第一區域11位於第二區域12上方,作為半導體元件10中所定義之電晶體的閘極區域。源極區域12位於基板(未繪示)上或位於基板上方,作為電晶體的源極/汲極區域。將參照圖3A與圖3B詳細說明電晶體。 第一區域11包含閘極終端G,用於將半導體元件10中的電晶體經由互連結構(未繪示)電連接至偏壓來源(bias source)或其他元件,該互連結構可另包含導電通路與金屬層。再者,第二區域12包含源極/汲極終端SD1至SD4,對於電晶體而言,源極/汲極終端SD1至SD4未與閘極區域11重疊。 依照相關電晶體的形式以及施加於源極/汲極終端電壓位準,源極/汲極終端SD1至SD4可各自做為源極終端或汲極終端。 圖1B為示意圖,例示本揭露實施例圖1所示之半導體元件10的源極/汲極區域12。 參閱圖1B,源極/汲極區域12包含第一區段(leg)21、第二區段22與第三區段23。第一區段21於第一源極/汲極終端SD1與第二源極/汲極SD2之間實質延伸於第一方向。第二區段22與第一區段21分離,實質延伸且與於第三源極汲極終端SD3與第四源極/汲極終端SD4之間的第一區段21平行。延伸於第二方向的第三區段23係連接於第一區段21與第二區段22之間,其中第二方向不同於第一方向。在本實施例中,第二方向實質上與第一方向垂直。 圖2A、2B、2C與2D分別為沿著圖1A之線AA、BB、CC與DD說明半導體元件10的剖面圖。 參閱圖2A,例如,半導體元件10包含絕緣層25,為求簡潔,未繪示於圖1A中。絕緣層25位於閘極區域11與源極/汲極區域12之間。此外,由於閘極區域11位於源極/汲極區域12上方,半導體元件10具有「頂部閘極(top-gate)」結構,半導體元件10中的電晶體稱為「頂部閘極電晶體(top-gate transistor)」。在頂部閘極結構中,源極/汲極區域12位於閘極區域11與半導體元件10的基板之間。 圖3A為電路圖,例示本揭露實施例之圖1A所示半導體元件10的p型電晶體T1至T5。 參閱圖3A與圖1B,以第一區段21的第一源極/汲極SD1、第三區段23與閘極區域11定義第一電晶體T1。此外,以第一區段21的第二源極/汲極SD2、第三區段23與閘極區域11定義第二電晶體T2。同樣地,以第二區段22的第三源極/汲極SD3、第三區段23與閘極區域11定義第三電晶體T3。再者,以第二區段22的第四源極/汲極SD4、第三區段23與閘極區域11定義第四電晶體T4。甚者,以第三區段23與閘極區域11定義第五電晶體T5。電晶體T1至T5共用閘極終端G。 電晶體T1至T5可各自包含薄膜電晶體(thin film transistor,TFT)或金屬氧化物半導體(metal-oxide-semiconductor,MOS)電晶體。以TFT為例,半導體元件10包含半導體層,該半導體層可與源極/汲極區12共平面或交錯。為求簡潔,圖1A或1B未繪示此半導體層。 圖3B為電路圖,例示本揭露實施例之圖1A所示半導體元件10的n型電晶體T1至T5。 參閱圖3B,電晶體T1至T5類似於圖3A所示與所述之電晶體,差別在於例如,圖3B所示之這些電晶體T1至T5為n型電晶體。 與佈局中具有一個源極終端和一個汲極終端的一些現有的半導體元件不同,半導體元件10包含超過兩個源極/汲極終端。在本實施例中,半導體元件10包含四個源極/汲極終端SD1、SD2、SD3與SD4。然而,在其他的實施例中,半導體元件10可包含超過兩個平行區段,因而具有超過四個源極/汲極終端。由於具有多個源極/汲極終端,半導體元件的佈局較為彈性,可有助於複雜的電路設計並且有利於面積成本(area cost)。 圖4為示意圖,例示本揭露實施例之半導體元件40的佈局。 參閱圖4,半導體元件40類似於圖1A所示與所述之半導體元件10,差別在於例如,閘極區域11係位於源極/汲極區域12下方。 圖5A、5B、5C與5D分別為沿著圖4之線AA、BB、CC與DD說明半導體元件40的剖面圖。 參閱圖5A,例如,半導體元件40包含絕緣層25,為求簡潔,未繪示於圖4中。絕緣層25位於閘極區域11與源極/汲極區域12之間。由於閘極區域11位於源極/汲極區域12下方,半導體元件40具有「底部閘極(bottom-gate)」結構,半導體元件10中的電晶體稱為「底部閘極電晶體(bottom-gate transistor)」。在底部閘極結構中,閘極區域11位於源極/汲極區域12與半導體元件40的基板之間。半導體元件40的電路結構類似於圖3A或3B所示與所述之電路結構。此外,該等電晶體各自可包含薄膜電晶體(TFT)。 圖6A為示意圖,例示本揭露實施例之半導體元件60的佈局。 參閱圖6A,半導體元件60類似於圖1A所示與所述之半導體元件10,差別在於例如,源極/汲極區域62不存在第四源極/汲極SD4。因此,在本實施例中,半導體元件60包含三個源極/汲極終端SD1、SD2與SD3。 圖6B為示意圖,例示本揭露實施例圖6A所示之半導體元件60的源極/汲極區域62。 參閱圖6B,源極/汲極區域62類似於圖1A所示與所述之半導體元件10的源極/汲極區域12。特別地,除了第一區段21與第三區段23之外,源極/汲極區域62包含第二區段72。再者,第三區段23的一端部連接至第二區段72的一端部。 圖7A至7F分別為沿著圖6A之線AA至FF說明半導體元件60的剖面圖。 參閱圖7A,例如,半導體元件60包含絕緣層25,為求簡潔,未繪示於圖6A中。絕緣層25係位於閘極區域11與源極/汲極區域62之間。由於閘極區域11位於源極/汲極區域62上方,因而半導體元件60具有頂部閘極結構,半導體元件60中的電晶體稱為頂部閘極電晶體。 圖8A為電路圖,例示本揭露實施例之圖6A所示半導體元件60的p型電晶體T1至T3與T5。 參閱圖8A,電路類似於圖3A所示與所述之電路,差別在於由於源極/汲極區域62不存在第四源極/汲極SD4,因而沒有第四電晶體T4。 圖8B為電路圖,例示本揭露實施例之圖6A所示半導體元件60的n型電晶體T1至T3與T5。 參閱圖8,電晶體T1至T3與T5類似於圖8A的電晶體T1至T3與T5,差別在於例如圖8所示的這些電晶體T1至T3與T5係n型電晶體。 圖9為示意圖,例示本揭露實施例之半導體元件90的佈局。 參閱圖9,半導體元件90類似於圖6A所示與所述之半導體元件60,差別在於例如,閘極區域11位於源極/汲極區域62下方。 圖10A至10F分別為沿著圖9之線AA至FF說明圖9之半導體元件90的剖面圖。 參閱圖10A,例如,半導體元件90包含絕緣層25,為求簡潔,其未繪示於圖9中。絕緣層25位於閘極區域11與源極/汲極區域62之間。由於閘極區域11位於源極/汲極區域6下方,因而半導體元件90具有底部閘極結構,並且半導體元件90中的電晶體為底部閘極電晶體。半導體元件90的電路結構類似於圖8A或8B所示與所述之電路結構。此外,各個電晶體可包含薄膜電晶體(TFT)。 圖11為示意圖,例示本揭露實施例之半導體元件110中的充電路徑CP1與驅動路徑DP1。 參閱圖11,半導體元件110類似於圖1A所示與所述之半導體元件10,差別在於例如,半導體元件110的第三區段123之位置不同於半導體元件10的第三區段23。具體而言,第三區段123位置接近終端SD1與SD3並且遠離終端SD2與SD4。因此,自終端SD1通過第三區段123至終端SD3的充電路徑CP1係短於自終端SD4通過第三區段123至終端SD2的驅動路徑DP1。例如,半導體元件110可操作於初始化階段(initialization phase)、充電階段與驅動階段。在充電階段過程中,充電電流流至充電路徑CP1中的半導體元件110中。相對地,在驅動階段過程中,驅動電流自驅動電路DP1中的半導體元件110流出。該技藝中具有通常技術者可理解就考量充電而言,需要具有期望程度的大電流,而不論充電電流是否均勻。相對地,就考量驅動而言,需要具有期望電流密度的均勻電流,而不論驅動電流是否為強電流。再者,較短的電流路徑有利於充電電流,而較長的電流路徑有利於驅動電流。 在本實施例中,第一區段121與第二區段122的終端SD1及SD3分別用於充電操作,而第一區段121與第二區段122的終端SD2及SD4分別用於驅動操作。由於第三區段123位置接近與充電操作相關的終端SD1與SD3,因而充電路徑CP1短於驅動路徑DP1,此有利於半導體元件110的充電與驅動操作。 在一些實施例中,終端SD1與SD3可用於驅動操作,而終端SD2與SD4用於充電操作。在此情況下,第三區段123位置接近充電路徑上的終端SD2與SD4,並且遠離驅動路徑上的終端SD1與SD3。 雖然本揭露說明頂部閘極結構,然而本揭露關於比驅動路徑更靠近充電路徑的第三區段的實施例可應用於底部閘極結構。 圖12為示意圖,例示本揭露另一實施例之半導體元件10中的充電路徑CP2與驅動路徑DP2。 參閱圖12,半導體元件120類似於圖11所示與所述之半導體元件110,差別在於例如,半導體元件120的第三區段223之形狀不同於半導體元件110的第三區段123。在本實施例中,第三區段223的形狀如駝峰(hump)。此外,第三區段223的「駝峰」比驅動路徑DP2上的終端SD2與SD4更接近充電路徑CP2上的終端SD1與SD3。在其他的實施例中,第三區段223為任意形狀,只要有相對短的充電路徑與相對長的驅動路徑存在即可。有利的是,如圖11所示之半導體元件110的第三區段123,達成較短的充電路徑與較長的驅動路徑,分別造成較大的充電電流與較均勻的驅動電流。 前述內容概述一些實施方式的特徵,因而熟知此技藝之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎,用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍,並且熟知此技藝之人士可進行各種變化、取代與替換,而不脫離本揭露之精神與範圍。
10‧‧‧半導體元件
11‧‧‧第一區域
12‧‧‧第二區域
21‧‧‧第一區段
22‧‧‧第二區段
23‧‧‧第三區段
25‧‧‧絕緣層
40‧‧‧半導體元件
60‧‧‧半導體元件
62‧‧‧源極/汲極區域
72‧‧‧第二區段
90‧‧‧半導體元件
110‧‧‧半導體元件
120‧‧‧半導體元件
121‧‧‧第一區段
122‧‧‧第二區段
123‧‧‧第三區段
223‧‧‧第三區段
SD1‧‧‧第一源極/汲極終端
SD2‧‧‧第二源極/汲極終端
SD3‧‧‧第三源極/汲極終端
SD4‧‧‧第四源極/汲極終端
AA‧‧‧線
BB‧‧‧線
CC‧‧‧線
DD‧‧‧線
EE‧‧‧線
FF‧‧‧線
G‧‧‧閘極終端
T1‧‧‧第一電晶體
T2‧‧‧第二電晶體
T3‧‧‧第三電晶體
T4‧‧‧第四電晶體
T5‧‧‧第五電晶體
CP1‧‧‧充電路徑
CP2‧‧‧充電路徑
DP1‧‧‧驅動路徑
DP2‧‧‧驅動路徑
為協助讀者達到最佳理解效果,建議在閱讀本揭露時同時參考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作法,本專利說明書中的圖式不一定按照正確的比例繪製。在某些圖式中,尺寸可能刻意放大或縮小,以協助讀者清楚了解其中的討論內容。 圖1A為示意圖,例示本揭露實施例之半導體元件的佈局。 圖1B為示意圖,例示本揭露實施例之圖1A所示半導體元件的源極與汲極區域。 圖2A至2D分別為沿著圖1A之線AA至DD說明半導體元件的剖面圖。 圖3A為電路圖,例示本揭露實施例之圖1A所示半導體元件的p型電晶體。 圖3B為電路圖,例示本揭露實施例之圖1A所示半導體元件的n型電晶體。 圖4為示意圖,例示本揭露實施例之半導體元件的佈局。 圖5A至5D分別為沿著圖4之線AA至DD說明半導體元件的剖面圖。 圖6A為示意圖,例示本揭露實施例之半導體元件的佈局。 圖6B為示意圖,例示本揭露實施例之圖6A所示半導體元件的源極與汲極區域。 圖7A至7F分別為沿著圖6A之線AA至FF說明半導體元件的剖面圖。 圖8A為電路圖,例示本揭露實施例之圖6A所示半導體元件的p型電晶體。 圖8B為電路圖,例示本揭露實施例之圖6A所示半導體元件的n型電晶體。 圖9為示意圖,例示本揭露實施例之半導體元件的佈局。 圖10A至10F分別為沿著圖9之線AA至FF說明半導體元件的剖面圖。 圖11為示意圖,例示本揭露實施例之半導體元件的充電路徑與驅動路徑。 圖12為示意圖,例示本揭露實施例之半導體元件的充電路徑與驅動路徑。
Claims (20)
- 一種半導體元件,包括:一閘極區域;一源極/汲極區域;以及一絕緣層,位於該閘極區域與該源極/汲極區域之間;其中該源極/汲極區域包含延伸於一第一方向的一第一區段,延伸平行於該第一區段的一第二區段,以及連接於該第一區段與該第二區段之間的一第三區段;該源極/汲極區域包含未與該閘極區域重疊的一第一源極/汲極終端、一第二源極/汲極終端以及一第三源極/汲極終端。
- 如請求項1所述之半導體元件,其中該第三區段延伸於一第二方向,該第二方向不同於該第一方向。
- 如請求項2所述之半導體元件,其中該第二方向垂直於該第一方向。
- 如請求項2所述之半導體元件,其中該第三區段的一端部在該第一區段兩端之間的位置與該第一區段相接。
- 如請求項1所述之半導體元件,其中該第一源極/汲極終端與該閘極區域定義一第一電晶體,該第二源極/汲極終端與該閘極區域定義一第二電晶體,以及該第三源極/汲極終端與該閘極區域定義一第三電晶體。
- 如請求項1所述之半導體元件,其中該第三區段的一端部連接至該第二區段的一端部。
- 如請求項1所述之半導體元件,另包括一第四源極/汲極終端。
- 如請求項7所述之半導體元件,其中該第四源極/汲極終端與該閘極區域定義一第四電晶體。
- 如請求項1所述之半導體元件,其中該第三區段位置接近該第一區段與該第二區段上的源極/汲極終端,並與該第一區段與該第二區段上的該源極/汲極終端一起定義一充電電流路徑。
- 如請求項9所述之半導體元件,其中該第三區段具有一駝峰形狀。
- 一種半導體元件,包括:一閘極區域;以及一源極/汲極區域,包括:一第一源極/汲極終端;一第二源極/汲極終端;以及一第三源極/汲極終端,其中該第一、第二與第三源極/汲極終端彼此分離,並且該第一、第二與第三源極/汲極終端各自未與該閘極區域重疊;該源極/汲極區域包含一第一區段、延伸平行於該第一區段的一第二區段,以及連接於該第一區段與該第二區段之間的一第三區段。
- 如請求項11所述之半導體元件,其中該第一源極/汲極終端與該閘極區域定義一第一電晶體,該第二源極/汲極終端與該閘極區域定義一第二電晶體,以及該第三源極/汲極終端與該閘極區域定義一第三電晶體。
- 如請求項11所述之半導體元件,其中該源極/汲極區域包含一第一區段,該第一區段於一第一方向自該第一源極/汲極終端延伸至該第二源極/汲極終端。
- 如請求項11所述之半導體元件,其中該第三區段的一端部在該第一區段兩端之間的位置與該第一區段相接。
- 如請求項11所述之半導體元件,其中該第三區段的一端部連接至該第二區段的一端部。
- 如請求項11所述之半導體元件,另包括一第四源極/汲極終端,該第四源極/汲極終端未與該閘極區域重疊。
- 如請求項16所述之半導體元件,其中該第二區段自該第三源極/汲極終端延伸至該第四源極/汲極終端。
- 如請求項16所述之半導體元件,其中該第四源極/汲極終端與該閘極區域定義一第四電晶體。
- 如請求項11所述之半導體元件,其中該源極/汲極區域位於該閘極區域與該半導體元件的一基板之間。
- 如請求項11所述之半導體元件,其中該閘極區域位於該源極/汲極區域與該半導體元件的一基板之間。
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