CN108074530B - 补偿电路与包含所述补偿电路的电致发光显示器 - Google Patents

补偿电路与包含所述补偿电路的电致发光显示器 Download PDF

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CN108074530B
CN108074530B CN201710797114.7A CN201710797114A CN108074530B CN 108074530 B CN108074530 B CN 108074530B CN 201710797114 A CN201710797114 A CN 201710797114A CN 108074530 B CN108074530 B CN 108074530B
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transistors
transistor
capacitor
terminal
coupled
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CN108074530A (zh
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郑士嵩
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Taizhou Guanyu Technology Co.,Ltd.
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INT Tech Co Ltd
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Abstract

一种补偿电路包含一电容器、一电致发光EL装置、一第一组晶体管及一第二组晶体管。上述第一组晶体管耦接于所述电容器的一第一端和一数据输入间，其是用以回应在该数据输入所接收的数据而提供一补偿电压。所述的补偿电压是由所述第一组晶体管中每一晶体管的阈值电压所构成。上述第二组晶体管耦接于所述EL装置和电容器的一第二端间，其是用以将一电流传送通过该EL装置。所述电流的强度与所述第二组晶体管中每一晶体管的阈值电压无关。

Description

补偿电路与包含所述补偿电路的电致发光显示器
技术领域
本发明涉及像素单元，特别是包含补偿电路的像素单元，以及包含此种像素单元的电致发光显示器。
背景技术
电致发光(EL)显示器，譬如主动矩阵有机发光二极管(active matrix organiclight emitting diode，AMOLED)显示器，可包含一像素阵列。此外，所述像素中的每一像素可包含一电致发光(EL)装置、用以传输含有与亮度相关的信息的一开关晶体管、以及用以驱动该EL装置使其根据该数据而发光的一驱动晶体管。虽然此种EL显示器具备电力消耗较低的优点，但半导体制备过程中的制程因素却可能使多个像素间的显示不均匀。因此，相关领域需要一种能够解决上述问题的电路。
发明内容
本发明的实施例提出一种补偿电路，其包含一电容器、一电致发光(EL)装置、一第一组晶体管及一第二组晶体管。该第一组晶体管耦接于该电容器的第一端和一数据输入间，其是用以回应在该数据输入所接收的数据而提供一补偿电压。该补偿电压是由该第一组晶体管中每一晶体管的阈值电压所构成。该第二组晶体管耦接于该EL装置和电容器的第二端间，其是用以使一电流流经该EL装置。该电流的强度与该第二组晶体管中每一晶体管的阈值电压无关。
于一实施例中，该第一组晶体管中每一晶体管的一栅极耦接至该电容器的该第一端。
于另一实施例中，该第二组晶体管中每一晶体管的一栅极耦接至该电容器的该第一端。
于又一实施例中，该第一组晶体管包含一第一晶体管、一第二晶体管及一第三晶体管。此外，该补偿电压是该第一、第二与第三晶体管的阈值电压总和。
在又另一实施例中，该第二组晶体管包含该第一晶体管、一第四晶体管及一第五晶体管。此外，该补偿电压是该第一、第四与第五晶体管的阈值电压总和。
在一实施例中，该电路还包含另一晶体管，用以回应一第一控制信号，以重置位于该电容器第一端的一电压电平。
在另一实施例中，该电路还包含数个晶体管，用以回应一第二控制信号，以通过该第一组晶体管而使该数据储存于该电容器中。
在又另一实施例中，该电路还包含数个晶体管，用以回应一第三控制信号，以使该电流通过该第二组晶体管而流经该EL装置。
在一实施例中，该第一组晶体管中每一晶体管及该第二组晶体管中每一晶体管分别包含一p-型晶体管。
在另一实施例中，该第一组晶体管中每一晶体管及该第二组晶体管中每一晶体管分别包含一n-型晶体管。
本发明的某些实施例提供一电致发光显示器，其包含一像素单元阵列，其中的每一像素单元包含一电容器、一电致发光(EL)装置、一第一组晶体管及一第二组晶体管。该第一组晶体管耦接于该电容器的第一端和一数据输入间，其是用以回应在该数据输入所接收的数据而提供一补偿电压。该补偿电压是由该第一组晶体管中每一晶体管的阈值电压所构成。该第二组晶体管耦接于该EL装置和电容器的第二端间，其是用以使一电流流经该EL装置。该电流的强度与该第二组晶体管中每一晶体管的阈值电压无关。
本发明的实施例亦提供一种电致发光(EL)显示器的电压补偿方法。该EL显示器包含多个像素，所述像素单元各包含一电容器、一EL装置、一第一组晶体管及一第二组晶体管。根据此种方法，于一第一阶段中，重置位于该电容器的第一端的电压电平。在一第二阶段中，将一数据储存于该电容器中。该数据是通过该第一组晶体管所接收。再者，于该第二阶段中，产生一补偿电压，其是由该第一组晶体管中每一晶体管的阈值电压所构成。更有甚者，于一第三阶段中，使一电流通过该第二组晶体管而流经该EL装置。该电流的强度与该第二组晶体管中每一晶体管的阈值电压无关。
附图说明
在阅读了下文实施方式以及附随附图时，能够最佳地理解本公开的多种实施方式。应注意到，根据本领域的标准作业习惯，图中的各种特征并未依比例绘制。事实上，为了能够清楚地进行描述，可能会刻意地放大或缩小某些特征的尺寸。
图1为根据一实施例的显示器的区域图。
图2为图1所示显示器中一子像素单元的电路图。
图3A及3B示出的根据某些实施例，于第一阶段中操作图2所示电路的方法。
图4A及4B示出的根据某些实施例，于第二阶段中操作图2所示电路的方法。
图5A及5B示出的根据某些实施例，于第三阶段中操作图2所示电路的方法。
图6A为根据另一实施例，一显示器中一子像素单元的电路图。
图6B为根据某些实施例，用以操作图6A所示电路的控制信号的波形图。
图7为流程图，其示出的在一电致发光显示器中进行电压补偿的方法。
附图标记说明：
10 显示器
12 主动区域
14 栅极驱动器
15 源极驱动器
16 电源驱动器
18 DC偏压源
20 子像素单元
28 EL装置
71～77 步骤
A 节点
C1 电容器
DATA 数据
Isd 电流
M 行
N 列
P 像素单元
S1、S2、EM 信号
t1、t2、t3 时间点
T1～T10 晶体管
VDD 工作电压
Vref 参考电压
VSS 接地电压
具体实施方式
以下公开内容提供了多种实施方式或例示，其能用以实现本公开内容的不同特征。下文所述的元件与配置的具体例子是用以简化本公开内容。当可想见，这些叙述仅为例示，其本意并非用于限制本公开内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包含某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包含某些实施例其中还有而外的元件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本公开内容可能会在多个实施例中重复使用元件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
此外，当可理解，若将一部件描述为与另一部件「连接(connected to)」或「耦接(耦接至)」，则两者可直接连接或耦接，或两者间可能出现其他中间(intervening)部件。
在下文说明中，当一装置属于正缘触发(active high)，将一信号拉高(asserted)至高逻辑值，以启动该相应装置。反之，将该信号拉低(deasserted)至低逻辑值，以停用该相应装置。然而当该装置属于负缘触发(active low)时，将该信号拉至低逻辑值，以启动该装置，并将其拉至高逻辑值，以停用该装置。
图1为根据一实施例的显示器10的区域图。显示器10可以是一电致发光(EL)显示器，譬如主动矩阵有机发光二极管(AMOLED)显示器，但并不以此为限。
参照图1，显示器10包含主动区域12、栅极驱动器14及源极驱动器15。主动区域12包含一像素单元阵列，举例来说，可将多个像素单元P排列成N×M的矩阵。栅极驱动器14经由N条扫描线将控制信号S1、S2及EM提供给N列像素单元P。源极驱动器15将数据提供给M行像素单元P中的一所选像素。此外，一电源驱动器16在VDD及VSS的电源中提供供应电压至该主动区域12，而一DC偏压源18则提供一参考电压Vref，例如接地电压，至该主动区域12。在一实施例中，VDD约为5伏特(5V)，VSS约为-5V，而Vref则约为0V。
主动区域12中的每一像素单元P包含三个子像素单元，其可用以显示红色(R)、绿色(G)及蓝色(B)。在其他实施例中，例如，子像素渲染(sub-pixel rendering，SPR)感应器，子像素单元的数目不限于三。在本实施例中，三种子像素单元是沿着列的方向排列。因此，源极驱动器15的数据线数目为3×M。
图2是根据图1所示显示器10中一例示性子像素单元20的电路图。
参照图2，所述电路为一补偿电路，其包含一EL装置28、多个晶体管T1至T10及一电容器C1。举例来说，EL装置28包含一电流驱动部件，其可包含一有机发光二极管(organiclight emitting diode，OLED)、微LED或量子点LED(quantum dot LED，QLED)。电容器C1耦接于VDD和节点A之间，其可作为一储存电容器。在一实施例中，电容器C1的电容约为0.5微法拉(LED)。此外，级联(cascode)连接的晶体管T2、T5与T6作为驱动晶体管，其可根据储存于电容器C1中的数据来驱动EL装置28。在本实施例中，多个晶体管T1至T10中的每一个晶体管包含一p-型薄膜晶体管(thin film transistor、TFT)或一p-型金氧半(p-type metal-oxide-semiconductor，PMOS)晶体管。
晶体管T1的栅极用以接收控制信号S1。晶体管T1的漏极用以接收来自DC偏压源18的参考电压Vref。晶体管T1的源极耦接至节点A。本发明所述技术领域中技术人员当可理解，MOS晶体管的漏极与源极端可互换，其取决于施加于该处的电压电平。
再者，晶体管T2、T3、T4、T5与T6的栅极分别耦接至节点A。晶体管T2的源极耦接至晶体管T3与T5两者的漏极。晶体管T2的漏极耦接至晶体管T6与T4两者的源极。
除此之外，晶体管T7与T8两者的栅极接收控制信号S2。晶体管T7的源极在一相应数据线上接收来自源极驱动器15的数据(标记为"DATA")。晶体管T7的漏极耦接至晶体管T3的源极。此外，晶体管T8的源极耦接至晶体管T4的漏极。晶体管T8的漏极耦接至节点A。
又，晶体管T9与T10两者的栅极接收控制信号EM。晶体管T9的源极接收VDD。晶体管T9的漏极耦接至晶体管T5的源极。此外，晶体管T10的源极耦接至晶体管T6的漏极。晶体管T10的漏极耦接至EL装置28的阳极。EL装置28的阴极耦接至VSS。
图3A及3B示出的根据某些实施例，在第一阶段中，操作图2所示电路20的方法。
参照图3A，控制信号S1、S2及EM经设定为负缘触发。在时间点t1，将控制信号S1拉至负缘(falling edge)，而位于高逻辑电平的控制信号S2与EM则未经拉动。因此，参照图3B，晶体管T1被开启，而晶体管T7至T10则被关闭(图中以"×"符号标记)。由于晶体管T1是开启的，节点A的电压电平(下文标记为VA)被拉低至Vref。此外，由于晶体管T2至T6的栅极分别连接到节点A，在第一阶段中，分别将作为驱动晶体管的晶体管T2、T5与T6的栅极的电压电平(标记为Vg)重置为Vref。电容器C1用以将VA与Vg保持在Vref的电压电平。在第一阶段中能够有效地将VA与Vg重置为Vref。
图4A及4B示出的根据某些实施例，在第二阶段中，操作图2所示电路20的方法。
参照图4A，在时间点t2，将控制信号S2拉至负缘，而处于一高逻辑电平的控制信号S1与EM则未经拉动。如此一来，参照图4B，晶体管T1被关闭，而晶体管T7与T8则被开启。在第二阶段中，将晶体管T2、T3与T4保持在开启状态，这是因为其栅极在最初被偏压至Vref。由于晶体管T7与T8被开启，可通过晶体管T7、T3、T2、T4与T8将数据写入至电容器C1。如此一来，在该第二阶段结束时，可将VA还有Vg以下列方程式(1)表示。
VA＝Vg＝Vdata–(|Vth2|+|Vth3|+|Vth4|) 方程式(1)
其中Vdata表示晶体管T7接收的数据的电压电平，而|Vth2|、|Vth3|與|Vth4|分别表示晶体管T2、T3与T4的阈值电压。在一实施例中，Vdata介于约2V至约5V，而|Vth2|、|Vth3|與|Vth4|分别约为0.6V。
与晶体管T2、T3与T4相关的(|Vth2|+|Vth3|+|Vth4|)一词称为补偿电压，下文将参照图5A及5B进一步讨论。
图5A及5B示出的根据某些实施例，在第三阶段中，操作图2所示电路20的方法。
参照图5A，在时间点t3，控制信号EM被拉至负缘，而位于高逻辑电平的控制信号S1与S2则未经拉动。如此一来，参照图5B，晶体管T1、T7与T8被关闭，而晶体管T9与T10则被开启。对于晶体管T2、T5与T6，由于栅极电压电平Vg为Vdata–(|Vth2|+|Vth3|+|Vth4|)且源极电压电平Vs约为VDD，使得|Vgs|>|Vth|，故将驱动晶体管T2、T5与T6保持在开启状态。如此一来，来自供应电源VDD的电流通过晶体管T9、T5、T2、T6与T10流经EL装置28而到达VSS，进而使得EL装置28发光。在第三阶段中，通过电容器C1的作用，将Vg保持在Vdata–(|Vth2|+|Vth3|+|Vth4|)。
可将流经EL装置28的电流Isd以下列方程式(2)来表示。
|Isd|＝k×[|Vsg|-(|Vth2|+|Vth5|+|Vth6|)]2 方程式(2)
其中k为一常数，且|Vth5|與|Vth6|分别表示晶体管T5与T6的阈值电压。
因为|Vsg|＝VDD–Vdata+(|Vth2|+|Vth3|+|Vth4|)，可将方程式(2)改写为下列方程式(3)。
|Isd|＝k×[VDD–Vdata+(|Vth3|+|Vth4|)-(|Vth5|+|Vth6|)]2
方程式(3)
举例来说，可通过控制装置特征构造，譬如半导体制造时的通道长度，而使方程式(3)中的(|Vth3|+|Vth4|)及(|Vth5|+|Vth6|)互相抵销。如此一来，可再次将方程式(3)改写为下列方程式(4)。
|Isd|＝k×[VDD–Vdata]2 方程式(4)
由于方程式(4)不包含方程式(2)或方程式(3)中所述的多个Vth参数，可以提升显示器10的显示品质。
如此一来，本发明的实施例提供一补偿电路，其包含一电容器C1、一电致发光(EL)装置28、一第一组晶体管以及一第二组晶体管。第一组晶体管包含一第一晶体管、一第二晶体管与一第三晶体管，分别对应于晶体管T2、T3与T4。第二组晶体管包含上述第一晶体管、一第四晶体管与一第五晶体管，分别对应于晶体管T2、T5与T6。第一组晶体管耦接于电容器C1的一第一端(连接至节点A)和数据输入之间，其是用以回应所述数据输入而提供一补偿电压。上述补偿电压是由第一组晶体管中每一晶体管T2、T3、T4的阈值电压所构成。第二组晶体管耦接于EL装置28和电容器C1的一第二端(连接至VDD)之间，其是用以使一电流通过第二组晶体管而流经EL装置。所述电流的强度不受第二组晶体管中每一晶体管T2、T5、T6的阈值电压影响。
图6A示出的根据另一实施例的显示器的子像素单元60的电路图。
参照图6A，所示电路与上文参照图2所示的电路20相似，不同之处在于譬如可利用n-型TFT或n-型金氧半(NMOS)晶体管来取代图2中的p-型TFT或PMOS晶体管T1至T10。具体来说，晶体管T1的栅极接收控制信号S1。晶体管T1的源极接收来自DC偏压源18的参考电压Vref。晶体管T1的漏极耦接至节点A。此外，晶体管T2、T3、T4、T5与T6的栅极也分别耦接至节点A。晶体管T2的源极分别耦接至晶体管T3的源极以及晶体管T5的漏极。晶体管T2的漏极分别耦接至晶体管T6的源极以及晶体管T4的漏极。
除此之外，晶体管T7与T8两者的栅极接收控制信号S2。晶体管T7的漏极从源极驱动器15接收一相应数据线上的数据(标记为"DATA")。晶体管T7的源极耦接至晶体管T3的漏极。此外，晶体管T8的源极耦接至节点A。晶体管T8的漏极耦接至晶体管T4的源极。
再者，晶体管T9与T10两者的栅极接收该控制信号EM。晶体管T9的源极接收VSS。晶体管T9的漏极耦接至晶体管T5的源极。除此之外，晶体管T10的源极耦接至晶体管T6的漏极。晶体管T10的漏极耦接至EL装置28的阴极。EL装置28的阳极耦接至VDD。
图6B为根据某些实施例，用以操作图6A所示电路的控制信号的波形图。
参照图6B，控制信号S1、S2与EM和上文参照图3A、4A或5A所述者相似，不同之处在于，例如，图6B的控制信号S1、S2及EM为正缘触发，或拉高至一正缘(rising edge)。相似地，可将流经EL装置28的电流Isd表示为下列方程式(5)。
|Isd|＝k×[VDD–Vdata+(|Vth3|+|Vth4|)-(|Vth5|+|Vth6|)]2
方程式(5)
通过控制装置特征结构，譬如半导体制程中(制造时)的通道长度，而使方程序(5)中的(|Vth3|+|Vth4|)及(|Vth5|+|Vth6|)互相抵销。如此一来，可再次将方程式(5)改写为下列方程式(6)。
|Isd|＝k×[Vdata–VSS]2 方程式(6)
图7为一流程图，示出的在电致发光显示器中进行电压补偿的方法。
参照图7，在操作71，提供一电致发光(EL)显示器。所述EL显示器包含多个像素单元，其分别包含电容器、EL装置、第一组晶体管及第二组晶体管。
在操作73，于第一阶段中，重置电容器第一端的电压电平。
在操作75，于第二阶段中，将数据储存于电容器中。上述数据是通过第一组晶体管所接收。此外，在第二阶段中，产生由第一组晶体管中每一晶体管的阈值电压所构成的补偿电压。
在操作77，于第三阶段中，使电流通过第二组晶体管而流经EL装置。所述电流的强度与第二组晶体管中每一晶体管的阈值电压无关。
上文的叙述简要地提出了本发明某些实施例的特征，而使得本发明所属技术领域技术人员能够更全面地理解本公开内容的多种实施方式。本发明所属技术领域技术人员当可明了，其可轻易地利用本公开内容作为基础，来设计或变动其他制程与结构，以实现与此处所述的实施方式相同的目的和/或达到相同的优点。本发明所属技术领域技术人员应当明白，这些均等的实施方式仍属于本公开内容的构思与范围，且其可进行各种变更、替代与变动，而不会悖离本公开内容的构思与范围。

Claims (16)

1.一种补偿电路，包含：
一电容器，包含一第一端及一第二端；
一电致发光EL装置；
一第一组晶体管，耦接于该电容器的该第一端和一数据输入之间，其是用以利用该第一组晶体管包含一第一晶体管、一第二晶体管及一第三晶体管，提供一补偿电压以回应于该数据输入所接收的数据，该补偿电压是由该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管各自的一阈值电压的总和所构成；以及
一第二组晶体管，耦接于该EL装置和该电容器的该第二端之间，其是用以使一电流通过该第二组晶体管的多个晶体管流经该EL装置，该电流的一强度与该第二组晶体管的所述多个晶体管各自的一阈值电压无关；该电流所流经的该第二组晶体管的所述多个晶体管各自的栅极均耦接至该电容器的该第一端，以及该第二组晶体管的所述多个晶体管中的至少一晶体管不同于用来提供该补偿电压的该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管。
2.如权利要求1所述的补偿电路，其中该第一组晶体管中的所述第一晶体管、第二晶体管与第三晶体管各自的一栅极耦接至该电容器的该第一端。
3.如权利要求1所述的补偿电路，其中该第二组晶体管的所述多个晶体管包含该第一晶体管、一第四晶体管及一第五晶体管，且该补偿电压是该第一、第四与第五晶体管的该阈值电压的总和。
4.如权利要求1所述的补偿电路，还包含另一晶体管，用以回应一第一控制信号，以重置该电容器的该第一端的一电压电平。
5.如权利要求1所述的补偿电路，还包含多个晶体管，用以回应一第二控制信号，以通过该第一组晶体管而使该数据储存于该电容器中。
6.如权利要求1所述的补偿电路，还包含多个晶体管，用以回应一第三控制信号，以使该电流通过该第二组晶体管流经该EL装置。
7.如权利要求1所述的补偿电路，其中该第一组晶体管中每一晶体管及该第二组晶体管中每一晶体管分别包含一p-型晶体管。
8.如权利要求1所述的补偿电路，其中该第一组晶体管中每一晶体管及该第二组晶体管中每一晶体管分别包含一n-型晶体管。
9.一电致发光显示器，包含：
一像素单元阵列，其中的每一像素单元包含：
一电容器，包含一第一端及一第二端；
一电致发光EL装置；
一第一组晶体管，耦接于该电容器的该第一端和一数据输入之间，其是用以利用该第一组晶体管包含一第一晶体管、一第二晶体管及一第三晶体管，提供一补偿电压以回应于该数据输入所接收的数据，该补偿电压是由该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管各自的一阈值电压的总和所构成；以及
一第二组晶体管，耦接于该EL装置和该电容器的该第二端之间，其是用以使一电流通过该第二组晶体管的多个晶体管流经该EL装置，该电流的一强度与该第二组晶体管的所述多个晶体管各自的一阈值电压无关；该电流所流经的该第二组晶体管的所述多个晶体管各自的栅极均耦接至该电容器的该第一端，以及该第二组晶体管的所述多个晶体管中的至少一晶体管不同于用来提供该补偿电压的该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管。
10.如权利要求9所述的电致发光显示器，其中该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管各自的一栅极耦接至该电容器的该第一端。
11.如权利要求9所述的电致发光显示器，其中该第二组晶体管的所述多个晶体管包含该第一晶体管、一第四晶体管及一第五晶体管，且该补偿电压是该第一、第四与第五晶体管的该阈值电压的总和。
12.如权利要求9所述的电致发光显示器，其中该每一像素单元还包含另一晶体管，用以回应一第一控制信号，以重置该电容器的该第一端的一电压电平。
13.如权利要求9所述的电致发光显示器，其中该每一像素单元还包含多个晶体管，用以回应一第二控制信号，以通过该第一组晶体管而使该数据储存于该电容器中。
14.如权利要求9所述的电致发光显示器，其中该每一像素单元还包含多个晶体管，用以回应一第三控制信号，以使该电流通过该第二组晶体管流经该EL装置。
15.一种电致发光EL显示器的电压补偿方法，该EL显示器包含多个像素单元，所述像素单元各别包含一电容器、一EL装置、一第一组晶体管及一第二组晶体管，该方法包含：
于一第一阶段中，重置该电容器的一第一端的一电压电平；
于一第二阶段中，将数据储存于该电容器中，该数据是通过该第一组晶体管所接收，该第一组晶体管包含一第一晶体管、一第二晶体管及一第三晶体管；
于该第二阶段中，产生一补偿电压，其是由该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管各自的一阈值电压的总和所构成；以及
于一第三阶段中，使一电流通过该第二组晶体管的多个晶体管流经该EL装置，该电流大小与该第二组晶体管的所述多个晶体管各自的一阈值电压无关，其中该电流所流经的该第二组晶体管的所述多个晶体管各自的栅极均耦接至该电容器的该第一端，以及该第二组晶体管的所述多个晶体管中的至少一晶体管不同于用来提供该补偿电压的该第一组晶体管的所述第一晶体管、第二晶体管与第三晶体管。
16.如权利要求15所述的方法，其中该补偿电压等于该第二组晶体管中每一晶体管的该阈值电压的总和。
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