TWI677074B - 具有隔離閘的半導體裝置及其形成方法 - Google Patents

具有隔離閘的半導體裝置及其形成方法 Download PDF

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TWI677074B
TWI677074B TW104129288A TW104129288A TWI677074B TW I677074 B TWI677074 B TW I677074B TW 104129288 A TW104129288 A TW 104129288A TW 104129288 A TW104129288 A TW 104129288A TW I677074 B TWI677074 B TW I677074B
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gate structure
diffusion region
contact
isolation gate
disposed
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TW201624671A (zh
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雷維基 森古普塔
Rwik Sengupta
麥克 Ｓ． 羅德爾
Mark S. Rodder
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南韓商三星電子股份有限公司
Samsung Electronics Co., Ltd.
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Abstract

一種包含半導體裝置的實施例，包括基板；連續擴散區， 配置於基板上；第一閘結構，配置於連續擴散區上；第二閘結構，配置於連續擴散區上；隔離閘結構，配置於第一閘結構及第二閘結構之間且鄰近於第一閘結構及第二閘結構；連續擴散區的第一擴散區，配置於第一閘結構及隔離閘結構之間；連續擴散區的第二擴散區，配置於第二閘結構及隔離閘結構之間；導電層，配置於第一擴散區及第二擴散區上；以及隔離閘接點，配置於隔離閘結構上且與第一擴散區電性絕緣。

Description

具有隔離閘的半導體裝置及其形成方法
本發明是有關於一種半導體裝置，且特別是有關於一種具有隔離閘的半導體裝置。
由半導體裝置製造之標準的單元邏輯閘(cell logic gate)可按比例縮小以增加晶片密度。此外，可使用不同的單元佈局(cell layout)以更增加晶片密度。然而，相鄰的電晶體之間應互相電性絕緣。為了隔離相鄰的電晶體，在擴散區中可使用虛擬閘區做為阻斷。此結構可能需要一倍或兩倍的半導體裝置之接觸多晶節距(contacted poly pitch)作為分隔。此距離限制電晶體之間的最小間距，且因此限制單元尺寸的最小化。
一實施例包含一種半導體裝置，其包括基板；連續擴散區，配置於基板上；第一閘結構，配置於連續擴散區上；第二閘結構，配置於連續擴散區上；隔離閘結構，配置於第一閘結構及 第二閘結構之間且鄰近於第一閘結構及第二閘結構；連續擴散區的第一擴散區，配置於第一閘結構及隔離閘結構之間；連續擴散區的第二擴散區，配置於第二閘結構及隔離閘結構之間；導電層，配置於第一擴散區及第二擴散區上；以及隔離閘接點(contact)，配置於隔離閘結構上且與第一擴散區電性絕緣。
一實施例包含一種半導體裝置，其包括基板；連續擴散區，配置於基板上；第一閘結構，配置於連續擴散區上；第二閘結構，配置於連續擴散區上；隔離閘結構，配置於第一閘結構及第二閘結構之間且鄰近於第一閘結構及第二閘結構；連續擴散區的第一擴散區，配置於第一閘結構及隔離閘結構之間；連續擴散區的第二擴散區，配置於第二閘結構及隔離閘結構之間；以及隔離閘接點，配置於隔離閘結構上且與第一擴散區及第二擴散區中的每一者電性絕緣。
一實施例包含一種方法，其包括形成連續擴散區於基板上；形成隔離閘結構於連續擴散區上；形成導電層於隔離閘結構的側面上；形成源極/汲極接點於導電層上；以及形成隔離閘接點於隔離閘結構上，其中隔離閘接點與至少一個源極/汲極接點電性絕緣。
100、200、300、400、500、600、700‧‧‧半導體裝置
101‧‧‧連續擴散區
102‧‧‧鰭片
103a、103b‧‧‧間隔
104、105‧‧‧閘結構
104a‧‧‧閘電極
104b‧‧‧閘絕緣層
106‧‧‧矽化物層
107‧‧‧源極/汲極
108、112、120、122、126、127‧‧‧接點
109、111、113‧‧‧擴散區
110‧‧‧隔離閘結構
114‧‧‧隔離閘接點
120a、120b‧‧‧部份
124、128‧‧‧內連線
131、132‧‧‧方向
1000、1002、1004、1006、1008、1010‧‧‧步驟
1100‧‧‧電子系統
1112‧‧‧記憶系統
1114‧‧‧處理器
1116‧‧‧RAM
1118‧‧‧使用者介面
1120‧‧‧匯流排
圖1是根據一實施例的半導體裝置的俯視圖。
圖2及圖3是圖1的半導體裝置的剖面圖。
圖4至圖6是根據不同實施例的半導體裝置的俯視圖。
圖7A是根據另一實施例的半導體裝置的俯視圖。
圖7B是圖6A的半導體裝置的剖面圖。
圖8A及圖8B是根據不同實施例的半導體裝置的俯視圖。
圖9是根據另一實施例的半導體裝置的俯視圖。
圖10所示為根據一實施例的形成半導體裝置的技術之流程圖。
圖11是根據一實施例的可包含半導體裝置的電子系統的示意圖。
本實施例是關於一種半導體裝置，且特別是關於一種具有隔離閘的半導體裝置。以下呈現的描述使所屬領域中具通常知識者能夠作出及使用實施例，且提供於專利申請及其需求的內文中。本文所描述的實施例的各種修正、一般性的原理及特徵將可無困難地理解。實施例大部分以特定的實作提供之特定的方法及裝置的方式來描述。
然而，此方法及裝置將有效地運作於其他實作中。例如“一實施例”及“另一實施例”的描述可代表相同或不同的實施例以及多個實施例。實施例將描述關於具有確切組成的系統及/或裝置。然而，所述系統及/或裝置可比所示者包含更多或更少的組件， 且在不違背此揭露的範圍下，可對配置及組件的型態作出改變。實施例也將描述於具有確切步驟之特定方法的上下文中。然而，此方法可根據具有不同及/或額外步驟的其他方法來操作，且不同次序的步驟並不會使本實施例前後矛盾。因此，實施例並不會被本發明所示的特定實施例刻意限制，而是符合最廣泛的範圍，且與本發明所描述的原理及特徵一致。
本實施例於上下文中描述具有確切組件的特定裝置。所屬領域中具通常知識者將理解在其他實施例中，此裝置可具有其他及/或額外的組件及/或其他的特徵。所屬領域中具通常知識者也將無困難地理解描述於具有與基板特定關聯結構之上下文中的方法及裝置。然而，所屬領域中具通常知識者將無困難地理解此方法及系統與其他結構一致。此外，所屬領域中具通常知識者將無困難地理解層能具有另一結構。方法及裝置也可以上下文中的單一構件來描述。然而，所屬領域中具通常知識者將無困難地理解此方法及裝置與使用具有多個構件之裝置一致。
所屬領域中具通常知識者將理解的是，一般來說，本發明且特別是在附加的申請專利範圍(例如附加申請專利範圍的正文)中使用的術語通常為“開放式”的術語，舉例來說，術語“包含”應詮釋為“包含但不限於”，術語“具有”應詮釋為“至少具有”，術語“包括”應詮釋為“包括但不限於”等等。所屬領域中具通常知識者更將理解的是，假如意圖陳述一些特定引入的申請專利範圍，其將會於申請專利範圍中明確地記載，且未意圖陳述的則不會呈現。 舉例來說，為了有助於了解，下述附加的申請專利範圍可包含引導式用語“至少一”以及“一或更多”的用法以引入請求項的陳述。然而，此用語的用法不應被解釋為意味著藉由不明確的冠詞“一”引入的申請專利範圍陳述來限制任一包含僅具有一種實施例之引入申請專利範圍的特定申請專利範圍，甚至當相同的申請專利範圍包含引導式用語“至少一”或“一或更多”以及不明確的冠詞例如“一”時，舉例來說，“一”應被解釋為“至少一”或“一或更多”的意思；其同樣適用於使用明確的冠詞用法以引入申請專利範圍陳述。此外，在那些例子中會使用與“A、B或C的至少一者”類似的常用語，一般來說，所屬領域中具通常知識者能夠了解此常用語的句法結構意圖表達的意思，舉例來說，“具有A、B或C的至少一者之系統”包含具有單獨的A、單獨的B、單獨的C、A和B、A和C、B和C及/或A、B和C之系統，但不限於此。所屬領域中具通常知識者將更加了解的是，實際上，無論在實施方式、申請專利範圍或圖式中，任一轉折的單字及/或用語會呈現兩個或更多的替代術語，且所屬領域中具通常知識者應了解並仔細思考上述單字及/或用語包含上述術語的其中之一或上述術語的兩者之可能性。舉例來說，“A或B”可理解為包含“A”或“B”或“A和B”的可能性。
在附圖中，不同的層、結構、尺寸或類似物以理想的方式說明，以有助於解釋不同方面的實施例。然而，在其他實施例中，根據製造技術及/或製造公差可預期說明形式的改變。因此， 實施例不應被理解成特定限制說明形式的範圍。在製造過程的期間可改變此形式。另外，不同的關聯性可被描述為實質上相同、實質上相等或其他類似的描述。如本發明中所述，“實質上”不僅包含完全相等的關聯性，也包含在製造技術及/或製造公差中相等的關聯性。
圖1是根據一實施例的半導體裝置100的俯視圖。圖2及圖3分別是沿著圖1的平面A及平面B的半導體裝置的剖面圖。請參照圖1至圖3，在一實施例中，半導體裝置100包含配置於基板上的連續擴散區101。為清楚起見，未繪示基板。在此實施例中，連續擴散區101包含多個鰭片102；然而，在其他實施例中，連續擴散區101可具有不同的結構。舉例來說，平面式場效電晶體(planar FET)、鰭狀場效電晶體(finFET)、環繞式閘極奈米線場效電晶體(GAA nanowire FET)、任一其他具有源極/汲極/閘極端子的水平式金氧半場效電晶體通道架構(horizontal MOSFET channel scheme)或其他類似電晶體的擴散區可作為所述半導體裝置的部分結構。
第一閘結構104及第二閘結構105配置於連續擴散區101上。閘結構104、105可包含多個堆疊層，其例如是閘絕緣層、閘電極、罩蓋圖案或其他類似的結構。舉例來說，閘結構104包含閘電極104a及閘絕緣層104b。閘結構105可具有類似的層；然而，為清楚起見，上述的層並未個別區別。第一閘結構104及第二閘結構105在邏輯裝置中可作為電晶體的閘極。
隔離閘結構110配置於連續擴散區101上。隔離閘結構110配置於第一閘結構104及第二閘結構105之間且鄰近於第一閘結構104及第二閘結構105。隔離閘結構110可具有與第一閘結構104及第二閘結構105類似的形式及/或層；然而，在其他實施例中，隔離閘結構110可與第一閘結構104與第二閘結構105中的一者或二者不同。
在一實施例中，第一閘結構104至隔離閘結構110的間距103a與第二閘結構105至隔離閘結構110的間距103b中的一者或二者可與半導體裝置100的接觸多晶節距(contacted poly pitch,CPP)實質上相等，其中接觸多晶節距為接觸閘(contacted gate)的最小節距。
電晶體的源極/汲極區可配置於閘結構104的側邊。舉例來說，連續擴散區101的第一擴散區109可配置在第一閘結構104及隔離閘結構110之間。連續擴散區102的第二擴散區111可配置在第二閘結構105及隔離閘結構110之間。第一擴散區109及第二擴散區111可形成不同電晶體的源極/汲極區。
在此實施例中，矽化物層106配置在第一擴散區及第二擴散區上。特別是，矽化物層106配置在位於第一擴散區109及第二擴散區111中的源極/汲極107上。接點108、112分別配置在位於擴散區109及擴散區111中的矽化物層上。接點108、112可為局部接點(partial contact)。因此，接點108、112不會延伸至橫跨整個對應的擴散區109及擴散區111。雖然實例中已使用矽化 物，但可使用包含金屬合金的任一導電層。
雖然已繪示出源極/汲極107具有合併的菱形剖面，但在其他實施例中，源極/汲極107可具有其他形狀及/或為非併接的。舉例來說，源極/汲極107的剖面可為長方形、五邊形、六邊形、橢圓形或其他類似的形狀。就源極/汲極107為非併接的例子來說，為了形成類似連接全部源極/汲極107的連續導電區，矽化物層106及/或包含金屬合金的任一導電層可更接觸除了包含源極/汲極107的實質上頂部表面，而且接觸包含源極/汲極107之實質上的邊緣或底部表面及/或位於非合併之源極/汲極107中間的絕緣區。
隔離閘接點114配置於隔離閘結構110上且與擴散區109及擴散區111中的至少一區電性絕緣。在此實施例中，隔離閘接點114與第一擴散區109電性絕緣。然而，隔離閘接點114與接點112電性連接。特別是，隔離閘接點114可接觸接點112。舉例來說，在此實施例中，接點112寬於接點108。因此，於隔離閘接點114與接點112之間作出電性連接。可形成具有足夠寬度的接點112以連接隔離閘接點114。
在此實施例中，當適當地施加偏壓於隔離閘結構110時，擴散區109及擴散區111可為電性絕緣。舉例來說，可透過接點112提供電力或接地電壓至擴散區111。上述電壓可為關閉在隔離閘結構110下方的通道之適當的電壓。舉例來說，對NMOS而言，可將其連接至0電位，而對PMOS而言，可將其連接至電力來源。 隔離閘接點114與接點112電性連接，且因此電壓被提供至隔離閘結構110以關閉通道。
雖然已描述隔離閘結構110與鄰近的擴散區111電性連接，但隔離閘接點114可與擴散區109及擴散區111電性絕緣，如以下將進一步描述。
在一實施例中，連續擴散區101可降低應變鬆弛及/或接點未準確連接的可能性。特別是，相對於使用單一或雙重擴散斷點(diffusion break)的半導體裝置，可降低上述情況的可能性。
在一實施例中，在具有未共有的源極/汲極之相同型態的電晶體之間的擴散斷點的數量可降低至0。特別是，其可藉由使用連續擴散區101作為鄰近電晶體的源極/汲極來達成。特別是，在一些半導體裝置中，對於每一個源極/汲極區109、111的接觸可包含穿過與所述裝置的多個鰭片102相關之全部源極/汲極區109、111的溝渠式接點(trench contact)，亦即“全接點(full contact)”。當單元按比例縮小時，製程裕度可能不足以防止於溝渠式接點及隔離閘結構110之間非刻意的電性連接。此外，路線的擁塞可能使隔離閘結構110更難以直接連接電源軌線(power rail)。
因此，在一實施例中，局部接點可取代覆蓋整個擴散區109或擴散區111的溝渠式接點。局部接觸可包含具有局部接點的毯覆式金屬矽化物源極/汲極，例如接點108。假如未消除隔離閘結構110及鄰近的擴散區109及擴散區111之間非刻意的電性連接的機會，則與隔離閘結構110的連接會於具有減少的MOSFET 裝置的主動區上形成。在此實施例中，接點108的長度不會沿著擴散區109的整個長度延伸。特別是，接點108可延伸至使所述接點的末端與隔離閘接點114分隔大於或等於需求製程裕度的距離。因此，可消除隔離閘接點114與接點108之間的電性連接，且因此可消除與擴散區109之間的電性連接。如圖2所示，儘管接點108並未出現於圖2的剖面圖中，但以虛線表示接點108以顯示接點108與隔離閘接點114的關係。如同於圖2所能看到的，若接點108與隔離閘接點114緊鄰，則可能形成非預期的接觸。
在一實施例中，隔離閘結構110可包含閘堆疊材料，其可使得分隔擴散區109及擴散區111的隔離閘具有較高程度的臨界電壓。由於可對隔離閘結構110施加偏壓使其總是關閉，因此可使用額外的植入或較大的閘極長度以增加隔離閘結構110的臨界電壓而比另一側的電晶體更高。
圖4至圖6是根據不同實施例的半導體裝置的俯視圖。請參照圖4，在此實施例中，半導體裝置200具有與圖1的半導體裝置100類似之結構。然而，隔離閘接點114並未直接配置於鰭片102上。在本實施例中，隔離閘接點114可配置於鰭片102之間。此外，在其他實施例中，隔離閘接點114可配置於其他位置中。
請參照圖5，在此實施例中，半導體裝置300具有與圖1的半導體裝置100類似之結構。然而，連續擴散區101僅包含一個鰭片102。雖然鰭片102是作為連續擴散區101的例子，但也可 使用其他的單一擴散區結構。
請參照圖6，在此實施例中，半導體裝置400具有與圖1的半導體裝置100類似之結構。然而，在此實施例中，接點120是作為代替圖1的接點112使用。特別是，接點120具有二維形狀。也就是說，接點120不僅是在方向131延伸的結構，而且也在第二方向132延伸。在本實施例中，第一方向131為實質上與隔離閘結構110平行的方向，同時第二方向132為實質上與第一方向131垂直的方向。方向131、132可實質上與基板的表面平行。
在此實施例中，接點120包含在方向132朝著隔離閘接點114延伸的部份120a。因此，隔離閘接點114可具有較小的寬度，例如在第二方向132(例如與隔離閘結構110垂直)上具有具有較短的長度。因此，更可降低接點114與擴散區109非刻意地電性連接之可能性。
此外，接點120的另一部份120b可實質上與其他接點(例如是接點108)類似。因此，除了刻意與鄰近結構(例如是隔離閘接點114)接觸的部份120a，接點120的空間裕度可與其他接點類似。
圖7A是根據另一實施例的半導體裝置的俯視圖。圖7B是沿著圖7A的平面C的半導體裝置的剖面圖。請參照圖7A及圖7B，在此實施例中，半導體裝置500具有與圖1的半導體裝置100類似之結構。然而，在此實施例中，接點122是作為代替圖1的接點112使用。特別是，接點122並未直接與隔離閘接點114接觸。相對的，包含內連線124的內連線層用以使隔離閘接點114 電性連接至接點122。
圖8A及圖8B是根據不同實施例的半導體裝置的俯視圖。請參照圖8A，在此實施例中，半導體裝置600具有與圖7A的半導體裝置500類似之結構。然而，在此實施例中，接點126是作為代替圖7A的接點122使用。接點126並未電性連接至隔離閘接點114。舉例來說，接點126可與接點108類似，例如是僅部份地延伸覆蓋擴散區109及擴散區111。因此，隔離閘結構110與鄰近的擴散區109及擴散區111電性絕緣。
此外，內連線128是作為代替圖7A的內連線124使用。特別是，內連線128延伸至半導體裝置600的另一部份，其中內連線128電性連接至一電壓以施加偏壓於隔離閘結構110。在一實施例中，內連線128可僅延伸至鄰近的單元、電路或類似物；然而，內連線128可延伸任一距離且也可連接至類似隔離閘結構110的其他閘結構。
請參照圖8B，在此實施例中，半導體裝置700具有與圖8A的半導體裝置600類似之結構。然而，在本實施例中，內連線128電性連接至在遠處的另一個擴散區113中之接點127。擴散區113可在相同的單元或鄰近的單元等等中，上述鄰近的單元為連接至適當電壓的下一個單元元件。
請參照圖9，在此實施例中，半導體裝置800具有與圖1的半導體裝置100類似之結構。然而，也繪示出訊號閘接點150。訊號閘接點150配置於閘結構105上以接觸閘結構105。在一實施 例中，訊號閘接點150及隔離閘接點114可具有實質上相同的結構。因此，可不需額外的製程以形成隔離閘結構114。在另一實施例中，隔離閘接點114可相對訊號閘接點150延長。舉例來說，隔離閘接點114在與隔離閘結構110延伸的方向垂直的方向上可比訊號閘接點150長。
圖10所示為根據一實施例的形成半導體裝置的技術之流程圖。在此實施例中，於步驟1000中，連續擴散區形成在基板上。於步驟1002中，隔離閘結構形成於連續擴散區上。於步驟1004中，矽化物層形成於隔離閘結構的側邊。矽化物層可為毯覆式矽化物層，其導致在連續擴散區的源極/汲極上的自我對準矽化物結構。於步驟1006中，源極/汲極接點形成於矽化物層上。於步驟1008中，隔離閘接點形成於隔離閘結構上。
使用上述的技術可形成本實施例描述的結構。舉例來說，於步驟1006及步驟1008中，形成源極/汲極接點及隔離閘接點可導致介於源極/汲極接點中的一者與隔離閘接點之間的電性連接。
於步驟1010中，形成內連線層。內連線層可包含內連線，所述內連線使隔離閘接點電性連接至源極/汲極接點。舉例來說，如上所述，內連線可使隔離閘接點電性連接至鄰近的源極/汲極接點、遠處的源極/汲極接點或類似的源極/汲極接點。
圖11是可包含根據一實施例的半導體裝置的電子系統的示意圖。電子系統1100可為各式各樣的電子裝置之一部分，其包 含攜帶型筆記型電腦(portable notebook computer)、超級移動電腦(Ultra-Mobile PC，UMPC)、平板電腦(Tablet PC)、伺服器(server)、工作站(workstation)、移動式遠程通信裝置(mobile telecommunication device)等等，但不限於此。舉例來說，電子系統1100可包含記憶系統1112、處理器1114、RAM 1116以及使用者介面1118，所述電子系統1100可使用匯流排1120以執行數據傳遞。
處理器1114可為微處理器或行動處理器(mobile processor，AP)。處理器1114可具有處理器核心(未繪示)，其可包含浮點單元(floating point unit，FPU)、算數邏輯單元(arithmetic logic unit，ALU)、圖形處理單元(graphics processing unit，GPU)以及數位信號處理核心(digital signal processing core，DSP Core)，或上述的任一組合。可安裝處理器1114以執行程式以及控制電子系統1100。
RAM 1116可作為處理器1114的操作記憶體使用。作為一種選擇，處理器1114及RAM 1116可封裝於單一封裝體中。
可使用使用者介面1118輸入數據至電子系統1100，或從電子系統1100輸出數據。舉例來說，使用者介面1118可包含觸控螢幕、鍵盤、網路介面、指向裝置、音響裝置、力回饋裝置或其他類似的裝置。
記憶系統1112可儲存用來操作處理器1114的代碼、藉由處理器1114處理的數據或外部的輸入數據。記憶系統1112可 包含控制器與記憶體。記憶體系統可包含電腦可讀媒體的介面。此電腦可讀媒體可儲存指令以執行上述各式各樣的操作。
雖然裝置、方法及系統已依據特定的實施例描述，所屬領域中具通常知識者將無困難地理解對已揭露的實施例作出許多變化是可能的，且因此任一變化應視為在本發明的裝置、方法及系統中揭露的精神及範圍中。因此，所屬領域中具通常知識者可作出許多修改而不違背附加申請專利範圍的精神及範圍。

Claims (14)

  1. 一種半導體裝置，包括：基板；連續擴散區，配置於所述基板上；第一閘結構，配置於所述連續擴散區上；第二閘結構，配置於所述連續擴散區上；隔離閘結構，配置於所述第一閘結構及所述第二閘結構之間且鄰近於所述第一閘結構及所述第二閘結構；所述連續擴散區的第一擴散區，配置於所述第一閘結構及所述隔離閘結構之間；所述連續擴散區的第二擴散區，配置於所述第二閘結構及所述隔離閘結構之間；導電層，配置於所述第一擴散區及所述第二擴散區上；隔離閘接點，配置於所述隔離閘結構上且與所述第一擴散區電性絕緣；以及源極/汲極接點，與所述隔離閘接點電性連接，其中所述源極/汲極接點電性連接至所述第二擴散區，其中所述源極/汲極接點接觸所述隔離閘接點，其中所述源極/汲極接點包括朝所述隔離閘接點延伸的部分。
  2. 如申請專利範圍第1項所述的半導體裝置，更包括與所述第一閘結構電性連接的訊號閘接點，其中所述訊號閘接點與所述隔離閘接點具有實質上相同的結構。
  3. 如申請專利範圍第1項所述的半導體裝置，其中所述隔離閘結構具有高於所述第一閘結構或所述第二閘結構的臨界電壓。
  4. 如申請專利範圍第1項所述的半導體裝置，其中所述第一閘結構及所述第二閘結構的節距與所述半導體裝置的接觸多晶節距實質上相等。
  5. 如申請專利範圍第1項所述的半導體裝置，更包括配置於所述第一閘結構上的閘接點，其中所述隔離閘接點相應於所述閘接點是長的。
  6. 如申請專利範圍第1項所述的半導體裝置，更包括：第一源極/汲極接點，在所述第一擴散區上延伸；以及第二源極/汲極接點，在所述第二擴散區上延伸，其中所述第一源極/汲極接點及所述第二源極/汲極接點在各自的擴散區上延伸不同量。
  7. 一種半導體裝置，包括：基板；連續擴散區，配置於所述基板上；第一閘結構，配置於所述連續擴散區上；第二閘結構，配置於所述連續擴散區上；隔離閘結構，配置於所述第一閘結構及所述第二閘結構之間且鄰近於所述第一閘結構及所述第二閘結構；所述連續擴散區的第一擴散區，配置於所述第一閘結構及所述隔離閘結構之間；所述連續擴散區的第二擴散區，配置於所述第二閘結構及所述隔離閘結構之間；隔離閘接點，配置於所述隔離閘結構上且與每一個所述第一擴散區及所述第二擴散區電性絕緣；以及內連線，與所述隔離閘接點電性連接，且所述內連線在所述第一擴散區上從所述隔離閘接點延伸至超出所述第一擴散區。
  8. 如申請專利範圍第7項所述的半導體裝置，其中所述內連線與另一隔離閘接點電性連接。
  9. 一種半導體裝置的形成方法，包括：形成連續擴散區於基板上；形成隔離閘結構於所述連續擴散區上；形成導電層於所述隔離閘結構的側邊；形成源極/汲極接點於所述導電層上；以及形成隔離閘接點於所述隔離閘結構上，其中所述隔離閘接點與所述源極/汲極接點中的至少一者電性絕緣。
  10. 如申請專利範圍第9項所述的半導體裝置的形成方法，其中形成所述隔離閘接點包括形成所述隔離閘接點與所述源極/汲極接點中的所述至少一者間隔一距離，其中所述距離大於或等於形成所述源極/汲極接點及形成所述隔離閘接點中的至少一者之製程裕度。
  11. 如申請專利範圍第9項所述的半導體裝置的形成方法，其中所述連續擴散區為鰭片。
  12. 如申請專利範圍第9項所述的半導體裝置的形成方法，其中形成所述源極/汲極接點包括形成至少一個接觸所述隔離閘接點的源極/汲極接點。
  13. 如申請專利範圍第9項所述的半導體裝置的形成方法，更包括形成內連線層，其中所述隔離閘接點透過所述內連線層與至少一個所述源極/汲極接點電性連接。
  14. 一種半導體裝置，包括：基板；連續擴散區，配置於所述基板上；第一閘結構，配置於所述連續擴散區上；第二閘結構，配置於所述連續擴散區上；隔離閘結構，配置於所述第一閘結構及所述第二閘結構之間且鄰近於所述第一閘結構及所述第二閘結構；所述連續擴散區的第一擴散區，配置於所述第一閘結構及所述隔離閘結構之間；所述連續擴散區的第二擴散區，配置於所述第二閘結構及所述隔離閘結構之間；導電層，配置於所述第一擴散區及所述第二擴散區上；隔離閘接點，配置於所述隔離閘結構上且與所述第一擴散區電性絕緣；以及源極/汲極接點，與所述隔離閘接點電性連接，其中所述源極/汲極接點透過內連線層電性連接至所述隔離閘接點，其中所述源極/汲極接點與所述第二擴散區電性絕緣。
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