TWI654746B - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
TWI654746B
TWI654746B TW106106011A TW106106011A TWI654746B TW I654746 B TWI654746 B TW I654746B TW 106106011 A TW106106011 A TW 106106011A TW 106106011 A TW106106011 A TW 106106011A TW I654746 B TWI654746 B TW I654746B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
electrode
semiconductor
channel
wafer
Prior art date
Application number
TW106106011A
Other languages
English (en)
Other versions
TW201733085A (zh
Inventor
小內俊之
小柳勝
Original Assignee
東芝記憶體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝記憶體股份有限公司 filed Critical 東芝記憶體股份有限公司
Publication of TW201733085A publication Critical patent/TW201733085A/zh
Application granted granted Critical
Publication of TWI654746B publication Critical patent/TWI654746B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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Abstract

根據本發明之一實施形態，設置有M(M為2以上之整數)個半導體晶片、與N(N為2以上之整數)通道量之貫通電極。將M個半導體晶片依序積層，貫通電極被埋入於上述半導體晶片而將上述半導體晶片於積層方向電性連接，上述貫通電極之連接目標於上述半導體晶片之1個或複數個上下層間更替。

Description

半導體裝置
本實施形態係關於一種半導體裝置。
為謀求半導體裝置之省空間化、高性能化及大容量化，而有時將半導體晶片積層。為取得所積層之半導體晶片之電性連接，而有時使用被稱為TSV(Through Silicon Via，矽穿孔)之貫通電極。 於使用此種TSV之半導體裝置中，為實現複數通道化而有時將進行通道切換之邏輯電路設置於各半導體晶片。
一實施形態之目的在於提供一種可謀求省空間化，並且可實現複數通道化之半導體裝置。 根據一實施形態，設置有M(M為2以上之整數)個半導體晶片、及N(N為2以上之整數)通道量之貫通電極。將M個半導體晶片依序積層。貫通電極被埋入於上述半導體晶片而將上述半導體晶片於積層方向電性連接。上述貫通電極之連接目標於上述半導體晶片之1個或複數個上下層間更替。
以下，參照隨附圖式對實施形態之半導體裝置詳細地進行說明。再者，並非藉由該等實施形態而限定本發明。 (第1實施形態) 圖1係表示第1實施形態之半導體裝置之概略構成之方塊圖。再者，於以下之實施形態中，作為半導體裝置而列舉非揮發性半導體裝置。作為非揮發性半導體裝置而列舉NAND(與非)記憶體。 圖1中，於非揮發性半導體裝置設置有NAND記憶體3及控制器2。NAND記憶體3連接於控制器2。控制器2經由主機IF(Inter Face，介面)而連接於主機1。NAND記憶體3可記憶由主機1處理之資料1。NAND記憶體3例如可搭載於SSD(Solid-State Drive，固態磁碟)，亦可搭載於SD卡(Secure Digital Memory Card，安全數位記憶卡)，還可搭載於USB(Universal Serial BUS，通用串列匯流排)記憶體。控制器2可驅動控制NAND記憶體3。再者，作為NAND記憶體3之驅動控制，可列舉例如NAND記憶體3之讀寫控制、區塊選擇、錯誤校正、耗損平均等。主機1可為個人電腦，亦可為數位相機等電子機器，還可為智慧型電話等移動終端。 於NAND記憶體3設置有依序積層之M(M為2以上之整數)個半導體晶片Cp0～CpM－1。於半導體晶片Cp0～CpM－1分別埋入有將半導體晶片Cp0～CpM－1於積層方向電性連接之貫通電極V0～VM－1。於各半導體晶片Cp0～CpM－1可設置N(N為2以上之整數)通道量之貫通電極V0～VM－1。貫通電極V0～VM－1能以使連接目標於半導體晶片Cp0～CpM－1之1個或複數個上下層間更替之方式連接。例如，貫通電極V0～VM－1可於半導體晶片Cp0～CpM－1之上下層間連接為龍捲風狀。 又，於NAND記憶體3設置有於與控制器2之間傳輸信號之介面部3A。介面部3A可針對每一半導體晶片Cp0～CpM－1而設置。介面部3A可處理N(N為2以上之整數)通道量之信號SH0～SHN－1。此處，介面部3A可相對於半導體晶片Cp0～CpM－1之各者，將N通道量之信號SH0～SHN－1中之僅1通道量之信號分別經由貫通電極V0～VM－1而與內部交換。此時，於各半導體晶片Cp0～CpM－1中，可將交換1通道量之信號之貫通電極V0～VM－1固定為N通道量之貫通電極V0～VM－1中之任1個。於各半導體晶片Cp0～CpM－1中，該固定之貫通電極V0～VM－1可選擇水平面之位置相等之貫通電極V0～VM－1。 N通道量之信號SH0～SHN－1可使用例如位址閂鎖啟動信號ALE、指令閂鎖啟動信號CLE、讀出啟動信號/RE(/表示低活動率信號)、RE、寫入啟動信號/WE、資料信號DQ、資料選通信號DQS、/DQS、晶片啟動信號/CE、寫入保護信號/WP、待命/忙碌信號RB、及晶片位址CADD。控制器2可使用該等信號而控制NAND記憶體3。 另一方面，主機IF根據應用NAND記憶體3之應用系統而變更。於NAND記憶體3應用於SSD(Solid-State Drive)之情形時，使用SAS(Serial Attached SCSI，串列連接之SCSI)、SATA(串列ATA)、及PCIe(Programmable Communications Interface，可編程通訊介面)，於NAND記憶體3應用於USB(Universal Serial Bus)記憶體等之情形時，使用USB，於NAND記憶體3應用於eMMC(embedded Multi-Media Card，嵌入式多媒體卡)之情形時，使用eMMC規格之介面，於NAND記憶體3應用於SD卡之情形時，使用SD記憶體規格之介面。 於控制器2設置有通道控制部2A。通道控制部2A控制NAND記憶體3之通道數。此處，通道控制部2A可藉由將同一信號輸入至N通道量之貫通電極V0～VM－1中之2個以上之貫通電極V0～VM－1而控制通道數。此時，通道控制部2A於使NAND記憶體3進行K(K為M以下之正整數)通道動作之情形時，可將N個通道分成K組，對同一組輸入同一信號，且對不同組輸入不同之信號。 控制器2接收自主機1經由主機IF而輸出之請求信號，且根據請求信號而產生晶片啟動信號/CE、指令閂鎖啟動信號CLE、位址閂鎖啟動信號ALE、寫入啟動信號/WE、讀出啟動信號/RE及寫入保護信號/WP等。 又，控制器2於根據自主機1接收到之請求信號而對NAND記憶體3寫入資料之情形時，經由1個以上且N個以下之通道而對NAND記憶體3供給資料。 又，控制器2於作為相對於自主機1接收到之請求信號之對主機1的回應而對NAND記憶體3進行資料讀出之情形時，經由1個以上且N個以下之通道自NAND記憶體3接收資料。 此處，相對於半導體晶片Cp0～CpM－1之各者，使N通道量之信號SH0～SHN－1中僅1通道量之信號分別經由貫通電極V0～VM－1而與內部進行交換，藉此，各半導體晶片Cp0～CpM－1無需根據所指定之通道而切換貫通電極V0～VM－1。因此，無需於各半導體晶片Cp0～CpM－1設置進行通道切換之邏輯電路，從而可謀求省空間化。 又，以使連接目標於半導體晶片Cp0～CpM－1之上下層間更替之方式連接貫通電極V0～VM－1，藉此即便於將交換1通道量之信號之貫通電極V0～VM－1於各半導體晶片Cp0～CpM－1中固定為水平面之位置相等的貫通電極V0～VM－1之情形時，亦可不針對每一半導體晶片Cp0～CpM－1而變更佈局即可謀求NAND記憶體3之複數通道化。 再者，貫通電極V0～VM－1亦可無需於半導體晶片Cp0～CpM－1之所有上下層間更替連接目標，而於一部分上下層間更替連接目標。例如，於在通道傳輸共通之信號之情形時，未必一定要更替連接目標，亦可將貫通電極V0～VM－1於上下層間連接成直線。 圖2係表示圖1之控制器及NAND記憶體之構成例之剖視圖。再者，於以下之說明中，以半導體晶片Cp0～CpM－1對應於2通道之情形為例。又，於圖2中，表示M為8之情形。 於圖2中，半導體晶片Cp0～Cp7依序積層，且安裝於支持基板12上。此處，於各半導體晶片Cp0～Cp7埋入有2通道量之貫通電極VA～VB。於各半導體晶片Cp0～Cp7，貫通電極VA以水平面之位置一致之方式配置，且貫通電極VB以水平面之位置一致之方式配置。又，於各半導體晶片Cp0～Cp7，貫通電極VA、VB可鄰接配置。貫通電極VA、VB以使連接目標於半導體晶片Cp0～Cp7之上下層間更替之方式連接。而且，貫通電極VA、VB經由焊錫球19A、19B而於半導體晶片Cp0～Cp7間連接。又，半導體晶片Cp0～C7經由接著層15而於上下層間連接。 於支持基板12之背面安裝有控制器晶片Ce1。此處，於支持基板12形成有配線23A、23B。而且，控制器晶片Ce1經由焊錫球18A、18B而連接於配線23A、23B。又，最下層之半導體晶片Cp0之貫通電極VA、VB連接於配線23A、23B，藉此控制器晶片Ce1與半導體晶片Cp0～Cp7電性連接。支持基板12經由焊錫球17而連接於安裝基板11。於安裝基板11之背面，設置有將安裝基板11連接於母基板之焊錫球16。 控制器晶片Ce1利用密封樹脂21而密封於安裝基板11上。半導體晶片Cp0～Cp7利用密封樹脂22而密封於支持基板12上。密封樹脂21、22之外周利用密封樹脂20密封，並且密封樹脂22之上部利用金屬板13密封。 圖3係表示圖2之半導體晶片之功能構成之方塊圖。再者，於圖3中，以半導體晶片Cp0為例，但對於半導體晶片Cp1～CpM－1亦相同。 於圖3中，半導體晶片Cp0包含邏輯控制部49、記憶體控制部50、記憶胞陣列41、列位址緩衝器43、列解碼器42、感測放大器44、資料暫存器45、行解碼器46、行位址緩衝器47、電壓產生電路56、輸入輸出(I/O)控制部48、指令暫存器53、位址暫存器52、狀態暫存器51、CSID(character set identifier，字元集識別符)暫存器54、待命/忙碌(R/B)電路55及邏輯電路57。 晶片啟動信號/CE、指令閂鎖啟動信號CLE、位址閂鎖啟動信號ALE、寫入啟動信號/WE、讀出啟動信號RE、/RE、寫入保護信號/WP、資料選通信號DQS、/DQS及晶片位址CADD自控制器2供給至邏輯控制部49。指令、位址及資料自控制器2經由信號線DQ0～DQ7而供給至I/O控制部48。 邏輯控制部49根據輸入信號而控制記憶體控制部50及I/O控制部48。指令暫存器53保持自I/O控制部48輸出之指令。位址暫存器52保持自I/O控制部48輸出之位址。 記憶體控制部50根據保持於指令暫存器53中之指令而控制列解碼器42、感測放大器44、資料暫存器45、行解碼器46、電壓產生電路56及R/B電路55，從而控制資料之寫入、讀出及抹除等。 R/B電路55根據記憶體控制部50之輸出信號而輸出待命/忙碌信號RB。電壓產生電路56根據記憶體控制部50之指示而產生寫入電壓、讀出電壓及抹除電壓等，且將該等電壓供給至記憶胞陣列41、列解碼器42、及感測放大器44。 記憶胞陣列41包含複數個NAND串。各NAND串係由第1、第2選擇電晶體與複數個記憶胞串聯連接而構成。於記憶胞設置有電荷儲存層及控制閘極電極。第1選擇電晶體連接於位元線，第2選擇電晶體連接於源極線。第1、第2選擇電晶體之閘極電極連接於第1、第2選擇線，各記憶胞之控制閘極電極分別連接於字元線。又，位元線之各者連接於感測放大器44。 列位址緩衝器43、行位址緩衝器47分別保持被保持於位址暫存器52中之列位址及行位址。列解碼器42對保持於列位址緩衝器43中之列位址進行解碼，且選擇記憶胞陣列41之第1、第2選擇線及字元線。行解碼器46對保持於行位址緩衝器47中之行位址進行解碼，且選擇記憶胞陣列41之位元線。 資料暫存器45於資料之寫入時，將自I/O控制部48供給之資料供給至感測放大器44。又，於資料之讀出時，保持藉由感測放大器44自選擇位元線檢測出之資料並供給至I/O控制部48。 感測放大器44於資料之寫入時，將保持於資料暫存器45中之資料寫入至所選擇之記憶胞中。又，於資料之讀出時，經由位元線而自所選擇之記憶胞讀出資料。 狀態暫存器51保持自記憶體控制部50輸出之資料之寫入、讀出及抹除例如是否正常結束等之狀態資料。保持於狀態暫存器51中之狀態資料經由I/O控制部48及控制器2而供給至主機1。 CSID暫存器54保持半導體晶片Cp0識別自身晶片之晶片識別資訊。保持於CSID暫存器54中之晶片識別資訊被供給至記憶體控制部50及邏輯電路57。 邏輯電路57根據晶片位址CADD及晶片識別資訊而產生內部啟動信號enb。由邏輯電路57產生之內部啟動信號enb被供給至I/O控制部48及邏輯控制部49。邏輯電路57於晶片位址CADD與晶片識別資訊一致時，可使內部啟動信號enb有效化。 圖4(a)係表示圖2之半導體晶片之2通道量之貫通電極之連接方法之一例之方塊圖，圖4(b)係表示圖2之半導體晶片之2通道量之貫通電極之連接方法之另一例之方塊圖。再者，於圖4(a)及圖4(b)之例中，僅表示半導體晶片Cp0～Cp2。 於圖4(a)及圖4(b)中，於半導體晶片Cp0設置有2通道量之貫通電極VA0、VB0。於半導體晶片Cp1設置有2通道量之貫通電極VA1、VB1。於半導體晶片Cp2設置有2通道量之貫通電極VA2、VB2。於貫通電極VA0上配置有貫通電極VA1，於貫通電極VA1上配置有貫通電極VA2。於貫通電極VB0上配置有貫通電極VB1，於貫通電極VB1上配置有貫通電極VB2。此處，貫通電極VA0～VA2、VB0～VB2以使連接目標於半導體晶片Cp0～Cp2之上下層間更替之方式連接。即，貫通電極VA0與貫通電極VB1電性連接，貫通電極VB1與貫通電極VA2電性連接。又，貫通電極VB0與貫通電極VA1電性連接，貫通電極VA1與貫通電極VB2電性連接。 又，如圖4(a)所示，於半導體晶片Cp0～Cp2分別設置有AND電路N0～N2。AND電路N0～N2之第1輸入端子分別連接於貫通電極VB0～VB2。對AND電路N0～N2之第2輸入端子分別輸入內部啟動信號enb0～enb2。於半導體晶片Cp0下配置有控制器晶片Ce1。於控制器晶片Ce1設置有控制器2。於控制器2設置有將2通道量之信號SH0、SH1輸入至半導體晶片Cp0～Cp2之輸入緩衝器B0、B1。而且，控制器2經由輸入緩衝器B0而輸出信號SH0，並且經由輸入緩衝器B1而輸出信號SH1。又，自控制器2將指定半導體晶片Cp0～Cp2之晶片位址CADD輸入至半導體晶片Cp0～Cp2。而且，於各半導體晶片Cp0～Cp2中，將自控制器2輸入之晶片位址CADD、與各半導體晶片Cp0～Cp2所保持之晶片識別資訊進行比較。而且，於晶片位址CADD與晶片識別資訊一致之半導體晶片Cp0～Cp2中，使內部啟動信號enb0～enb2有效化，且將信號SH0、SH1分別經由AND電路N0～N2而擷取至半導體晶片Cp0～Cp2之內部。 藉此，控制器2可對半導體晶片Cp0、Cp分配通道Ch0，並且對半導體晶片Cp1分配通道Ch1，從而可實現NAND記憶體3之2通道輸入。 又，如圖4(b)所示，於半導體晶片Cp0～Cp2分別設置有AND電路N0' ～N2'。AND電路N0'～N2'之第1輸入端子分別連接於貫通電極VB0～VB2。對AND電路N0'～N2'之第2輸入端子分別輸入內部啟動信號enb0'～enb2'。又，於控制器2設置有將2通道量之信號SH0、SH1自半導體晶片Cp0～Cp2輸出之輸出緩衝器B0'，B1'。而且，控制器2可經由輸出緩衝器B0'而接收信號SH0，並且可經由輸出緩衝器B1'而接收信號SH1。 此時，自控制器2將指定半導體晶片Cp0～Cp2之晶片位址CADD輸入至半導體晶片Cp0～Cp2。而且，於各半導體晶片Cp0～Cp2中，將自控制器2輸入之晶片位址CADD與各半導體晶片Cp0～Cp2所保持之晶片識別資訊進行比較。而且，於晶片位址CADD與晶片識別資訊一致之半導體晶片Cp0～Cp2中，使內部啟動信號enb0'～enb2'有效化，且將信號SH0、SH1分別經由AND電路N0'～N2'而自半導體晶片Cp0～Cp2之內部輸出。 藉此，控制器2可對半導體晶片Cp0、Cp2分配通道Ch0，並且可對半導體晶片Cp1分配通道Ch1，從而可實現NAND記憶體3之2通道輸出。 圖5係表示圖4之2通道量之貫通電極之連接配線例之剖視圖，圖6係表示圖5之2通道量之貫通電極之連接配線例之立體圖。再者，於圖5中，表示與圖4(a)之構成對應之連接配線例。又，於圖6中，表示半導體晶片Cp0之連接配線例。 於圖5及圖6中，於半導體晶片Cp0設置有配線H01A、H01B、H02A、H02B。配線H01A、H01B可形成於半導體晶片Cp0之第1層，配線H02A、H02B可形成於半導體晶片Cp0之第2層。於半導體晶片Cp1設置有配線H11A、H11B、H12A、H12B。配線H11A、H11B可形成於半導體晶片Cp1之第1層，配線H12A、H12B可形成於半導體晶片Cp1之第2層。 配線H01A連接於貫通電極VA0，配線H01B連接於貫通電極VB0。配線H01A連接於配線H02B，配線H01B連接於配線H02A。配線H02A可配置於貫通電極VA0上，配線H02B可配置於貫通電極VB0上。 配線H11A連接於貫通電極VA1，配線H11B連接於貫通電極VB1。配線H11A連接於配線H12B，配線H11B連接於配線H12A。配線H12A可配置於貫通電極VA1上，配線H12B可配置於貫通電極VB1上。 配線H02A經由焊錫球19A而連接於貫通電極VA1，配線H02B經由焊錫球19B而連接於貫通電極VB1。 此處，藉由使用2層配線，可不變更貫通電極VA0、VB0、VA1、VB1之位置而將貫通電極VA0連接於貫通電極VB1，且將貫通電極VB0連接於貫通電極VA1。 又，於控制器2設置有通道控制部2A，於通道控制部2A設置有MOS電晶體T0～T2。MOS電晶體T0之汲極連接於輸入緩衝器B0，MOS電晶體T1、T2之汲極連接於輸入緩衝器B1。對MOS電晶體T0、T1之源極輸入信號SH0，MOS電晶體T2之源極被輸入信號SH1。對MOS電晶體T0～T2之閘極分別輸入控制信號f0～f2。 而且，控制器2於使NAND記憶體3進行2通道動作之情形時，可將控制信號f0、f2設定為高位準，且將控制信號f1設定為低位準。藉此，控制器2可將信號SH0供給至半導體晶片Cp0，並且可將信號SH1供給至半導體晶片Cp1，從而可使NAND記憶體3進行2通道動作。 另一方面，控制器2於使NAND記憶體3進行1通道動作之情形時，可將控制信號f0、f1設定為高位準，且將控制信號f2設定為低位準。藉此，控制器2可將信號SH0供給至半導體晶片Cp0、Cp1，從而可使NAND記憶體3進行1通道動作。 (第2實施形態) 圖7係表示應用於第2實施形態之半導體裝置之4通道量之貫通電極之連接方法之方塊圖。再者，於圖7之例中表示8層量之半導體晶片Cp10～Cp18。又，於圖7之例中，表示使輸入至半導體晶片Cp10～Cp18之信號4通道化之構成，但亦可同樣應用於使自半導體晶片Cp10～Cp18輸出之信號4通道化之構成。 於圖7中，於半導體晶片Cp10設置有4通道量之貫通電極VA10～VD10。於半導體晶片Cp11設置有4通道量之貫通電極VA11～VD11。於半導體晶片Cp12設置有4通道量之貫通電極VA12～VD12。於半導體晶片Cp13設置有4通道量之貫通電極VA13～VD13。於半導體晶片Cp14設置有4通道量之貫通電極VA14～VD14。於半導體晶片Cp15設置有4通道量之貫通電極VA15～VD15。於半導體晶片Cp16設置有4通道量之貫通電極VA16～VD16。於半導體晶片Cp17設置有4通道量之貫通電極VA17～VD17。 貫通電極VA10～VA17依序積層，貫通電極VB10～VB17依序積層，貫通電極VC10～VC17依序積層，貫通電極VD10～VD17依序積層。此處，貫通電極VA10～VA17、VB10～VB17、VC10～VC17、VD10～VD17以使連接目標於半導體晶片Cp10～Cp18之上下層間依序更替之方式連接。例如，於半導體晶片Cp10、Cp11間，貫通電極VD10電性連接於貫通電極VA11，貫通電極VA10電性連接於貫通電極VB11。又，貫通電極VB10電性連接於貫通電極VC11，貫通電極VC10電性連接於貫通電極VD11。 又，於半導體晶片Cp10～Cp18分別設置有AND電路N10～N17。AND電路N10～N17之第1輸入端子分別連接於貫通電極VC10～VC17。對AND電路N10～N17之第2輸入端子分別輸入內部啟動信號enb0～enb7。於半導體晶片Cp10下配置有控制器晶片Ce2。於控制器晶片Ce2設置有控制器2'。於控制器2'設置有將4通道量之信號SH0～SH3輸入至半導體晶片Cp10～Cp18之輸入緩衝器B10～B13。而且，控制器2'經由輸入緩衝器B10而輸出信號SH0，經由輸入緩衝器B11而輸出信號SH1，經由輸入緩衝器B12而輸出信號SH2，且經由輸入緩衝器B13而輸出信號SH3。又，自控制器2'將指定半導體晶片Cp10～Cp18之晶片位址CADD輸入至半導體晶片Cp10～Cp18。而且，於各半導體晶片Cp10～Cp18中，將自控制器2'輸入之晶片位址CADD、與各半導體晶片Cp10～Cp18所保持之晶片識別資訊進行比較。而且，於晶片位址CADD與晶片識別資訊一致之半導體晶片Cp10～Cp18中，使內部啟動信號enb0～enb7有效化，且將信號SH0～SH4分別經由AND電路N10～N17而擷取至半導體晶片Cp10～Cp18之內部。 藉此，控制器2'可對半導體晶片Cp13、Cp17分配通道Ch0，對半導體晶片Cp12、Cp16分配通道Ch1，對半導體晶片Cp11、Cp15分配通道Ch2，且對半導體晶片Cp10、Cp14分配通道Ch3，從而可實現NAND記憶體3之4通道輸入。 圖8係表示圖7之4通道量之貫通電極之連接配線例之剖視圖。再者，於圖8中，表示半導體晶片Cp10、Cp11之連接配線例。又，於圖8中省略圖7之輸入緩衝器B10～B13。 於圖8中，於半導體晶片Cp10設置有配線01A～01D、02A～02D。配線01A～01D可形成於半導體晶片Cp10之第1層，配線02A～02D可形成於半導體晶片Cp10之第2層。於半導體晶片Cp11設置有配線11A～11D、12A～12B。配線11A～11D可形成於半導體晶片Cp11之第1層，配線12A～12B可形成於半導體晶片Cp11之第2層。 配線01A連接於貫通電極VA10，配線01B連接於貫通電極VB10，配線01C連接於貫通電極VC10，配線01D連接於貫通電極VD10。配線01A連接於配線02B，配線01B連接於配線02C，配線01C連接於配線02D，配線01D連接於配線02A。配線02A可配置於貫通電極VA10上，配線02B可配置於貫通電極VB10上，配線02C可配置於貫通電極VC10上，配線02D可配置於貫通電極VD10上。 配線11A連接於貫通電極VA11，配線11B連接於貫通電極VB11，配線11C連接於貫通電極VC11，配線11D連接於貫通電極VD11。配線11A連接於配線12B，配線11B連接於配線12C，配線11C連接於配線12D，配線11D連接於配線12A。配線12A可配置於貫通電極VA11上，配線12B可配置於貫通電極VB11上，配線12C可配置於貫通電極VC11上，配線12D可配置於貫通電極VD11上。 配線12A經由焊錫球52A而連接於貫通電極VA10，配線12B經由焊錫球52B而連接於貫通電極VB10，配線12C經由焊錫球52C而連接於貫通電極VC10，配線12D經由焊錫球52D而連接於貫通電極VD10。配線01A～01D分別經由焊錫球51A～51D而連接於控制器晶片Ce2。 此處，藉由使用2層配線，可不變更貫通電極VA10～VD10、VA11～VD11之位置而將貫通電極VA10連接於貫通電極VD11，將貫通電極VB10連接於貫通電極VA11，將貫通電極VC10連接於貫通電極VB11，且將貫通電極VD10連接於貫通電極VC11。 又，於控制器2'設置有通道控制部2A'，於通道控制部2A'設置有MOS電晶體T11～T17。MOS電晶體T10、T11之汲極連接於焊錫球51C，MOS電晶體T12、T13之汲極連接於焊錫球51B，MOS電晶體T14之汲極連接於焊錫球51A，MOS電晶體T15～T16之汲極連接於焊錫球51D。對MOS電晶體T11、T13、T14、T17之源極輸入信號SH0，MOS電晶體T12之源極可輸入信號SH1，MOS電晶體T10、T16之源極可輸入信號SH2，MOS電晶體T15之源極可輸入信號SH3。對MOS電晶體T10～T17之閘極分別輸入控制信號f0～f7。 而且，控制器2'於使NAND記憶體3進行4通道動作之情形時，可將控制信號f0、f2、f4、f5設定為高位準，且將控制信號f1、f3、f6、f7設定為低位準。藉此，控制器2'可將信號SH0供給至半導體晶片Cp13、Cp17，將信號SH1供給至半導體晶片Cp12、Cp16，將信號SH2供給至半導體晶片Cp11、Cp15，且將信號SH3供給至半導體晶片Cp10、Cp14，從而可使NAND記憶體3進行4通道動作。 控制器2'於使NAND記憶體3進行3通道動作之情形時，例如可將控制信號f0、f2、f4、f7設定為高位準，且將控制信號f1、f3、f5、f6設定為低位準。藉此，控制器2'可將信號SH0供給至半導體晶片Cp13、Cp17，將信號SH1供給至半導體晶片Cp12、Cp16，將信號SH2供給至半導體晶片Cp11、Cp15，且將信號SH3供給至半導體晶片Cp10、Cp14，從而可使NAND記憶體3進行3通道動作。 控制器2'於使NAND記憶體3進行2通道動作之情形，例如可將控制信號f0、f3、f4、f6設定為高位準，且將控制信號f1、f2、f5、f7設定為低位準。藉此，控制器2'可將信號SH0供給至半導體晶片Cp12、Cp13、Cp16、Cp17，且可將信號SH2供給至半導體晶片Cp10、Cp11、Cp14、Cp15，從而可使NAND記憶體3進行2通道動作。 控制器2'於使NAND記憶體3進行1通道動作之情形，可將控制信號f1、f3、f4、f7設定為高位準，且將控制信號f0、f2、f5、f6設定為低位準。藉此，控制器2'可將信號SH0供給至半導體晶片Cp10～Cp18，從而可使NAND記憶體3進行1通道動作。 圖9係表示晶片啟動信號相對於圖8之4通道量之信號之分配例之圖。 於圖9中，控制器2'可對N通道量之信號控制晶片啟動信號之分配數。例如，於1通道動作之情形時，可對4通道量之信號SH0～SH3分配共通之晶片啟動信號CE0。藉此，可減少伴隨晶片切換之晶片啟動信號之切換次數，從而可使控制簡化。或者於1通道動作之情形時，亦可對4通道量之信號SH0～SH3分配不同之晶片啟動信號CE0～CE3。藉此，可使非選擇晶片非活化，從而可降低消耗電力。 圖10(a)係表示圖8之4通道量之貫通電極之連接配線例之俯視圖，圖10(b)～圖10(e)係將圖10(a)之連接配線針對每一配線層分解而表示之俯視圖。再者，於圖10(a)～圖10(e)中，表示圖8之半導體晶片Cp11之連接配線例。 於圖10(a)中，貫通電極VA10～VD10、VA11～VD11以正方形配置。配線11A～11D分別配置於貫通電極VA11～VD11上。於配線11A～11D上，於配線11D、11A～11C之方向分別附加有引出部LA～LD。配線12A～12D分別配置於配線11D、11A～11C上。於配線12A～12D上，於配線12B～12D、12A之方向分別附加有引出部MA～MD。於配線12A～12D上分別配置有焊錫球52A～52D。而且，引出部LA～LD分別經由插塞電極PA～PD而分別連接於引出部MA～MD。 藉此，可抑制佈局面積之增大，並且可將貫通電極VA10連接於貫通電極VD11，將貫通電極VB10連接於貫通電極VA11，將貫通電極VC10連接於貫通電極VB11，且將貫通電極VD10連接於貫通電極VC11。 對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出，並未意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且可於不脫離發明之主旨之範圍進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍中記載之發明及其均等之範圍。
01A‧‧‧配線
01B‧‧‧配線
01C‧‧‧配線
01D‧‧‧配線
02A‧‧‧配線
02B‧‧‧配線
02C‧‧‧配線
02D‧‧‧配線
1‧‧‧主機
2‧‧‧控制器
2' ‧‧‧控制器
2A‧‧‧通道控制部
2A'‧‧‧通道控制部
3‧‧‧NAND記憶體
3A‧‧‧介面部
11‧‧‧基板
11A‧‧‧配線
11B‧‧‧配線
11C‧‧‧配線
11D‧‧‧配線
12‧‧‧支持基板
12A‧‧‧配線
12B‧‧‧配線
12C‧‧‧配線
12D‧‧‧配線
13‧‧‧金屬板
15‧‧‧接著層
16‧‧‧焊錫球
17‧‧‧焊錫球
18A‧‧‧焊錫球
18B‧‧‧焊錫球
19A‧‧‧焊錫球
19B‧‧‧焊錫球
20‧‧‧密封樹脂
21‧‧‧密封樹脂
22‧‧‧密封樹脂
23A‧‧‧配線
23B‧‧‧配線
41‧‧‧記憶胞陣列
42‧‧‧列解碼器
43‧‧‧列位址緩衝器
44‧‧‧感測放大器
45‧‧‧資料暫存器
46‧‧‧行解碼器
47‧‧‧行位址緩衝器
48‧‧‧I/O控制部
49‧‧‧邏輯控制部
50‧‧‧記憶體控制部
51‧‧‧狀態暫存器
51A‧‧‧焊錫球
51B‧‧‧焊錫球
51C‧‧‧焊錫球
51D‧‧‧焊錫球
52‧‧‧位址暫存器
52A‧‧‧焊錫球
52B‧‧‧焊錫球
52C‧‧‧焊錫球
52D‧‧‧焊錫球
53‧‧‧指令暫存器
54‧‧‧CSID暫存器
55‧‧‧R/B電路
56‧‧‧電壓產生電路
57‧‧‧邏輯電路
ALE‧‧‧位址閂鎖啟動信號
B0‧‧‧輸入緩衝器
B1‧‧‧輸入緩衝器
B0'‧‧‧輸出緩衝器
B1'‧‧‧輸出緩衝器
B10‧‧‧輸入緩衝器
B11‧‧‧輸入緩衝器
B12‧‧‧輸入緩衝器
B13‧‧‧輸入緩衝器
CADD ‧‧‧晶片位址
Ce1‧‧‧控制器晶片
Ce2‧‧‧控制器晶片
CE0‧‧‧晶片啟動信號
CE1‧‧‧晶片啟動信號
CE2‧‧‧晶片啟動信號
CE3‧‧‧晶片啟動信號
Ch0‧‧‧通道
Ch1‧‧‧通道
Ch2‧‧‧通道
Ch3‧‧‧通道
CLE‧‧‧指令閂鎖啟動信號
Cp0‧‧‧半導體晶片
Cp1‧‧‧半導體晶片
Cp2‧‧‧半導體晶片
Cp3‧‧‧半導體晶片
Cp4‧‧‧半導體晶片
Cp5‧‧‧半導體晶片
Cp6‧‧‧半導體晶片
Cp7‧‧‧半導體晶片
Cp8‧‧‧半導體晶片
Cp9‧‧‧半導體晶片
Cp10‧‧‧半導體晶片
Cp11‧‧‧半導體晶片
Cp12‧‧‧半導體晶片
Cp13‧‧‧半導體晶片
Cp14‧‧‧半導體晶片
Cp15‧‧‧半導體晶片
Cp16‧‧‧半導體晶片
Cp17‧‧‧半導體晶片
CpM－1‧‧‧半導體晶片
CpM－2‧‧‧半導體晶片
DQ0‧‧‧信號線
DQ1‧‧‧信號線
DQ7‧‧‧信號線
DQS‧‧‧資料選通信號
enb0‧‧‧內部啟動信號
enb1‧‧‧內部啟動信號
enb2‧‧‧內部啟動信號
enb3‧‧‧內部啟動信號
enb4‧‧‧內部啟動信號
enb5‧‧‧內部啟動信號
enb6‧‧‧內部啟動信號
enb7‧‧‧內部啟動信號
enb0'‧‧‧內部啟動信號
enb1'‧‧‧內部啟動信號
enb2'‧‧‧內部啟動信號
H01A‧‧‧配線
H01B‧‧‧配線
H02A‧‧‧配線
H02B‧‧‧配線
H11A‧‧‧配線
H11B‧‧‧配線
H12A‧‧‧配線
H12B‧‧‧配線
LA‧‧‧引出部
LB‧‧‧引出部
LC‧‧‧引出部
LD‧‧‧引出部
MA‧‧‧引出部
MB‧‧‧引出部
MC‧‧‧引出部
MD‧‧‧引出部
N0‧‧‧AND電路
N1‧‧‧AND電路
N2‧‧‧AND電路
N10‧‧‧AND電路
N11‧‧‧AND電路
N12‧‧‧AND電路
N13‧‧‧AND電路
N14‧‧‧AND電路
N15‧‧‧AND電路
N16‧‧‧AND電路
N17‧‧‧AND電路
N0'‧‧‧AND電路
N1'‧‧‧AND電路
N2'‧‧‧AND電路
PA‧‧‧插塞電極
PB‧‧‧插塞電極
PC‧‧‧插塞電極
PD‧‧‧插塞電極
RB‧‧‧待命/忙碌信號
RE‧‧‧讀出啟動信號
SH0～SHN－1‧‧‧信號
SH1‧‧‧信號
SH2‧‧‧信號
SH3‧‧‧信號
T0‧‧‧MOS電晶體
T1‧‧‧MOS電晶體
T2‧‧‧MOS電晶體
T10‧‧‧MOS電晶體
T11‧‧‧MOS電晶體
T12‧‧‧MOS電晶體
T13‧‧‧MOS電晶體
T14‧‧‧MOS電晶體
T15‧‧‧MOS電晶體
T16‧‧‧MOS電晶體
T17‧‧‧MOS電晶體
V0‧‧‧貫通電極
V1‧‧‧貫通電極
V2‧‧‧貫通電極
VA‧‧‧貫通電極
VA0‧‧‧貫通電極
VA1‧‧‧貫通電極
VA10‧‧‧貫通電極
VA11‧‧‧貫通電極
VA12‧‧‧貫通電極
VA13‧‧‧貫通電極
VA14‧‧‧貫通電極
VA15‧‧‧貫通電極
VA16‧‧‧貫通電極
VA17‧‧‧貫通電極
VA20‧‧‧貫通電極
VB‧‧‧貫通電極
VB0‧‧‧貫通電極
VB1‧‧‧貫通電極
VB2‧‧‧貫通電極
VB10‧‧‧貫通電極
VB11‧‧‧貫通電極
VB12‧‧‧貫通電極
VB13‧‧‧貫通電極
VB14‧‧‧貫通電極
VB15‧‧‧貫通電極
VB16‧‧‧貫通電極
VB17‧‧‧貫通電極
VC10‧‧‧貫通電極
VC11‧‧‧貫通電極
VC12‧‧‧貫通電極
VC13‧‧‧貫通電極
VC14‧‧‧貫通電極
VC15‧‧‧貫通電極
VC16‧‧‧貫通電極
VC17‧‧‧貫通電極
VD10‧‧‧貫通電極
VD11‧‧‧貫通電極
VD12‧‧‧貫通電極
VD13‧‧‧貫通電極
VD14‧‧‧貫通電極
VD15‧‧‧貫通電極
VD16‧‧‧貫通電極
VD17‧‧‧貫通電極
VM－1‧‧‧貫通電極
VM－2‧‧‧貫通電極
f0‧‧‧控制信號
f1‧‧‧控制信號
f2‧‧‧控制信號
f3‧‧‧控制信號
f4‧‧‧控制信號
f5‧‧‧控制信號
f6‧‧‧控制信號
f7‧‧‧控制信號
f15‧‧‧控制信號
f16‧‧‧控制信號
f17‧‧‧控制信號
/DQS‧‧‧資料選通信號
/RE‧‧‧讀出啟動信號
/WE‧‧‧寫入啟動信號
/WP‧‧‧寫入保護信號
圖1係表示第1實施形態之半導體裝置之概略構成之方塊圖。 圖2係表示圖1之控制器及NAND記憶體之構成例之剖視圖。 圖3係表示圖2之半導體晶片之功能構成之方塊圖。 圖4(a)係表示圖2之半導體晶片之2通道量之貫通電極之連接方法之一例之方塊圖，圖4(b)係表示圖2之半導體晶片之2通道量之貫通電極之連接方法之另一例之方塊圖。 圖5係表示圖4之2通道量之貫通電極之連接配線例之剖視圖。 圖6係表示圖5之2通道量之貫通電極之連接配線例之立體圖。 圖7係表示應用於第2實施形態之半導體裝置之4通道量之貫通電極之連接方法之方塊圖。 圖8係表示圖7之4通道量之貫通電極之連接配線例之剖視圖。 圖9係表示晶片啟動信號相對於圖8之4通道量之信號之分配例之圖。 圖10(a)係表示圖8之4通道量之貫通電極之連接配線例之俯視圖，圖10(b)～圖10(e)係將圖10(a)之連接配線按每一配線層分解而表示之俯視圖。

Claims (23)

  1. 一種半導體裝置，其包含：半導體晶片，其包括依序積層之第1半導體晶片、第2半導體晶片及第3半導體晶片；電極，其埋入於上述半導體晶片，將上述半導體晶片於積層方向電性連接；及控制器，其係控制上述第1半導體晶片、上述第2半導體晶片及上述第3半導體晶片；其中上述電極之連接目標(connection destination)係於上述半導體晶片之上下層間更替(exchanged)；上述第1半導體晶片中之第1電極係電性連接至上述第2半導體晶片中之第2電極及上述第3半導體晶片中之第1電極，且上述第1半導體晶片中之第2電極係電性連接至上述第2半導體晶片中之第1電極及上述第3半導體晶片中之第2電極；上述第1及第3半導體晶片係屬於第1通道，且上述第2半導體晶片係屬於第2通道；且於使上述第1半導體晶片、上述第2半導體晶片及上述第3半導體晶片進行2通道動作之情形時，上述控制器對上述第1通道及上述第2通道輸入個別之信號(separate signal)，於使上述第1半導體晶片、上述第2半導體晶片及上述第3半導體晶片進行1通道動作之情形時，上述控制器對上述第1通道及上述第2通道輸入共通之信號(common signal)。
  2. 如請求項1之半導體裝置，其中上述第3半導體晶片係積層於上述第2半導體晶片上；上述第2半導體晶片係積層於上述第1半導體晶片上；上述電極包括第1及第2電極；上述第1半導體晶片中之上述第1電極係電性連接至上述第2半導體晶片中之上述第2電極；上述第1半導體晶片中之上述第2電極係電性連接至上述第2半導體晶片中之上述第1電極；上述第2半導體晶片中之上述第1電極係電性連接至上述第3半導體晶片中之上述第2電極；且上述第2半導體晶片中之上述第2電極係電性連接至上述第3半導體晶片中之上述第1電極。
  3. 如請求項1之半導體裝置，其包含：配線層；上述配線層係設置於上述各別(individual)半導體晶片中，且於上述半導體晶片之上下層間，切換(switch)上述電極之上述連接目標。
  4. 如請求項1之半導體裝置，其中上述半導體晶片包含介面部，該介面部可將複數通道量之信號(signal for plural channels)中僅1通道量之信號(signal for one channel)經由上述電極而與上述半導體晶片之內部交換(communicating)。
  5. 如請求項4之半導體裝置，其中於上述各別半導體晶片中，交換上述1通道量之信號所經由之上述電極係固定為用於上述複數通道量之電極中之任1個。
  6. 如請求項4之半導體裝置，其中上述介面部包含AND電路，該AND電路係根據內部啟動信號(internal enable signal)而將上述1通道量之信號擷取至內部(take in)。
  7. 如請求項6之半導體裝置，其中上述半導體晶片包含邏輯電路，該邏輯電路係根據晶片位址與晶片識別資訊而產生上述內部啟動信號。
  8. 如請求項1之半導體裝置，其中上述控制器包含通道控制部，其控制以上述半導體晶片實現之通道數。
  9. 如請求項1之半導體裝置，其中上述控制器配置於最上層之半導體晶片上或最下層之半導體晶片下。
  10. 如請求項1之半導體裝置，其中上述控制器為控制器晶片。
  11. 如請求項1之半導體裝置，其中上述半導體晶片為記憶體。
  12. 如請求項1之半導體裝置，其中上述半導體晶片為NAND記憶體。
  13. 如請求項1之半導體裝置，其中上述第2半導體晶片之上述第1電極係配置於上述第1半導體晶片之上述第1電極之上(above)，上述第3半導體晶片之上述第1電極係配置於上述第2半導體晶片之上述第1電極之上，且上述第2半導體晶片之上述第2電極係配置於上述第1半導體晶片之上述第2電極之上，上述第3半導體晶片之上述第2電極係配置於上述第2半導體晶片之上述第2電極之上。
  14. 如請求項1之半導體裝置，其中上述第1半導體晶片包含第1介面部，其可僅將第1通道之信號經由上述第1電極而與上述第1半導體晶片之內部交換(communicating)，上述第2半導體晶片包含第2介面部，其可僅將第2通道之信號經由上述第2電極而與上述第2半導體晶片之內部交換，且上述第3半導體晶片包含第3介面部，其可僅將第1通道之信號經由上述第1電極而與上述第3半導體晶片之內部交換。
  15. 如請求項1之半導體裝置，其中上述第1至第3半導體晶片之各者具有第1面及與上述第1面相反之第2面，上述第1至第3半導體晶片之各者於晶片中包含配線層，且上述第1及第2電極之各者係設置於從上述第1及第2面之一者至上述配線層之對應部分。
  16. 如請求項1之半導體裝置，其中上述第1至第3半導體晶片之各者具有第1面及與上述第1面相反之第2面，上述第1至第3半導體晶片之各者於晶片中包含配線層，且上述第1及第2電極之各者設置於從上述第1及第2面之一者至上述配線層之對應部分，上述第2半導體晶片之上述第1電極係配置於上述第1半導體晶片之上述第1電極之上，上述第3半導體晶片之上述第1電極係配置於上述第2半導體晶片之上述第1電極之上，且上述第2半導體晶片之上述第2電極係配置於上述第1半導體晶片之上述第2電極之上，上述第3半導體晶片之上述第2電極係配置於上述第2半導體晶片之上述第2電極之上，上述半導體裝置進而包含：居於(interposed)上述第1半導體晶片與上述第2半導體晶片之間及居於上述第2半導體晶片與上述第3半導體晶片之間的焊錫球(solder ball)，上述第1半導體晶片中之上述第1電極係經由上述配線層及第1焊錫球而電性連接至上述第2半導體晶片中之上述第2電極，上述第1半導體晶片中之上述第2電極係經由上述配線層及第2焊錫球而電性連接至上述第2半導體晶片中之上述第1電極，上述第2半導體晶片中之上述第1電極係經由上述配線層及第3焊錫球而電性連接至上述第3半導體晶片中之上述第2電極，上述第2半導體晶片中之上述第2電極係經由上述配線層及第4焊錫球而電性連接至上述第3半導體晶片中之上述第1電極。
  17. 如請求項1之半導體裝置，其中上述第1至第3半導體晶片之各者進而包含：連接至上述第2電極且未連接至上述第1電極之邏輯電路。
  18. 如請求項17之半導體裝置，其中上述邏輯電路產生晶片啟動信號(chip enable signal)。
  19. 一種半導體裝置，其包含：半導體晶片，其包括依序積層之第1半導體晶片、第2半導體晶片及第3半導體晶片；及電極，其埋入於上述半導體晶片，將上述半導體晶片於積層方向電性連接；其中上述電極之連接目標係於上述半導體晶片之上下層間更替；上述第1半導體晶片中之第1電極係電性連接至上述第2半導體晶片中之第2電極及上述第3半導體晶片中之第1電極，且上述第1半導體晶片中之第2電極係電性連接至上述第2半導體晶片中之第1電極及上述第3半導體晶片中之第2電極；上述第1及第3半導體晶片係屬於第1通道，且上述第2半導體晶片係屬於第2通道；上述半導體晶片包含介面部，該介面部可將複數通道量之信號中僅1通道量之信號經由上述電極而與上述半導體晶片之內部交換；上述介面部包含AND電路，該AND電路係根據內部啟動信號而將上述1通道量之信號擷取至內部。
  20. 如請求項19之半導體裝置，其中上述半導體晶片包含邏輯電路，該邏輯電路係根據晶片位址與晶片識別資訊而產生上述內部啟動信號。
  21. 一種半導體裝置，其包含：半導體晶片，其包括依序積層之第1半導體晶片、第2半導體晶片及第3半導體晶片；及電極，其埋入於上述半導體晶片，將上述半導體晶片於積層方向電性連接；其中上述電極之連接目標係於上述半導體晶片之上下層間更替；上述第1半導體晶片中之第1電極係電性連接至上述第2半導體晶片中之第2電極及上述第3半導體晶片中之第1電極，且上述第1半導體晶片中之第2電極係電性連接至上述第2半導體晶片中之第1電極及上述第3半導體晶片中之第2電極；上述第1及第3半導體晶片係屬於第1通道，且上述第2半導體晶片係屬於第2通道；上述第1半導體晶片包含第1介面部，其可僅將第1通道之信號經由上述第1電極而與上述第1半導體晶片之內部交換，上述第2半導體晶片包含第2介面部，其可僅將第2通道之信號經由上述第2電極而與上述第2半導體晶片之內部交換，且上述第3半導體晶片包含第3介面部，其可僅將第1通道之信號經由上述第1電極而與上述第3半導體晶片之內部交換。
  22. 一種半導體裝置，其包含：半導體晶片，其包括依序積層之第1半導體晶片、第2半導體晶片及第3半導體晶片；及電極，其埋入於上述半導體晶片，將上述半導體晶片於積層方向電性連接；其中上述電極之連接目標係於上述半導體晶片之上下層間更替；上述第1半導體晶片中之第1電極係電性連接至上述第2半導體晶片中之第2電極及上述第3半導體晶片中之第1電極，且上述第1半導體晶片中之第2電極係電性連接至上述第2半導體晶片中之第1電極及上述第3半導體晶片中之第2電極；上述第1及第3半導體晶片係屬於第1通道，且上述第2半導體晶片係屬於第2通道；且上述第1至第3半導體晶片之各者進而包含：連接至上述第2電極且未連接至上述第1電極之邏輯電路。
  23. 如請求項22之半導體裝置，其中上述邏輯電路產生晶片啟動信號。
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