JP7226055B2 - 半導体装置およびシステム - Google Patents
半導体装置およびシステム Download PDFInfo
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- JP7226055B2 JP7226055B2 JP2019078778A JP2019078778A JP7226055B2 JP 7226055 B2 JP7226055 B2 JP 7226055B2 JP 2019078778 A JP2019078778 A JP 2019078778A JP 2019078778 A JP2019078778 A JP 2019078778A JP 7226055 B2 JP7226055 B2 JP 7226055B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
- G11C29/886—Masking faults in memories by using spares or by reconfiguring with partially good memories combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Memory System (AREA)
- Hardware Redundancy (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
10a、10b スイッチ
20 プログラム部
30 メモリモジュールインタフェース
40 シリコンインターポーザ
50 パッケージ基板
60 マザーボード
70 CPUコア
72、74 メモリアクセスコントローラ
76 選択部
100、102 積層メモリ(半導体装置)
200、202 CPU
300、302 メモリモジュール
LOG 論理ダイ
MEM メモリダイ
SEL セレクタ
TE 貫通電極
Claims (7)
- 複数のメモリダイと論理ダイとが積層された半導体装置であって、
前記論理ダイは、
前記半導体装置に接続されるメモリ装置用のメモリインタフェースと、
前記半導体装置を制御する制御装置が有する複数のチャネルの各々に接続されたスイッチを含むスイッチ部と、を有し、
前記スイッチ部は、
前記複数のチャネルのいずれかを、前記メモリインタフェースまたは前記複数のメモリダイのいずれかに接続する第1のスイッチと、
前記複数のチャネルの他のいずれかを、互いに異なる前記メモリダイのいずれかに接続する第2のスイッチと、を有することを特徴とする半導体装置。 - 積層された前記複数のメモリダイは、前記複数のメモリダイの各々に設けられる貫通電極を介して、メモリダイ毎に前記論理ダイに接続され、
前記複数のメモリダイのいずれかは、互いに異なる貫通電極を介して、互いに異なる前記スイッチに接続されること、を特徴とする請求項1に記載の半導体装置。 - 積層された前記複数のメモリダイは、前記複数のメモリダイの各々に設けられる貫通電極を介して、メモリダイ毎に前記論理ダイに接続され、
前記複数のメモリダイのいずれかは、共通の貫通電極を介して、互いに異なる前記スイッチに接続されること、を特徴とする請求項1に記載の半導体装置。 - 前記メモリ装置は、DDRインタフェースで動作し、
前記メモリインタフェースは、前記制御装置が出力する前記メモリ装置に対するメモリアクセス要求を、DDRインタフェースに変換する変換部を有すること、を特徴とする請求項1ないし請求項3のいずれか1項に記載の半導体装置。 - 積層された前記複数のメモリダイが正常に動作するかに基づいて、前記スイッチ部の切り替え状態がプログラムされるプログラム部を有すること、を特徴とする請求項1ないし請求項4のいずれか1項に記載の半導体装置。
- 複数のメモリダイと論理ダイとが積層された半導体装置と、前記半導体装置を制御する制御装置とを有するシステムであって、
前記論理ダイは、
前記半導体装置に接続されるメモリ装置用のメモリインタフェースと、
前記半導体装置を制御する制御装置が有する複数のチャネルの各々に接続されたスイッチを含むスイッチ部と、を有し、
前記スイッチ部は、
前記複数のチャネルのいずれかを、前記メモリインタフェースまたは前記複数のメモリダイのいずれかに接続する第1のスイッチと、
前記複数のチャネルの他のいずれかを、互いに異なる前記メモリダイのいずれかに接続する第2のスイッチと、を有することを特徴とするシステム。 - 前記制御装置は、
前記メモリダイのアクセスを制御する第1のメモリアクセス制御部と、
前記メモリインタフェースを介して前記半導体装置に接続される前記メモリ装置のアクセスを制御する第2のメモリアクセス制御部と、
前記第1のメモリアクセス制御部が生成する第1のメモリアクセス要求および前記第2のメモリアクセス制御部が生成する第2のメモリアクセス要求を前記複数のチャネルのいずれに出力するかを選択する選択部と、を有することを特徴とする請求項6に記載のシステム。
Priority Applications (3)
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JP2019078778A JP7226055B2 (ja) | 2019-04-17 | 2019-04-17 | 半導体装置およびシステム |
US16/837,564 US11074947B2 (en) | 2019-04-17 | 2020-04-01 | Semiconductor memory apparatus and data processing system |
KR1020200044643A KR102295895B1 (ko) | 2019-04-17 | 2020-04-13 | 반도체 장치 및 시스템 |
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JP2020177720A JP2020177720A (ja) | 2020-10-29 |
JP7226055B2 true JP7226055B2 (ja) | 2023-02-21 |
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US11495318B2 (en) * | 2020-06-03 | 2022-11-08 | Nanya Technology Corporation | Memory device and method for using shared latch elements thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090161401A1 (en) | 2007-12-24 | 2009-06-25 | Christoph Bilger | Multi-die Memory, Apparatus and Multi-die Memory Stack |
US20100088460A1 (en) | 2008-10-07 | 2010-04-08 | Micron Technology, Inc. | Memory apparatus, systems, and methods |
WO2016042603A1 (ja) | 2014-09-17 | 2016-03-24 | 株式会社東芝 | 半導体装置 |
JP2018198017A (ja) | 2017-05-24 | 2018-12-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及びデータ処理システム |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8254191B2 (en) | 2008-10-30 | 2012-08-28 | Micron Technology, Inc. | Switched interface stacked-die memory architecture |
US20100157644A1 (en) | 2008-12-19 | 2010-06-24 | Unity Semiconductor Corporation | Configurable memory interface to provide serial and parallel access to memories |
US8796863B2 (en) | 2010-02-09 | 2014-08-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and semiconductor packages |
KR101854243B1 (ko) * | 2011-05-16 | 2018-05-03 | 삼성전자주식회사 | 적층 메모리 장치, 및 이를 포함하는 메모리 시스템 |
KR101900423B1 (ko) | 2011-09-19 | 2018-09-21 | 삼성전자주식회사 | 반도체 메모리 장치 |
CN103946980B (zh) | 2011-12-02 | 2017-06-20 | 英特尔公司 | 允许装置互连中的变化的堆栈式存储器 |
KR101903520B1 (ko) * | 2012-01-06 | 2018-10-04 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US8922243B2 (en) | 2012-12-23 | 2014-12-30 | Advanced Micro Devices, Inc. | Die-stacked memory device with reconfigurable logic |
CN104575584B (zh) | 2013-10-23 | 2018-11-30 | 钰创科技股份有限公司 | 具有嵌入式内存的系统级封装内存模块 |
KR102207562B1 (ko) * | 2014-03-10 | 2021-01-27 | 에스케이하이닉스 주식회사 | 다양한 경로로 신호 입력이 가능한 적층 반도체 장치 및 반도체 시스템 |
KR20170060205A (ko) * | 2015-11-23 | 2017-06-01 | 에스케이하이닉스 주식회사 | 적층형 메모리 장치 및 이를 포함하는 반도체 메모리 시스템 |
JP2017123208A (ja) * | 2016-01-06 | 2017-07-13 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP2017010605A (ja) | 2016-07-08 | 2017-01-12 | インテル・コーポレーション | デバイス相互接続の変化を可能にする積層メモリ |
KR20180006229A (ko) * | 2016-07-08 | 2018-01-17 | 삼성전자주식회사 | 스택 구조의 반도체 메모리 패키지, 메모리 장치 및 반도체 메모리 시스템 |
JP6736441B2 (ja) * | 2016-09-28 | 2020-08-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10365325B2 (en) * | 2017-08-22 | 2019-07-30 | Micron Technology, Inc. | Semiconductor memory device |
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- 2019-04-17 JP JP2019078778A patent/JP7226055B2/ja active Active
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- 2020-04-01 US US16/837,564 patent/US11074947B2/en active Active
- 2020-04-13 KR KR1020200044643A patent/KR102295895B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090161401A1 (en) | 2007-12-24 | 2009-06-25 | Christoph Bilger | Multi-die Memory, Apparatus and Multi-die Memory Stack |
US20100088460A1 (en) | 2008-10-07 | 2010-04-08 | Micron Technology, Inc. | Memory apparatus, systems, and methods |
WO2016042603A1 (ja) | 2014-09-17 | 2016-03-24 | 株式会社東芝 | 半導体装置 |
JP2018198017A (ja) | 2017-05-24 | 2018-12-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及びデータ処理システム |
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KR102295895B1 (ko) | 2021-08-31 |
US20200335143A1 (en) | 2020-10-22 |
KR20200122246A (ko) | 2020-10-27 |
US11074947B2 (en) | 2021-07-27 |
JP2020177720A (ja) | 2020-10-29 |
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