CN106605266A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106605266A
CN106605266A CN201480081668.1A CN201480081668A CN106605266A CN 106605266 A CN106605266 A CN 106605266A CN 201480081668 A CN201480081668 A CN 201480081668A CN 106605266 A CN106605266 A CN 106605266A
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CN
China
Prior art keywords
electrode
semiconductor chip
signal
channel
semiconductor
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Granted
Application number
CN201480081668.1A
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English (en)
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CN106605266B (zh
Inventor
小内俊之
小柳胜
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Kioxia Corp
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Toshiba Corp
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Publication of CN106605266A publication Critical patent/CN106605266A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
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    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
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    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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Abstract

根据本发明的一实施方式，设置有M(M为2以上的整数)个半导体芯片、与N(N为2以上的整数)通道量的贯通电极。将M个半导体芯片依序积层，贯通电极被埋入于所述半导体芯片而将所述半导体芯片在积层方向上电连接，所述贯通电极的连接目标在所述半导体芯片的1个或多个上下层间更替。

Description

半导体装置
技术领域
本实施方式是关于一种半导体装置。
背景技术
为谋求半导体装置的省空间化、高性能化及大容量化，存在将半导体芯片积层的情况。为取得所积层的半导体芯片的电连接，而有时使用被称为TSV(Through SiliconVia，硅穿孔)的贯通电极。
在使用此种TSV的半导体装置中，为实现多通道化而有时将进行通道切换的逻辑电路设置在各半导体芯片。
先前技术文献
专利文献1：日本专利特开2014-53055号公报
发明内容
[发明所要解决的问题]
一实施方式的目的在于提供一种可谋求省空间化，并且可实现多通道化的半导体装置。
[解决问题的技术手段]
根据一实施方式，设置有M(M为2以上的整数)个半导体芯片、及N(N为2以上的整数)通道量的贯通电极。将M个半导体芯片依序积层。贯通电极被埋入于所述半导体芯片而将所述半导体芯片在积层方向上电连接。所述贯通电极的连接目标在所述半导体芯片的1个或多个上下层间更替。
附图说明
图1是表示第一实施方式的半导体装置的概略构成的方块图。
图2是表示图1的控制器及NAND存储器的构成例的截面图。
图3是表示图2的半导体芯片的功能构成的方块图。
图4(a)是表示图2的半导体芯片的2通道量的贯通电极的连接方法的一例的方块图，图4(b)是表示图2的半导体芯片的2通道量的贯通电极的连接方法的另一例的方块图。
图5是表示图4的2通道量的贯通电极的连接配线例的截面图。
图6是表示图5的2通道量的贯通电极的连接配线例的立体图。
图7是表示应用在第二实施方式的半导体装置的4通道量的贯通电极的连接方法的方块图。
图8是表示图7的4通道量的贯通电极的连接配线例的截面图。
图9是表示芯片启动信号相对于图8的4通道量的信号的分配例的图。
图10(a)是表示图8的4通道量的贯通电极的连接配线例的俯视图，图10(b)～图10(e)是将图10(a)的连接配线按每一配线层分解而表示的俯视图。
具体实施方式
以下，参照随附图式对实施方式的半导体装置详细地进行说明。另外，并非通过这些实施方式而限定本发明。
(第一实施方式)
图1是表示第一实施方式的半导体装置的概略构成的方块图。另外，在以下的实施方式中，作为半导体装置而行举非易失性半导体装置。作为非易失性半导体装置而行举NAND(与非)存储器。
图1中，在非易失性半导体装置设置有NAND存储器3及控制器2。NAND存储器3连接在控制器2。控制器2经由主机IF(Inter Face，接口)而连接在主机1。NAND存储器3可存储由主机1处理的数据1。NAND存储器3例如可搭载在SSD(Solid-State Drive，固态硬盘)，也可搭载在SD卡(Secure Digital Memory Card，安全数码存储卡)，还可搭载在USB(UniversalSerial BUS，通用串行总线)存储器。控制器2可驱动控制NAND存储器3。另外，作为NAND存储器3的驱动控制，可行举例如NAND存储器3的读写控制、区块选择、错误校正、耗损平均等。主机1可为个人电脑，也可为数码相机等电子设备，还可为智能电话等移动终端。
在NAND存储器3设置有依序积层的M(M为2以上的整数)个半导体芯片Cp0～CpM－1。在半导体芯片Cp0～CpM－1分别埋入有将半导体芯片Cp0～CpM－1在积层方向上电连接的贯通电极V0～VM－1。在各半导体芯片Cp0～CpM－1可设置N(N为2以上的整数)通道量的贯通电极V0～VM－1。贯通电极V0～VM－1能以使连接目标在半导体芯片Cp0～CpM－1的1个或多个上下层间更替的方式连接。例如，贯通电极V0～VM－1可在半导体芯片Cp0～CpM－1的上下层间连接为龙卷风状。
此外，在NAND存储器3设置有在与控制器2之间传输信号的接口部3A。接口部3A可针对每一半导体芯片Cp0～CpM－1而设置。接口部3A可处理N(N为2以上的整数)通道量的信号SH0～SHN－1。此处，接口部3A可相对于半导体芯片Cp0～CpM－1的各者，将N通道量的信号SH0～SHN－1中的仅1通道量的信号分别经由贯通电极V0～VM－1而与内部交换。此时，在各半导体芯片Cp0～CpM－1中，可将交换1通道量的信号的贯通电极V0～VM－1固定为N通道量的贯通电极V0～VM－1中的任一个。在各半导体芯片Cp0～CpM－1中，该固定的贯通电极V0～VM－1可选择水平面的位置相等的贯通电极V0～VM－1。
N通道量的信号SH0～SHN－1可使用例如地址闩锁启动信号ALE、指令闩锁启动信号CLE、读出启动信号/RE(/表示低活动率信号)、RE、写入启动信号/WE、数据信号DQ、数据选通信号DQS、/DQS、芯片启动信号/CE、写入保护信号/WP、就绪/忙碌信号RB、及芯片地址CADD。控制器2可使用这些信号而控制NAND存储器3。
另一方面，主机IF根据应用NAND存储器3的应用系统而变更。在NAND存储器3应用在SSD(Solid-State Drive)的情况下，使用SAS(Serial Attached SCSI，串行连接的SCSI)、SATA(串行ATA)、及PCIe(Programmable Communications Interface，可编程通讯接口)，在NAND存储器3应用在USB(Universal Serial Bus)存储器等的情况下，使用USB，在NAND存储器3应用在eMMC(embedded Multi-Media Card，嵌入式多媒体卡)的情况下，使用eMMC规格的接口，在NAND存储器3应用在SD卡的情况下，使用SD存储器规格的接口。
在控制器2设置有通道控制部2A。通道控制部2A控制NAND存储器3的通道数。此处，通道控制部2A可通过将同一信号输入至N通道量的贯通电极V0～VM－1中的2个以上的贯通电极V0～VM－1而控制通道数。此时，通道控制部2A在使NAND存储器3进行K(K为M以下的正整数)通道动作的情况下，可将N个通道分成K组，对同一组输入同一信号，且对不同组输入不同的信号。
控制器2接收从主机1经由主机IF而输出的请求信号，且根据请求信号而产生芯片启动信号/CE、指令闩锁启动信号CLE、地址闩锁启动信号ALE、写入启动信号/WE、读出启动信号/RE及写入保护信号/WP等。
此外，控制器2在根据从主机1接收到的请求信号而对NAND存储器3写入数据的情况下，经由1个以上且N个以下的通道而对NAND存储器3供给数据。
此外，控制器2在作为相对于从主机1接收到的请求信号的对主机1的回应而对NAND存储器3进行数据读出的情况下，经由1个以上且N个以下的通道从NAND存储器3接收数据。
此处，相对于半导体芯片Cp0～CpM－1的各者，使N通道量的信号SH0～SHN－1中仅1通道量的信号分别经由贯通电极V0～VM－1而与内部进行交换，由此，各半导体芯片Cp0～CpM－1无需根据所指定的通道而切换贯通电极V0～VM－1。因此，无需在各半导体芯片Cp0～CpM－1设置进行通道切换的逻辑电路，从而可谋求省空间化。
此外，以使连接目标在半导体芯片Cp0～CpM－1的上下层间更替的方式连接贯通电极V0～VM－1，由此即便在将交换1通道量的信号的贯通电极V0～VM－1在各半导体芯片Cp0～CpM－1中固定为水平面的位置相等的贯通电极V0～VM－1的情况下，也可不针对每一半导体芯片Cp0～CpM－1而变更布局即可谋求NAND存储器3的多通道化。另外，贯通电极V0～VM－1也可无需在半导体芯片Cp0～CpM－1的所有上下层间更替连接目标，而在一部分上下层间更替连接目标。例如，于在通道传输共通的信号的情况下，未必一定要更替连接目标，也可将贯通电极V0～VM－1在上下层间连接成直线。
图2是表示图1的控制器及NAND存储器的构成例的截面图。另外，在以下的说明中，以半导体芯片Cp0～CpM－1对应在2通道的情况为例。此外，在图2中，表示M为8的情况。
在图2中，半导体芯片Cp0～Cp7依序积层，且安装在支撑衬底12上。此处，在各半导体芯片Cp0～Cp7埋入有2通道量的贯通电极VA～VB。在各半导体芯片Cp0～Cp7，贯通电极VA以水平面的位置一致的方式配置，且贯通电极VB以水平面的位置一致的方式配置。此外，在各半导体芯片Cp0～Cp7，贯通电极VA、VB可邻接配置。贯通电极VA、VB以使连接目标在半导体芯片Cp0～Cp7的上下层间更替的方式连接。而且，贯通电极VA、VB经由焊料球19A、19B而在半导体芯片Cp0～Cp7间连接。此外，半导体芯片Cp0～C7经由接着层15而在上下层间连接。
在支撑衬底12的背面安装有控制器芯片Ce1。此处，在支撑衬底12形成有配线23A、23B。而且，控制器芯片Ce1经由焊料球18A、18B而连接在配线23A、23B。此外，最下层的半导体芯片Cp0的贯通电极VA、VB连接在配线23A、23B，由此控制器芯片Ce1与半导体芯片Cp0～Cp7电连接。支撑衬底12经由焊料球17而连接在安装衬底11。在安装衬底11的背面，设置有将安装衬底11连接在母衬底的焊料球16。
控制器芯片Ce1利用密封树脂21而密封在安装衬底11上。半导体芯片Cp0～Cp7利用密封树脂22而密封在支撑衬底12上。密封树脂21、22的外周利用密封树脂20密封，并且密封树脂22的上部利用金属板13密封。
图3是表示图2的半导体芯片的功能构成的方块图。另外，在图3中，以半导体芯片Cp0为例，但对于半导体芯片Cp1～CpM－1也相同。
在图3中，半导体芯片Cp0包含逻辑控制部49、存储器控制部50、存储器单元阵列41、行地址缓冲器43、行解码器42、传感放大器44、数据暂存器45、列解码器46、列地址缓冲器47、电压产生电路56、输入输出(I/O)控制部48、指令暂存器53、地址暂存器52、状态暂存器51、CSID(character set identifier，字集识别符)暂存器54、就绪/忙碌(R/B)电路55及逻辑电路57。
芯片启动信号/CE、指令闩锁启动信号CLE、地址闩锁启动信号ALE、写入启动信号/WE、读出启动信号RE、/RE、写入保护信号/WP、数据选通信号DQS、/DQS及芯片地址CADD从控制器2供给至逻辑控制部49。指令、地址及数据从控制器2经由信号线DQ0～DQ7而供给至I/O控制部48。
逻辑控制部49根据输入信号而控制存储器控制部50及I/O控制部48。指令暂存器53保持从I/O控制部48输出的指令。地址暂存器52保持从I/O控制部48输出的地址。
存储器控制部50根据保持在指令暂存器53中的指令而控制行解码器42、传感放大器44、数据暂存器45、列解码器46、电压产生电路56及R/B电路55，从而控制数据的写入、读出及删除等。
R/B电路55根据存储器控制部50的输出信号而输出就绪/忙碌信号RB。电压产生电路56根据存储器控制部50的指示而产生写入电压、读出电压及删除电压等，且将这些电压供给至存储器单元阵列41、行解码器42、及传感放大器44。
存储器单元阵列41包含多个NAND串。各NAND串是由第一、第二选择电晶体与多个存储器单元串联连接而构成。在存储器单元设置有电荷储存层及控制栅极电极。第一选择电晶体连接在位线，第二选择电晶体连接在源极线。第一、第二选择电晶体的栅极电极连接在第一、第二选择线，各存储器单元的控制栅极电极分别连接在字线。此外，位线的各者连接在传感放大器44。
行地址缓冲器43、列地址缓冲器47分别保持被保持在地址暂存器52中的行地址及列地址。行解码器42对保持在行地址缓冲器43中的行地址进行解码，且选择存储器单元阵列41的第一、第二选择线及字线。列解码器46对保持在列地址缓冲器47中的列地址进行解码，且选择存储器单元阵列41的位线。
数据暂存器45在数据的写入时，将从I/O控制部48供给的数据供给至传感放大器44。此外，在数据的读出时，保持通过传感放大器44从选择位线检测出的数据并供给至I/O控制部48。
传感放大器44在数据的写入时，将保持在数据暂存器45中的数据写入至所选择的存储器单元中。此外，在数据的读出时，经由位线而从所选择的存储器单元读出数据。
状态暂存器51保持从存储器控制部50输出的数据的写入、读出及删除例如是否正常结束等的状态数据。保持在状态暂存器51中的状态数据经由I/O控制部48及控制器2而供给至主机1。
CSID暂存器54保持半导体芯片Cp0识别从身芯片的芯片识别信息。保持在CSID暂存器54中的芯片识别信息被供给至存储器控制部50及逻辑电路57。
逻辑电路57根据芯片地址CADD及芯片识别信息而产生内部启动信号enb。由逻辑电路57产生的内部启动信号enb被供给至I/O控制部48及逻辑控制部49。逻辑电路57在芯片地址CADD与芯片识别信息一致时，可使内部启动信号enb有效化。
图4(a)是表示图2的半导体芯片的2通道量的贯通电极的连接方法的一例的方块图，图4(b)是表示图2的半导体芯片的2通道量的贯通电极的连接方法的另一例的方块图。另外，在图4(a)及图4(b)的例中，仅表示半导体芯片Cp0～Cp2。
在图4(a)及图4(b)中，在半导体芯片Cp0设置有2通道量的贯通电极VA0、VB0。在半导体芯片Cp1设置有2通道量的贯通电极VA1、VB1。在半导体芯片Cp2设置有2通道量的贯通电极VA2、VB2。在贯通电极VA0上配置有贯通电极VA1，在贯通电极VA1上配置有贯通电极VA2。在贯通电极VB0上配置有贯通电极VB1，在贯通电极VB1上配置有贯通电极VB2。此处，贯通电极VA0～VA2、VB0～VB2以使连接目标在半导体芯片Cp0～Cp2的上下层间更替的方式连接。即，贯通电极VA0与贯通电极VB1电连接，贯通电极VB1与贯通电极VA2电连接。此外，贯通电极VB0与贯通电极VA1电连接，贯通电极VA1与贯通电极VB2电连接。
此外，如图4(a)所示，在半导体芯片Cp0～Cp2分别设置有AND电路N0～N2。AND电路N0～N2的第一输入端子分别连接在贯通电极VB0～VB2。对AND电路N0～N2的第二输入端子分别输入内部启动信号enb0～enb2。在半导体芯片Cp0下配置有控制器芯片Ce1。在控制器芯片Ce1设置有控制器2。在控制器2设置有将2通道量的信号SH0、SH1输入至半导体芯片Cp0～Cp2的输入缓冲器B0、B1。而且，控制器2经由输入缓冲器B0而输出信号SH0，并且经由输入缓冲器B1而输出信号SH1。此外，从控制器2将指定半导体芯片Cp0～Cp2的芯片地址CADD输入至半导体芯片Cp0～Cp2。而且，在各半导体芯片Cp0～Cp2中，将从控制器2输入的芯片地址CADD、与各半导体芯片Cp0～Cp2所保持的芯片识别信息进行比较。而且，在芯片地址CADD与芯片识别信息一致的半导体芯片Cp0～Cp2中，使内部启动信号enb0～enb2有效化，且将信号SH0、SH1分别经由AND电路N0～N2而撷取至半导体芯片Cp0～Cp2的内部。
由此，控制器2可对半导体芯片Cp0、Cp2分配通道Ch0，并且对半导体芯片Cp1分配通道Ch1，从而可实现NAND存储器3的2通道输入。
此外，如图4(b)所示，在半导体芯片Cp0～Cp2分别设置有AND电路N0'～N2'。AND电路N0'～N2'的第一输入端子分别连接在贯通电极VB0～VB2。对AND电路N0'～N2'的第二输入端子分别输入内部启动信号enb0'～enb2'。此外，在控制器2设置有将2通道量的信号SH0、SH1从半导体芯片Cp0～Cp2输出的输出缓冲器B0'，B1'。而且，控制器2可经由输出缓冲器B0'而接收信号SH0，并且可经由输出缓冲器B1'而接收信号SH1。
此时，从控制器2将指定半导体芯片Cp0～Cp2的芯片地址CADD输入至半导体芯片Cp0～Cp2。而且，在各半导体芯片Cp0～Cp2中，将从控制器2输入的芯片地址CADD与各半导体芯片Cp0～Cp2所保持的芯片识别信息进行比较。而且，在芯片地址CADD与芯片识别信息一致的半导体芯片Cp0～Cp2中，使内部启动信号enb0'～enb2'有效化，且将信号SH0、SH1分别经由AND电路N0'～N2'而从半导体芯片Cp0～Cp2的内部输出。
由此，控制器2可对半导体芯片Cp0、Cp2分配通道Ch0，并且可对半导体芯片Cp1分配通道Ch1，从而可实现NAND存储器3的2通道输出。
图5是表示图4的2通道量的贯通电极的连接配线例的截面图，图6是表示图5的2通道量的贯通电极的连接配线例的立体图。另外，在图5中，表示与图4(a)的构成对应的连接配线例。此外，在图6中，表示半导体芯片Cp0的连接配线例。
在图5及图6中，在半导体芯片Cp0设置有配线H01A、H01B、H02A、H02B。配线H01A、H01B可形成在半导体芯片Cp0的第一层，配线H02A、H02B可形成在半导体芯片Cp0的第二层。在半导体芯片Cp1设置有配线H11A、H11B、H12A、H12B。配线H11A、H11B可形成在半导体芯片Cp1的第一层，配线H12A、H12B可形成在半导体芯片Cp1的第二层。
配线H01A连接在贯通电极VA0，配线H01B连接在贯通电极VB0。配线H01A连接在配线H02B，配线H01B连接在配线H02A。配线H02A可配置在贯通电极VA0上，配线H02B可配置在贯通电极VB0上。
配线H11A连接在贯通电极VA1，配线H11B连接在贯通电极VB1。配线H11A连接在配线H12B，配线H11B连接在配线H12A。配线H12A可配置在贯通电极VA1上，配线H12B可配置在贯通电极VB1上。
配线H02A经由焊料球19A而连接在贯通电极VA1，配线H02B经由焊料球19B而连接在贯通电极VB1。
此处，通过使用2层配线，可不变更贯通电极VA0、VB0、VA1、VB1的位置而将贯通电极VA0连接在贯通电极VB1，且将贯通电极VB0连接在贯通电极VA1。
此外，在控制器2设置有通道控制部2A，在通道控制部2A设置有MOS电晶体T0～T2。MOS电晶体T0的漏极连接在输入缓冲器B0，MOS电晶体T1、T2的漏极连接在输入缓冲器B1。对MOS电晶体T0、T1的源极输入信号SH0，MOS电晶体T2的源极被输入信号SH1。对MOS电晶体T0～T2的栅极分别输入控制信号φ0～φ2。
而且，控制器2在使NAND存储器3进行2通道动作的情况下，可将控制信号φ0、φ2设定为高电平，且将控制信号φ1设定为低电平。由此，控制器2可将信号SH0供给至半导体芯片Cp0，并且可将信号SH1供给至半导体芯片Cp1，从而可使NAND存储器3进行2通道动作。
另一方面，控制器2在使NAND存储器3进行1通道动作的情况下，可将控制信号φ0、φ1设定为高电平，且将控制信号φ2设定为低电平。由此，控制器2可将信号SH0供给至半导体芯片Cp0、Cp1，从而可使NAND存储器3进行1通道动作。
(第二实施方式)
图7是表示应用在第二实施方式的半导体装置的4通道量的贯通电极的连接方法的方块图。另外，在图7的例中表示8层量的半导体芯片Cp10～Cp18。此外，在图7的例中，表示使输入至半导体芯片Cp10～Cp18的信号4通道化的构成，但也可同样应用在使从半导体芯片Cp10～Cp18输出的信号4通道化的构成。
在图7中，在半导体芯片Cp10设置有4通道量的贯通电极VA10～VD10。在半导体芯片Cp11设置有4通道量的贯通电极VA11～VD11。在半导体芯片Cp12设置有4通道量的贯通电极VA12～VD12。在半导体芯片Cp13设置有4通道量的贯通电极VA13～VD13。在半导体芯片Cp14设置有4通道量的贯通电极VA14～VD14。在半导体芯片Cp15设置有4通道量的贯通电极VA15～VD15。在半导体芯片Cp16设置有4通道量的贯通电极VA16～VD16。在半导体芯片Cp17设置有4通道量的贯通电极VA17～VD17。
贯通电极VA10～VA17依序积层，贯通电极VB10～VB17依序积层，贯通电极VC10～VC17依序积层，贯通电极VD10～VD17依序积层。此处，贯通电极VA10～VA17、VB10～VB17、VC10～VC17、VD10～VD17以使连接目标在半导体芯片Cp10～Cp18的上下层间依序更替的方式连接。例如，在半导体芯片Cp10、Cp11间，贯通电极VD10电连接在贯通电极VA11，贯通电极VA10电连接在贯通电极VB11。此外，贯通电极VB10电连接在贯通电极VC11，贯通电极VC10电连接在贯通电极VD11。
此外，在半导体芯片Cp10～Cp18分别设置有AND电路N10～N17。AND电路N10～N17的第一输入端子分别连接在贯通电极VC10～VC17。对AND电路N10～N17的第二输入端子分别输入内部启动信号enb0～enb7。在半导体芯片Cp10下配置有控制器芯片Ce2。在控制器芯片Ce2设置有控制器2'。在控制器2'设置有将4通道量的信号SH0～SH3输入至半导体芯片Cp10～Cp18的输入缓冲器B10～B13。而且，控制器2'经由输入缓冲器B10而输出信号SH0，经由输入缓冲器B11而输出信号SH1，经由输入缓冲器B12而输出信号SH2，且经由输入缓冲器B13而输出信号SH3。此外，从控制器2'将指定半导体芯片Cp10～Cp18的芯片地址CADD输入至半导体芯片Cp10～Cp18。而且，在各半导体芯片Cp10～Cp18中，将从控制器2'输入的芯片地址CADD、与各半导体芯片Cp10～Cp18所保持的芯片识别信息进行比较。而且，在芯片地址CADD与芯片识别信息一致的半导体芯片Cp10～Cp18中，使内部启动信号enb0～enb7有效化，且将信号SH0～SH4分别经由AND电路N10～N17而撷取至半导体芯片Cp10～Cp18的内部。
由此，控制器2'可对半导体芯片Cp13、Cp17分配通道Ch0，对半导体芯片Cp12、Cp16分配通道Ch1，对半导体芯片Cp11、Cp15分配通道Ch2，且对半导体芯片Cp10、Cp14分配通道Ch3，从而可实现NAND存储器3的4通道输入。
图8是表示图7的4通道量的贯通电极的连接配线例的截面图。另外，在图8中，表示半导体芯片Cp10、Cp11的连接配线例。此外，在图8中省略图7的输入缓冲器B10～B13。
在图8中，在半导体芯片Cp10设置有配线01A～01D、02A～02D。配线01A～01D可形成在半导体芯片Cp10的第一层，配线02A～02D可形成在半导体芯片Cp10的第二层。在半导体芯片Cp11设置有配线11A～11D、12A～12B。配线11A～11D可形成在半导体芯片Cp11的第一层，配线12A～12B可形成在半导体芯片Cp11的第二层。
配线01A连接在贯通电极VA10，配线01B连接在贯通电极VB10，配线01C连接在贯通电极VC10，配线01D连接在贯通电极VD10。配线01A连接在配线02B，配线01B连接在配线02C，配线01C连接在配线02D，配线01D连接在配线02A。配线02A可配置在贯通电极VA10上，配线02B可配置在贯通电极VB10上，配线02C可配置在贯通电极VC10上，配线02D可配置在贯通电极VD10上。
配线11A连接在贯通电极VA11，配线11B连接在贯通电极VB11，配线11C连接在贯通电极VC11，配线11D连接在贯通电极VD11。配线11A连接在配线12B，配线11B连接在配线12C，配线11C连接在配线12D，配线11D连接在配线12A。配线12A可配置在贯通电极VA11上，配线12B可配置在贯通电极VB11上，配线12C可配置在贯通电极VC11上，配线12D可配置在贯通电极VD11上。
配线12A经由焊料球52A而连接在贯通电极VA10，配线12B经由焊料球52B而连接在贯通电极VB10，配线12C经由焊料球52C而连接在贯通电极VC10，配线12D经由焊料球52D而连接在贯通电极VD10。配线01A～01D分别经由焊料球51A～51D而连接在控制器芯片Ce2。
此处，通过使用2层配线，可不变更贯通电极VA10～VD10、VA11～VD11的位置而将贯通电极VA10连接在贯通电极VD11，将贯通电极VB10连接在贯通电极VA11，将贯通电极VC10连接在贯通电极VB11，且将贯通电极VD10连接在贯通电极VC11。
此外，在控制器2'设置有通道控制部2A'，在通道控制部2A'设置有MOS电晶体T11～T17。MOS电晶体T10、T11的漏极连接在焊料球51C，MOS电晶体T12、T13的漏极连接在焊料球51B，MOS电晶体T14的漏极连接在焊料球51A，MOS电晶体T15～T16的漏极连接在焊料球51D。对MOS电晶体T11、T13、T14、T17的源极输入信号SH0，MOS电晶体T12的源极可输入信号SH1，MOS电晶体T10、T16的源极可输入信号SH2，MOS电晶体T15的源极可输入信号SH3。对MOS电晶体T10～T17的栅极分别输入控制信号φ0～φ7。
而且，控制器2'在使NAND存储器3进行4通道动作的情况下，可将控制信号φ0、φ2、φ4、φ5设定为高电平，且将控制信号φ1、φ3、φ6、φ7设定为低电平。由此，控制器2'可将信号SH0供给至半导体芯片Cp13、Cp17，将信号SH1供给至半导体芯片Cp12、Cp16，将信号SH2供给至半导体芯片Cp11、Cp15，且将信号SH3供给至半导体芯片Cp10、Cp14，从而可使NAND存储器3进行4通道动作。
控制器2'在使NAND存储器3进行3通道动作的情况下，例如可将控制信号φ0、φ2、φ4、φ7设定为高电平，且将控制信号φ1、φ3、φ5、φ6设定为低电平。由此，控制器2'可将信号SH0供给至半导体芯片Cp13、Cp17，将信号SH1供给至半导体芯片Cp12、Cp16，将信号SH2供给至半导体芯片Cp11、Cp15，且将信号SH3供给至半导体芯片Cp10、Cp14，从而可使NAND存储器3进行3通道动作。
控制器2'在使NAND存储器3进行2通道动作的情况，例如可将控制信号φ0、φ3、φ4、φ6设定为高电平，且将控制信号φ1、φ2、φ5、φ7设定为低电平。由此，控制器2'可将信号SH0供给至半导体芯片Cp12、Cp13、Cp16、Cp17，且可将信号SH2供给至半导体芯片Cp10、Cp11、Cp14、Cp15，从而可使NAND存储器3进行2通道动作。
控制器2'在使NAND存储器3进行1通道动作的情况，可将控制信号φ1、φ3、φ4、φ7设定为高电平，且将控制信号φ0、φ2、φ5、φ6设定为低电平。由此，控制器2'可将信号SH0供给至半导体芯片Cp10～Cp18，从而可使NAND存储器3进行1通道动作。
图9是表示芯片启动信号相对于图8的4通道量的信号的分配例的图。
在图9中，控制器2'可对N通道量的信号控制芯片启动信号的分配数。例如，在1通道动作的情况下，可对4通道量的信号SH0～SH3分配共通的芯片启动信号CE0。由此，可减少伴随芯片切换的芯片启动信号的切换次数，从而可使控制简化。或者在1通道动作的情况下，也可对4通道量的信号SH0～SH3分配不同的芯片启动信号CE0～CE3。由此，可使非选择芯片非活化，从而可降低消耗电力。
图10(a)是表示图8的4通道量的贯通电极的连接配线例的俯视图，图10(b)～图10(e)是将图10(a)的连接配线针对每一配线层分解而表示的俯视图。另外，在图10(a)～图10(e)中，表示图8的半导体芯片Cp11的连接配线例。
在图10(a)中，贯通电极VA10～VD10、VA11～VD11以正方形配置。配线11A～11D分别配置在贯通电极VA11～VD11上。在配线11A～11D上，在配线11D、11A～11C的方向分别附加有引出部LA～LD。配线12A～12D分别配置在配线11D、11A～11C上。在配线12A～12D上，在配线12B～12D、12A的方向分别附加有引出部MA～MD。在配线12A～12D上分别配置有焊料球52A～52D。而且，引出部LA～LD分别经由插塞电极PA～PD而分别连接在引出部MA～MD。
由此，可抑制布局面积的增大，并且可将贯通电极VA10连接在贯通电极VD11，将贯通电极VB10连接在贯通电极VA11，将贯通电极VC10连接在贯通电极VB11，且将贯通电极VD10连接在贯通电极VC11。
对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出，并未意图限定发明的范围。这些新颖的实施方式能以其他各种形态实施，且可在不脱离发明的主旨的范围进行各种省略、置换、变更。这些实施方式及其变化包含在发明的范围及主旨中，并且包含在权利要求书中记载的发明及其均等的范围。

Claims (20)

1.一种半导体装置，其特征在于具备：
M(M为2以上的整数)个半导体芯片，依序积层；及
N(N为2以上的整数)通道量的贯通电极，埋入于所述半导体芯片，将所述半导体芯片在积层方向上电连接；且
所述贯通电极的连接目标在所述半导体芯片的1个或多个上下层间更替。
2.根据权利要求1所述的半导体装置，其特征在于：所述M个半导体芯片包含2个第一半导体芯片及1个第二半导体芯片，
一所述第一半导体芯片积层在所述第二半导体芯片上，
所述第二半导体芯片积层在另一所述第一半导体芯片上，
所述贯通电极包含第一及第二贯通电极，
设置在另一所述第一半导体芯片上的第一贯通电极、与设置在所述第二半导体芯片上的第二贯通电极连接，
设置在另一所述第一半导体芯片上的第二贯通电极、与设置在所述第二半导体芯片上的第一贯通电极连接，
设置在所述第二半导体芯片上的第一贯通电极、与设置在一所述第一半导体芯片上的第二贯通电极连接，
设置在所述第二半导体芯片上的第二贯通电极、与设置在一所述第一半导体芯片上的第一贯通电极连接。
3.根据权利要求21所述的半导体装置，其特征在于具备配线层，该配线层是针对每一所述半导体芯片而设置，且在所述半导体芯片的上下层间更替所述贯通电极的连接目标。
4.根据权利要求2所述的半导体装置，其特征在于：所述半导体芯片包含接口部，该接口部可将所述N通道量的信号中仅1通道量的信号经由所述贯通电极而与内部交换。
5.根据权利要求4所述的半导体装置，其特征在于：在各半导体芯片中，将交换1通道量的信号的贯通电极固定为所述N通道量的贯通电极中的任一个。
6.根据权利要求4所述的半导体装置，其特征在于：所述接口部包含AND电路，该AND电路是根据内部启动信号而将所述1通道量的信号撷取至内部。
7.根据权利要求6所述的半导体装置，其特征在于：所述半导体芯片包含逻辑电路，该逻辑电路是根据芯片地址与芯片识别信息而产生所述内部启动信号。
8.根据权利要求2所述的半导体装置，其特征在于具备控制所述半导体芯片的控制器，且
所述控制器包含通道控制部，其控制以所述M个半导体芯片实现的通道数。
9.根据权利要求8所述的半导体装置，其特征在于：所述通道控制部通过将同一信号输入至所述N通道量的贯通电极中的2个以上的贯通电极而控制所述通道数。
10.根据权利要求9所述的半导体装置，其特征在于：所述通道控制部在使所述M个半导体芯片进行K(K为M以下的正整数)通道动作的情况下，将所述N通道分成K个组，对同一组输入同一信号，且对不同组输入不同的信号。
11.根据权利要求8所述的半导体装置，其特征在于：所述控制器对所述N通道量的信号控制芯片启动信号的分配数。
12.根据权利要求8所述的半导体装置，其特征在于：所述控制器配置在最上层的半导体芯片上或最下层的半导体芯片下。
13.根据权利要求2所述的半导体装置，其特征在于：所述半导体芯片为NAND存储器。
14.根据权利要求2所述的半导体装置，其特征在于：所述半导体芯片包含第一半导体芯片与第二半导体芯片，且
所述第一半导体芯片包含第一贯通电极与第二贯通电极，
所述第二半导体芯片包含第三贯通电极与第四贯通电极，
所述第三贯通电极配置在所述第一贯通电极上，所述第四贯通电极配置在所述第二贯通电极上，
对所述第一贯通电极及所述第四贯通电极分配第一通道，
对所述第二贯通电极及所述第三贯通电极分配第二通道。
15.根据权利要求14所述的半导体装置，其特征在于：所述第一半导体芯片包含第一接口部，其可仅将第一通道的信号经由所述第一贯通电极而与内部交换，且
所述第二半导体芯片包含第二接口部，其可仅将第二通道的信号经由所述第三贯通电极而与内部交换。
16.根据权利要求15所述的半导体装置，其特征在于具备控制器，该控制器是控制所述第一半导体芯片及所述第二半导体芯片，且
所述控制器：
在使所述第一半导体芯片及所述第二半导体芯片进行2通道动作的情况下，对所述第一通道及所述第二通道输入不同的信号，
在使所述第一半导体芯片及所述第二半导体芯片进行1通道动作的情况下，对所述第一通道及所述第二通道输入共通的信号。
17.根据权利要求2所述的半导体装置，其特征在于：所述半导体芯片包含第一半导体芯片与第二半导体芯片，
所述第一半导体芯片包含第一贯通电极、第二贯通电极、第三贯通电极及第四贯通电极，
所述第二半导体芯片包含第五贯通电极、第六贯通电极、第七贯通电极及第八贯通电极，
所述第五贯通电极配置在所述第一贯通电极上，所述第六贯通电极配置在所述第二贯通电极上，所述第七贯通电极配置在所述第三贯通电极上，所述第八贯通电极配置在所述第四贯通电极上，
对所述第一贯通电极及所述第六贯通电极分配第一通道，
对所述第二贯通电极及所述第七贯通电极分配第二通道，
对所述第三贯通电极及所述第八贯通电极分配第三通道，
对所述第四贯通电极及所述第五贯通电极分配第四通道。
18.根据权利要求17所述的半导体装置，其特征在于：所述第一半导体芯片包含第一接口部，其可仅将第一通道的信号经由所述第一贯通电极而与内部交换，且
所述第二半导体芯片包含第二接口部，其可仅将第二通道的信号经由所述第五贯通电极而与内部交换。
19.根据权利要求18所述的半导体装置，其特征在于具备控制器，该控制器是控制所述第一半导体芯片及所述第二半导体芯片，且
所述控制器：
在使所述第一半导体芯片及所述第二半导体芯片进行4通道动作的情况下，对所述第一通道、所述第二通道、所述第三通道及所述第四通道输入不同的信号，
在使所述第一半导体芯片及所述第二半导体芯片进行1通道动作的情况下，对所述第一通道、所述第二通道、所述第三通道及所述第四通道输入共通的信号。
20.根据权利要求17所述的半导体装置，其特征在于：所述第一贯通电极、所述第二贯通电极、所述第三贯通电极及所述第四贯通电极以正方形配置，
所述第五贯通电极、所述第六贯通电极、所述第七贯通电极及所述第八贯通电极以正方形配置。
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