TWI624012B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI624012B
TWI624012B TW105125563A TW105125563A TWI624012B TW I624012 B TWI624012 B TW I624012B TW 105125563 A TW105125563 A TW 105125563A TW 105125563 A TW105125563 A TW 105125563A TW I624012 B TWI624012 B TW I624012B
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TW
Taiwan
Prior art keywords
substrate
bump
routing
semiconductor device
semiconductor
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TW105125563A
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English (en)
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TW201719827A (zh
Inventor
西澤弘一郎
日坂隆行
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三菱電機股份有限公司
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Publication of TW201719827A publication Critical patent/TW201719827A/zh
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Publication of TWI624012B publication Critical patent/TWI624012B/zh

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Abstract

保持中空部的氣密性且提昇良率及耐久性。半導體裝置1具有裝置基板2、半導體電路3、封裝框7、蓋基板8、路由部10、電極11、12、13、及凸塊部14等。裝置基板2及蓋基板8之間，設有以氣密狀態收容半導體電路3的中空部9。凸塊部14連結全部的路由部10及蓋基板8。藉此，使用凸塊部14A能補強路由部10。

Description

半導體裝置
本發明係有關於半導體裝置，特別是有關於具有中空部的半導體裝置。
通常，半導體晶片，由於空氣中的水分產生電極的腐蝕等而有動作不良的情形，所以有以具有氣密結構的方式而被封裝化的情形。又，於高頻操作的半導體晶片，為了防止受外部電波的影響而導致的動作不穩定化及來自半導體自身的不必要輻射的問題，而被要求在封裝上具有電磁屏蔽功能。此種晶片的封裝材，一般是在CuW等的基材上做金屬蓋(metal cap)，由於價格高而成為成本上昇的因素。對此，近年來將半導體晶片利用晶片級封裝化(CSP結構化)，以削減封裝化成本的方法不斷地被開發。像這樣，作為已封裝化的中空裝置的代表結構，例如專利文件1、2、3係廣為周知。
專利文件1所記載者，是關於將是高頻裝置的基本電晶體之一的HEMT結構封裝化的情形。專利文件1中，如第4至6圖所示，在裝置基板的晶片外圍設置封裝框，此外，藉由在封裝框上貼附金屬蓋而將半導體電路封裝於中空部以封裝化。又，提出了藉由使蓋及封裝框具有導電性而實現電磁屏蔽功能的結構。電磁屏蔽是用於高頻半導體的功能，目的是抑制 從半導體電路產生的電磁波輻射對周邊裝置的影響、以及周邊裝置的電磁波對半導體電路的影響。
專利文件2、3沒有使用封裝框，藉由在蓋形成凹陷以在裝置基板與蓋之間設置中空部。又，專利文件2中，在蓋的凹陷形成有導電性膜，藉此實現電磁屏蔽功能。又，專利文件3，在蓋的反對面形成散熱電極。
[先前技術文件]
[專利文件]
[專利文件1]日本特開2005-57136號公報
[專利文件2]日本特開2012-33615號公報
[專利文件3]日本特開2012-244059號公報
[專利文件4]國際公開第2007/049376號
[專利文件5]國際公開第2010/013728號
然而上述習知技術，由於以下的理由而難以確保封裝內的氣密性。首先，專利文件1至3的習知技術，有從路由(via)部容易產生氣密破壞的共同問題。具體而言，基板上形成的路由孔(via hole)的側壁上，存在蝕刻時的產生物(聚積物)等。因此，即使在側壁上以緊密狀態形成導電金屬，也容易減低其密著性。而且，路由孔內的導電金屬與基板之間存在熱膨脹率及線膨脹率的差異。因此，對半導體裝置在晶圓製程及晶片動作時加上熱履歷時，原本緊密性低的路由孔內的導電金屬 會有剝離的情形，而施加應力至接合於該導電金屬的電極墊則會有電極墊剝離的情形；結果，產生中空部的氣密性破壞的問題。又，作為上述的熱履歷，例舉有例如銲接黏晶(solder die bond)構裝、烘烤、藥品處理、電晶體動作等所產生之50~300℃程度的溫度變化。
又，專利文件3所記載的習知技術，裝置基板與蓋基板之間，併存有由導電金屬所形成的凸塊(bump)結構、以及蓋自身被接合至裝置基板的接合部。此等部位存在線膨脹率的差異。因此，加上熱履歷時，應力施加至裝置基板與蓋基板的接合部，會在蓋基板、裝置基板等產生龜裂，容易發生氣密破壞的問題。
本發明是為解決如上述的問題而完成，目的為提供能夠穩定地保持中空部的氣密性、且可提昇良率及耐久性的半導體裝置。
本發明的半導體裝置，包括：裝置基板，具有表面及背面；半導體電路，設置於裝置基板的表面側；封裝框，接合於裝置基板的表面、且包圍半導體電路；蓋基板，由具有表面及背面的基板所形成，背面以覆蓋半導體電路的狀態而與封裝框的全周圍接合，同時在蓋基板與裝置基板之間形成以氣密狀態收容半導體電路的中空部；複數路由部，由導電性材料所形成以將半導體電路連接至外部，且貫通裝置基板的表面和背面同時連接半導體電路；以及，複數凸塊部，在中空部的內部分別設置於全部的路由部上，且連結該路由部與蓋基板。
依據本發明，在全部的路由部上設置凸塊部，能藉由該凸塊部連結路由部及蓋基板。藉此，利用蓋基板所支持的凸塊部將路由部補強，能抑制路由部的變形、剝離等。結果，能提高裝置基板及蓋基板的接合可靠度、且能穩定保持中空部的氣密性。因此，能提昇半導體裝置的良率及耐久性。
1、1'、21、31、41、51、61‧‧‧半導體裝置
61、71、81、91、101、111‧‧‧半導體裝置
2‧‧‧裝置基板(基板)
2A、8A、94A‧‧‧表面(對向面)
2B、8B、94B‧‧‧背面
3‧‧‧半導體電路
3A‧‧‧源極電極
3B‧‧‧汲極電極
3C‧‧‧閘極電極
3D‧‧‧半導體動作層
4‧‧‧接地電極墊(電極墊)
5‧‧‧輸入電極墊(電極墊)
6‧‧‧輸出電極墊(電極墊)
7‧‧‧封裝框
8‧‧‧蓋基板(基板)
9‧‧‧中空部
10、75、102、102'‧‧‧路由部
10A、102C、104、104'、113‧‧‧空洞
11、72、95‧‧‧接地電極
12、73、96‧‧‧輸入電極
13、74、97‧‧‧輸出電極
14、14A、14B、14C、14D、14E、14F‧‧‧凸塊部
14G、103、103'、103A、103B、112‧‧‧凸塊部
14a、14a'‧‧‧凸塊本體
15、17‧‧‧接合墊
16‧‧‧接合墊(電極墊)
18、19‧‧‧晶圓
20‧‧‧標記
22、32、42、52、62、82‧‧‧導電膜
23‧‧‧絕緣蓋
33、43、63‧‧‧絕緣膜
76‧‧‧基材
77‧‧‧整合基板
78‧‧‧銲線
92、93‧‧‧半導體晶片
94‧‧‧共通基板
102A‧‧‧路由孔
102B‧‧‧充填金屬
112a‧‧‧第1凸塊層
112b‧‧‧第2凸塊層
第1圖是將本發明的實施樣態1的半導體裝置在部分省略的狀態所表示的平面圖。
第2圖是第1圖所示半導體裝置的箭號I-I線剖面圖。
第3圖是第1圖所示半導體裝置的箭號Ⅱ-Ⅱ線剖面圖。
第4圖是表示於本發明的實施樣態1中在裝置基板上形成半導體電路、凸塊部等之步驟的剖面圖。
第5圖是表示在蓋基板形成接合墊之步驟的剖面圖。
第6圖是表示接合裝置基板與蓋基板之步驟的剖面圖。
第7圖是表示接合後將裝置基板與蓋基板薄板化之步驟的剖面圖。
第8圖是表示在裝置基板上形成路由部及裏面側的電極之步驟的剖面圖。
第9圖是表示在晶圓上形成複數裝置基板及該基板側的構成要素之步驟的說明圖。
第10圖是表示在晶圓上形成複數蓋基板及該基板側的構成要素之步驟的說明圖。
第11圖是表示習知技術的半導體裝置之一例的剖面圖。
第12圖是表示第11圖中產生氣密破壞的部位的主要部分的放大圖。
第13圖是表示將本發明實施樣態2的半導體裝置的蓋基板從裝置基板側所見的仰視圖。
第14圖是表示本發明實施樣態2的半導體裝置在第13圖中的箭號I-I線位置割裂的剖面圖。
第15圖是表示本發明實施樣態2的半導體裝置在第13圖中的箭號Ⅱ-Ⅱ線位置割裂的剖面圖。
第16圖是表示將本發明實施樣態3的半導體裝置的蓋基板從裝置基板側所見的仰視圖。
第17圖是表示將本發明實施樣態3的半導體裝置在第16圖中的箭號I-I線位置割裂的剖面圖。
第18圖是表示本發明實施樣態3的半導體裝置在第16圖中的箭號Ⅱ-Ⅱ線位置割裂的剖面圖。
第19圖是本發明實施樣態4的半導體裝置從與第2圖相同的位置所見的剖面圖。
第20圖是本發明實施樣態5的半導體裝置從與第2圖相同的位置所見的剖面圖。
第21圖是本發明實施樣態6的半導體裝置從與第2圖相同的位置所見的剖面圖。
第22圖是本發明實施樣態7的半導體裝置從與第2圖相同的位置所見的剖面圖。
第23圖是本發明實施樣態7的半導體裝置從與第3圖相同 的位置所見的剖面圖。
第24圖是在本發明實施樣態7中將半導體裝置構裝於基材的狀態概要表示的剖面圖。
第25圖是表示習知技術中的半導體裝置的構裝狀態的剖面圖。
第26圖是本發明實施樣態8的半導體裝置從與第2圖相同的位置所見的剖面圖。
第27圖是本發明實施樣態8的半導體裝置從與第3圖相同的位置所見的剖面圖。
第28圖是本發明實施樣態9的半導體裝置從與第2圖相同的位置所見的剖面圖。
第29圖是本發明實施樣態10的半導體裝置從與第2圖相同的位置所見的剖面圖。
第30圖是表示比較本發明實施樣態1至9的路由部的剖面圖30(A)與習知技術的路由部的剖面圖30(B)的說明圖。
第31圖是本發明實施樣態11的半導體裝置從與第2圖相同的位置所見的剖面圖。
第32圖是本發明實施樣態11的半導體裝置從與第3圖相同的位置所見的剖面圖。
第33圖是將第31圖中的凸塊部等放大表示的主要部分放大剖面圖。
第34圖是第33圖中的箭號Ⅲ-Ⅲ線剖面圖。
第35圖是於本發明實施樣態11中表示變化例的凸塊部的橫剖面圖。
第36圖是表示圖案化裝置基板之步驟的剖面圖。
第37圖是表示薄板化裝置基板以形成路由孔之步驟的剖面圖。
第38圖是表示在裝置基板上形成路由部及接地電極之步驟的剖面圖。
第39圖是表示形成凸塊部及封裝框之步驟的剖面圖。
第40圖是表示形成接合墊於蓋基板之步驟的剖面圖。
第41圖是表示接合裝置基板與蓋基板之步驟的剖面圖。
第42圖是表示於本發明實施樣態11中其他變化例的剖面圖。
第43圖是將本發明實施樣態12的半導體裝置的凸塊部等放大表示的主要部分放大剖面圖。
第44圖是主要部分放大剖面圖，係從與第43圖相同位置所見的在形成路由孔時發生過蝕刻的模樣。
以下參照圖式說明本發明的實施樣態。又，於本說明書使用的各圖中，共同的要素則附以相同的符號，且省略重複的說明。又，本發明並非限定於以下的實施樣態，在未跳脫本發明的中心思想的範圍內而可有各式各樣的變化。又，本發明在以下的各實施樣態所示的構成中，包含可組合的構成的每個組合。此外，於本說明書中，具有電性功能的結構物們的「連接」是表示電性的及機械的連接。
實施樣態1
首先，參照第1至12圖以說明本發明實施樣態1。第1圖是 將本發明的實施樣態1的半導體裝置在部分省略的狀態所表示的平面圖。又，第1圖中省略蓋基板8等的圖示。又，第2圖是第1圖所示半導體裝置的箭號I-I線剖面圖，第3圖是第1圖所示半導體裝置的箭號Ⅱ-Ⅱ線剖面圖。如這些圖所示，本發明實施樣態的半導體裝置1，具有裝置基板2、半導體電路3、電極墊4、5、6、封裝框7、蓋基板8、中空部9、路由部10、凸塊部14、接合墊15、16、17等。又，本說明書中，有將裝置基板2與蓋基板8統整表示為「基板2、8」的情形。又，接地電極墊4、輸入電極墊5、輸出電極墊6有表示為「電極墊4、5、6」的情形，接地電極11、輸入電極12及輸出電極13有表示為「電極11、12、13」的情形。
裝置基板2，例如由單結晶的GaAs基板、矽基板等形成平板狀、且具有表面2A及背面2B。半導體電路3，例如由HEMT電晶體(高電子移動率電晶體)等所構成，且設於裝置基板2的表面2A側(半導體動作面)。又，本發明並非限定於HEMT電晶體，例如由其他的場效電晶體、HBT等的雙載子電晶體、積體電路等所構成的半導體電路也適用。又，本發明中，裝置基板2的兩面中將與蓋基板8對向的的對向面標記為表面2A，將面向半導體裝置1的外部的外側的面標記為背面2B。
半導體電路3，具有固定於裝置基板2的表面2A的源極電極3A、汲極電極3B及閘極電極3C。汲極電極3B例如配置於裝置基板2的中央部，源極電極3A分別配置於汲極電極3B的兩側。閘極電極3C在汲極電極3B的兩側，分別設置於汲極電極3B與各源極電極3A之間。
又，接地電極墊4、輸入電極墊5及輸出電極墊6，被固定在裝置基板2的表面2A上。接地電極墊4，例如配置2個，每個接地電極墊4各連接1個源極電極3A。輸入電極墊5連接2個閘極電極3C。輸出電極墊6連接汲極電極3B。又，上述電極3A、3B、3C及電極墊4、5、6，例如由Au等金屬膜所形成。
此種構成的半導體電路3，當輸入訊號從輸入電極墊5輸入至各閘極電極3C時，此輸入訊號經過電晶體放大後，從汲極電極3B輸出至輸出電極6。又，上述半導體電路3的構成是一例，本發明並非限定於此。又，接地電極墊4、輸入電極墊5及輸出電極墊6，構成在該電極墊4、5、6的位置所形成的凸塊部14的一部分。依據此構成，凸塊部14被直接連結於路由部10。一方面，本發明中接地電極墊4、輸入電極墊5及輸出電極墊6，亦可視為與凸塊部14不同之其他的結構物。在此情形下，凸塊部14透過電極墊4、5、6的任一者而間接地連結路由部10。本發明的特徵為將凸塊部14連結於路由部10上，且包含凸塊部14藉由電極墊4~6而連接路由部10的構成、及凸塊部14直接連接路由部10的構成。
封裝框7，例如由包含Au、Ag、Cu、Pt、Pd或這些合金等的導電性材料所構成，且被形成四邊形的框狀。又，封裝框7在將半導體裝置3全週包圍的位置，被接合在裝置基板2的表面2A上，而從表面2A垂直地突出。蓋基板8作為與裝置基板2對向的平板狀的晶片而被形成，以將半導體電路3等覆蓋的狀態，而被接合於封裝框7的全週。藉此，裝置基板2與蓋基板8之間，在成為封裝框7的內側的位置上形成中空部9。中空部9 的內部中，以氣密狀態收容半導體電路3、及包含電極墊4、5、6的凸塊部14。又，本說明書中，將蓋基板8的兩面中與裝置基板2的表面2A對向的對向面標記為表面8A，將面向半導體裝置1的外部的外側的面標記為背面8B。
作為蓋基板8的材料，可使用像是例如半導體基板、玻璃、藍寶石基板等平坦性高的基板。因為，基板的平坦性愈高，接合狀態愈均一，能得到穩定的氣密封裝。又，合意的是，裝置基板2與蓋基板8由相同材料形成、或由相互線膨脹率相近的材料形成。藉此，能夠抑制熱履歷導致的應力。又，在使用環氧樹脂、聚酰亞胺(Polyimide)膜之有機膜等材料的情形中，氣密性有下降的傾向。
路由部10是將半導體電路3連接至外部之物，貫通裝置基板2以露出表面2A和背面2B。路由部10，係在裝置基板2上所形成的路由孔的內部充填金屬材料而形成。又，裝置基板2上設有複數路由部10。各路由部10之中位於裝置基板2的表面2A側的部位，連接電極墊4、5、6的其中之一，此外透過該電極墊而連接半導體電路3。又，各路由部10，被連接至使用金屬材料等導電膜而被設置在裝置基板2的背面2B上的接地電極11、輸入電極12及輸出電極13的其中之一。藉此，接地電極墊4、輸入電極墊5、輸出電極墊6透過各別的路由部10而連接接地電極11、輸入電極12、輸出電極13。又，關於路由部10的空洞10A，將參照第29圖而在後敘述。
一方面，凸塊部14連結各個路由部10及蓋基板8。亦即，全部的路由部10透過互相不同的凸塊部14而連結蓋基板 8。這些凸塊部14，配置於裝置基板2與蓋基板8之間(中空部9的內部)，且被形成該各基板2、8對向而延伸的柱狀。更詳細而言，凸塊部14中包含2種凸塊部14A、14B。凸塊部14A是透過路由部10而沒有被接地的凸塊部，凸塊部14B是透過路由部10而被接地的凸塊部。凸塊部14以平面所視可以是路由孔的內側。
一部分的凸塊部14A，如第2圖所示，由例如導電性材所形成的柱狀的凸塊本體14a、輸入電極墊5、及接合墊16所構成。輸入電極墊5，分別被接合於凸塊本體14a的一端側及路由部10。接合墊16，分別被接合於凸塊本體14a的另一端側及蓋基板8的表面8A。又，其餘的凸塊部14A由凸塊本體14a、輸出電極6及接合墊16所構成。輸出電極墊6被接合於凸塊本體14a的一端側及路由部10。一方面，凸塊部14B，如第3圖所示，由凸塊本體14a、接地電極墊4、及接合墊16所構成。接地電極墊4分別被接合於凸塊本體14a的一端側及路由部10。
凸塊部14是提高路由部10的強度之物。因此，凸塊部14合意的是由硬質的材質形成。具體上，使用例如金屬材料、矽氧化膜等的無機絕緣膜、聚酰亞胺等材料形成凸塊部14，藉此能夠提昇路由部10的強度。又，凸塊部14理想的是使用和封裝框7相同的材料而形成。藉此，能防止封裝框7和凸塊部14的線膨脹率的差異所造成在裝置基板2和蓋基板8發生變形、龜裂等，能夠提昇半導體裝置1的耐久性。又，在使用金屬材料、無機絕緣膜等形成封裝框7的情形，對基板2、8使壔裝框7穩定地密著，能提高中空部9的氣密性。又，關於第2、3 圖所示的接合墊15、16、17將在後敘述。
接著，參照第4至8圖，說明本實施樣態之半導體裝置1相關的製造步驟。此等圖式是從與第2圖相同位置所視的剖面圖。首先，第4圖表示在本發明實施樣態1中，在裝置基板上形成半導體電路、凸塊部等的步驟。於此步驟中，在使用磊晶成長等的手段而在裝置基板2的表面2A側形成半導體動作層(未圖示)之後，使用微影成像、蝕刻、金屬成膜等的手段，以形成包含電晶體結構的半導體電路3。又，藉由在裝置基板2的表面2A側上氣相沈積例如Au等的金屬膜而圖案化，以形成電極墊4、5、6。電極墊4、5、6，在從裝置基板2的背面2B側藉由例如蝕刻而形成路由孔時，其功能是作為停止層。
又，第4圖所示的步驟中，在電極墊4、5、6上分別形成凸塊本體14a，此外在包圍半導體電路3的位置形成封裝框7。此情形下，各凸塊本體14a與封裝框7，為了將對基板2、8的接合狀態均一化，合意的是使用相互相同材料而同時形成。舉一具體例，在使用光阻材料而形成圖案化的裝置基板2上，充填銲接劑等的金屬膏。藉此，能夠將具有既定圖案的凸塊本體14a及封裝框7，以相互相等的高度尺寸同時地有效率地形成。
在此，在將凸塊本體14a及封裝框7在裝置基板2上直接圖案化的情形下，有無法得到高密著性的情形。因此，在裝置基板2上，合意的是預先形成兼作為凸塊本體14a的接合部的電極4、5、6以及成為封裝框7的接合部的接合墊15。接合墊15係使用氣相沈積等的手段而形成，構成封裝框7的一部分。 又，在本發明中，如後所述，可以不形成電極4、5、6，而將凸塊部14直接形成於路由部10上。又，本發明中，將凸塊部14形成在所有的路由部10的位置上雖是必要，但是除此之外，可以將凸塊部14形成在路由部10不存在的位置。
一方面，第5圖表示在蓋基板上形成接合墊的步驟。此步驟和第4圖所示步驟是分別地被執行。第5圖所示步驟中，在蓋基板8的表面8A，形成成為凸塊部14的接合部的接合墊16、及成為封裝框7的接合部的接合墊17。接合墊16是構成凸塊部14的一部分。接合墊17被與封裝框7一體化，成為其一部分。又，在第4、5圖中是例示，在裝置基板2形成凸塊本體14a及封裝框7之後，將這些的凸塊本體14a及封裝框7與蓋基板8接合情形下的步驟。但是，本發明並非限定於此，亦可以在蓋基板8形成凸塊本體14a及封裝框7之後，將這些的凸塊本體14a及封裝框7與裝置基板2接合。
接著，第6圖表示將裝置基板與蓋基板接合的步驟。此步驟是在第4、5圖所示的步驟之後執行。第6圖所示的步驟中，使用像是例如由Sn、SnAg構成的銲接劑等熔點低的金屬，將裝置基板2側的封裝框7與蓋基板8側的接合墊17(或蓋基板8)壓黏而接合。在此步驟中，合意的是以例如200℃以上的溫度進行接合。又，作為本步驟中的接合方法，可以使用像是例如Au等的同一金屬材料而形成兩者的接合面、且利用超音波將該接合面接合的方法。又，可以使用混合例如Au、Ag、Cu、Pd、Pt等微細金屬粒子於溶劑中的膏劑而形成薄膜，且在藉由將此薄膜圖案化而形成封裝框7及各凸塊本體14a之後，利用 200℃~500℃的高溫以壓黏而接合。又，為了使接合穩定，合意的是，將封裝框7及各凸塊本體14a的接合面積降低為所需的最小限度，提高施加至接合部的壓力。列舉具體例合意的是，設定封裝框7的寬度為20μm程度，且設定凸塊部14a的直徑為Φ50μm程度。
封裝框7及各凸塊部14的高度(從裝置基板2或蓋基板8突出的尺寸)，可以是比半導體電路3大的尺寸。列舉具體例，當半導體電路3包含HEMT及HBT等的電晶體時，高度係取決於其輸出電力量，但基本上，合意的是將封裝框7及各凸塊部14的高度設定為3~20μm程度。又，在GaAs高輸出半導體的情形下，GaAs的熱阻抗高，裝置基板2的厚度厚會不利於對路由孔的蝕刻。因此，裝置基板2的厚度，合意的是設定為例如數10~數10μm程度。
又，裝置基板2上，會擔心因接合時的壓力而產生龜裂等。因此，裝置基板2的厚度，合意的是最後形成比必需的尺寸大。在此情形中，於接合後將裝置基板2薄板化之後，進行路由孔等的蝕刻及電極11、12、13的形成。一方面，關於蓋基板8，由於沒有進行路由孔等的加工且無進行薄板化的優點，所以難以發生龜裂。因此，蓋基板8的厚度可以是例如500μm程度。又，在蓋基板8也有進行路由孔等的加工的情形下，合意的是將蓋基板8的厚度設定為與裝置基板2相同的程度、且在接合後薄板化。又，第7圖表示在接合後將裝置基板及蓋基板薄板化的步驟。
接著，第8圖表示在裝置基板形成路由部及背面側 的電極的步驟。此步驟是在第6圖(及第7圖)所示步驟之後被執行。第8圖所示的步驟中，首先，在藉由微影成像形成光阻圖案之後，使用乾蝕刻或濕蝕刻形成路由孔。之後，使用光阻溶解性的藥品去除光阻圖案，或使用氧電漿處理分解以去除光阻圖案。接著，藉由例如濺鍍等的手段，在裝置基板2的背面2A側及路由孔內形成成為片層的導電膜，此外，在片層上形成藉由電解鍍膜法等產生的導電金屬的厚膜。導電金屬的厚度取決於半導體電路流通的電流值，基本上，合意的是形成數μm以上的膜厚(鍍膜厚度)。又，導電金屬係在路由孔內順應性(conformal)地形成、或埋入形成。又，藉由將如此形成的金屬進行圖案化，以形成各路由部10及背面側的電極11、12、13。此時，電極11、12、13係以相互分離的狀態被形成。作為圖案化的方法，舉例例如有在各路由部10及電極11、12、13上形成光阻圖案且利用濕藥品進行蝕刻的方法等。又，當導電金屬是Au鍍膜時，能使用碘化鉀水溶液作為濕藥品。又，基板接合以後進行的步驟，亦即關於裝置基板的薄板化、路由形成等的步驟，可以在基板接合前進行。
藉由以上的步驟，能製造半導體裝置1。又，這些步驟，例如第9、10圖所示，能將複數裝置基板2及蓋基板8分別形成於晶圓18及19、且將晶圓18、19互相接合。藉此，能夠統整複數半導體裝置1以有效率地製造。又，第9圖表示在晶圓上形成複數裝置基板及該基板側的構成要素之步驟的說明圖。又，第10圖表示在晶圓上形成複數蓋基板及該基板側的構成要素之步驟的說明圖。關於此等圖示，標記20是用以在各個 裝置基板2及蓋基板8互相可對合的位置形成於晶圓18、19上的對位標記。
依據上述半導體裝置1，能得到如下的功用效果。首先，參照第11、12圖，說明習知技術的問題。第11圖是表示習知技術的半導體裝置的一例的剖面圖，而第12圖是表示第11圖中產生氣密破壞的部位的主要部分的放大圖。又，於第11、12圖，對於與本實施樣態的半導體裝置1共同的構成要素，則在相同符號上付加「'(破折號)」以作為標記。
通常，在形成於裝置基板2'的路由孔的壁側上，會存在蝕刻時產生的聚積物等。因此，既使將導電金屬以緊密狀態形成於側壁上，也容易減低其密著性。而且，路由孔內的導電金屬與裝置基板2'之間，線膨脹率互相有差異。因此，對半導體裝置加上熱履歷時，於例如第12圖中的■印的部分中，路由孔內的導電金屬會有剝離的情形，而施加應力至被接合於該導電金屬的電極墊5'、6'則會有電極墊剝離的情形；結果產生中空部9'的氣密性破壞的問題。專利文件1、2、3所記載的半導體裝置中，由於路由部沒有透過凸塊部而補強，所以保持中空部的氣密性是困難的。
對此，於本實施樣態中，在全部的路由部10上形成凸塊部14，且將該凸塊部14作為接合蓋基板8的構成。依據此種構成，能夠藉由被蓋基板8支持的凸塊部14而補強路由部10，且能夠抑制路由部10內的導電金屬及電極墊4、5、6的變形、剝離等。藉此，能夠提高裝置基板2及蓋基板8的接合可靠度、以及穩定地保持中空部9的氣密性。因此，依據本實施樣 態，半導體裝置1的良率及耐久擋得以提昇。
又，藉由將封裝框7及凸塊部14以相同材料形成，能抑制由熱履歷所導致的裝置基板2和蓋基板8的應力。茲舉一例，接合基板2、8的步驟中，由於在例如200℃以上的高溫下執行接合，所以若封裝框7和凸塊部14的線膨脹率相異，在到常溫被冷卻時，基板2、8間容易產生殘留應力。依據本實施樣態，能防止由此種應力所導致的基板2、8的龜裂、剝離、凸塊部14及封裝框7的變形等，以及穩定地確保中空部9的氣密性。又，於專利文件3所記載的半導體裝置中，凸塊部只形成在一部分的路由部上，取代封裝框而將蓋基板蝕刻以形成中空部。因此，在被施加熱履歷時，由於蓋基板與凸塊部的線膨脹率相異，應力施加至基板與凸塊部的接合部、蓋基板與裝置基板的接合部等，恐怕會產生龜裂。依據本實施樣態，能避免此種缺陷。
此外，本實施樣態中，裝置基板2及蓋基板8可由同一材料形成。在此情形下，能將基板2、8的線膨脹率設定為相同值，在施加熱履歷時，能抑制基板2、8間的封裝框7及凸塊部14上產生的應力。因此，能提昇接合部的強度及穩定地確保中空部9的氣密性。
又，於本實施樣態中，利用包含例如Au、Ag、Cu、Pt、Pd等金屬材料、或此等的合金等的導電性材料，形成封裝框7及凸塊部14。藉此，能使用具有高導電性的凸塊部14，將半導體電路3連接接地電極11、輸入電極12及輸出電極13。因此，能夠一方面使用凸塊部14補強路由部10，一方面將電極墊 4、5、6的取出結構簡略化、且容易進行該電極的取出。又，能控制輸入訊號及電力的耗損，實現省電力型的半導體裝置1。又，於本發明中，可以將至少一部分的凸塊部14以上述金屬材料或其合金形成，一部分的凸塊部14可以由其他金屬材料或絕緣材料形成。
又，本實施樣態中，將封裝框7和凸塊部14的高度以相同尺寸形成，裝置基板2及蓋基板8形成沒有凹部等存在的平板狀。依據此種構成，即使在裝置基板2及蓋基板8沒有施加凹部等的加工，也能在基板2、8之間形成中空部9。藉此，能將基板2、8的加工步驟簡略化，以及抑制製程成本。
又，本實施樣態中，作為從半導體電路3將訊號取出的電極，已例示有接地能極11、輸入電極12、及輸出電極13。但是此等電極11、12、13是一例，本發明並非限定於此。從半導體電路3取出電極中的1個電極，須連接電磁屏蔽金屬，除此之外的電極則藉由本實施樣態所提的結構而被電性地分離。作為那些電極，除了有例如輸入輸出電極之外，列舉的有用以確認電氣特性的測試用電極等。
實施樣態2
接著，參照第13至15圖，說明關於本發明實施樣態2。本實施樣態的特徵，在蓋基板的背面上形成導電膜。第13圖是將本發明實施樣態2的半導體裝置的蓋基板從裝置基板側所見的仰視圖。又，第14圖是表示半導體裝置在第13圖中的箭號I-I線位置割裂的剖面圖；第15圖是表示本發明實施樣態2的半導體裝置在第13圖中的箭號Ⅱ-Ⅱ線位置割裂的剖面圖。又，本 實施樣態的半導體裝置21的平面圖與第1圖相同。如第13至第15圖所示，半導體裝置21與實施樣態1的半導體裝置1係大致上相同地構成，但是具有形成在蓋基板8的表面8A的導電膜22。
導電膜22構成半導體裝置21的電磁屏蔽膜，所以係由導電性材料(合意的是與接合墊16相同的金屬材料)所形成。又，導電膜22如第13、14圖所示，將一部分的凸塊部14A的周圍除外，係覆蓋蓋基板8的表面8A。亦即，導電膜22係以包圍凸塊部14A的接合墊16之方式而被形成，在該接合墊16與導電膜22之間形成包圍接合墊16的絕緣蓋23。藉此，導電膜22從凸塊部14A及接合墊16，被分離且絕緣。
一方面，導電膜22，如第15圖所示，與凸塊部14B的接合墊16(參照第3圖)及封裝框7的接合墊17被一體化。藉此，導電膜22，將凸塊部14A的周圍除外，全面地覆蓋蓋基板8的表面8A。而且，導電膜22，是在藉由絕緣蓋23而與輸入電極墊5及輸出電極墊6絕緣的狀態，且透過凸塊部14B、路由部10及接地電極11而被接地。又，由導電性材料形成的封裝框7被連接於導電膜22，所以與導電膜22以相同的路徑而被接地。藉此，半導體電路3的周圍，藉由導電膜22、封裝框7及接地電極11而大致上全體被電磁屏蔽。
依據如此構成的本實施樣態，相較於例如專利文件4、5所記載的習知技術，能得到高的電磁屏蔽性。亦即，於此等習知技術中，裝置的側面上有並未形成電磁屏蔽膜的部分，電磁屏蔽膜沒有完全地包圍裝置。因此，電磁屏蔽性不充分，恐會產生電磁波的輻射及侵入。對於此，於本實施樣態中， 使用導電膜22、封裝框7及接地電極11，能夠將半導體電路3從第15圖的上下、下方及側方(蓋基板8側、裝置基板2側及封裝框7)大致全體地電磁屏蔽。因此，對於來自外部的電磁波及半導體電路3自身的不必要輻射，能夠安定半導體電路3的動作。又，也能夠安配置在半導體裝置21周圍的裝置的動作。
又，絕緣蓋23的寬，合意的是形成比半導體電路3所處理的電磁波的波長短的尺寸。藉此，於抑制對於輸入電極墊5及輸出電極墊6的電磁波的影響，且更提昇電磁屏蔽性。又，於本實施樣態中，能使用凸塊部14B將導電膜22連接接地電極11側。藉此，除了有與前述實施樣態1相同的功效之外，能夠簡化電磁屏蔽的配線結構，且能容易地形成具有高可靠度的半導體裝置21。
實施樣態3
接著，參照第16至18圖，說明本發明實施樣態3。本實施樣態的特徵是，取代前述實施樣態2的絕緣蓋，而由絕緣材料形成凸塊部的至少一部分。第16圖是表示將本發明實施樣態3的半導體裝置的蓋基板從裝置基板側所見的仰視圖。又，第17圖是表示將半導體裝置在第16圖中的箭號I-I線位置割裂的剖面圖；第18圖是表示將半導體裝置在第16圖中的箭號Ⅱ-Ⅱ線位置割裂的剖面圖。又，本實施樣態的半導體裝置31的平面圖與第1圖相同。
如第16至18圖所示，半導體裝置31與實施樣態2的半導體裝置21是大致相同的構成。但是，凸塊部14具有凸塊14B、及取代凸塊部14A而被配置的凸塊部14C。又，半導體裝 置31，具有形成於蓋基板8的表面8A是電磁屏蔽膜的導電膜32、以及使用絕緣材料而被形成於裝置基板2的表面2A側的絕緣膜33。
絕緣膜33例如由SiN膜所形成，且具有200nm程度的厚度。這種絕緣膜33，能使用例如電漿CVD(化學氣相沈積)裝置來形成。絕緣膜33覆蓋半導電路3、電極墊5、6。又，在封裝框7及凸塊部14B的位置，如第18圖所示，以蝕刻等手段去除絕緣膜33。
凸塊部14C的一部分由絕緣膜33構成。更具體而言，凸塊部14C的凸塊本體14a透過絕緣膜33而被連結至輸入電極墊5及輸出電極墊6上。藉此，凸塊部14C一方面連結路由部10及蓋基板8，一方面將導電膜32保持在與輸入電極墊5及輸出電極墊6絕緣的狀態。結果，導電膜32，如第16至18圖所示，將蓋基板8的表面8A全面地覆蓋。又，導電膜32也兼作為形成在蓋基板8的全部的接合墊16(參照第3圖)。
依據此種構成的本實施樣態，在導電膜32上，不須設置用以將該導電膜32與輸入電極墊5及輸出電極墊6絕緣的絕緣蓋。因此，能以導電膜32將蓋基板8的表面8A完全地覆蓋。結果，除了有與前述實施樣態2相同的功外之外，能使半導體裝置31的電磁屏蔽性進一步提昇。
實施樣態4
接著，參照第19圖以說明本發明實施樣態4。本實施樣態的特徵是，凸塊部中用絕緣材料形成與實施樣態3不同的的部位。第19圖是本發明實施樣態4的半導體裝置從與第2圖相同的 位置所見的剖面圖。本實施樣態的半導體裝置41具有導電膜42及絕緣膜43。又，半導體裝置41的凸塊部14，具有凸塊部14B、及取代凸塊部14A而被配置的凸塊部14D。
導電膜42由導體性材料全面地形成於蓋基板8的表面8A，以構成電磁屏蔽膜。絕緣膜43在凸塊部14D的位置形成於導電膜42上。凸塊部14D中位於蓋基板8側的一部分，藉由絕緣膜43構成。亦即，凸塊本體14a是透過絕緣膜43而連結導電膜42。藉此，凸塊部14D一方面連結路由部10及蓋基板8，一方面將導電膜42保持為與輸入電極墊5及輸出電極墊6絕緣的狀態。此種構成的本實施樣態，能得到與前述實施樣態3相同的功效。
實施樣態5
接著，參照第20圖以說明本發明實施樣態5。本實施樣態的特徵是將凸塊部全體以絕緣材料形成。第20圖是本發明實施樣態5的半導體裝置從與第2圖相同的位置所見的剖面圖。依據本實施樣態的半導體裝置51具有導電膜52，是與前述實施樣態4同樣地被形成的電磁屏蔽膜。又，半導體裝置51的凸塊部14，具有凸塊部14B、以及取代凸塊部14A而被配置的凸塊部14E。
凸塊部14E具有由絕緣材料形成的凸塊本體14a'，且被連接至導電膜52。藉此，凸塊部14E一方面連結路由部10及蓋基板8、一方面將導電膜52保持為與輸入電極墊5及輸出電極墊6絕緣的狀態。此種構成的本實施樣態，能得到與前述實施樣態3相同的功效。
實施樣態6
參照第21圖以說明本實施樣態6。本實施樣態的特徵在於用絕緣膜覆蓋半導體電路且由此絕緣膜形成凸塊部的至少一部分。第21圖是本發明實施樣態6的半導體裝置從與第2圖相同的位置所見的剖面圖。本實施樣態的半導體裝置61，具有導電膜62及絕緣膜63；導電膜62是和前述實施樣態4相同地被形成的電磁屏蔽膜。又，半導體裝置61的凸塊部14，具有凸塊部14B、及取代凸塊部14A而被配置的凸塊部14F。
絕緣膜63和前述實施樣態3相同，由例如SiN膜所形成，且覆蓋半導體電路3、電極墊5、6。又，在封裝框7及凸塊部14B的位置，以蝕刻等手段將絕緣膜63去除。又，絕緣膜63從蓋基板8側覆蓋凸塊部14F的凸塊本體14a。亦即，凸塊部14F中位於蓋基板8側的一部分由絕緣膜63構成，凸塊本體14a透過絕緣膜63而連結導電膜62。藉此，凸塊部14F一方面連結路由部10及蓋基板8，一方面將導電膜62保持為與輸入電極墊5及輸出電極墊6絕緣的狀態。此種構成的本實施樣態，能得到與前述實施樣態3相同的功效。
又，前述實施樣態3至6，雖將凸塊部14C、14D、14E、14F的至少一部分用絕緣材料形成，但於本發明中，關於全部的凸塊部14可以用絕緣材料構成至少一部分。
實施樣態7
接著，參照第22至25圖以說明本發明實施樣態7。本實施樣態的特徵在於將路由部形成於蓋基板上。第22圖是將本發明實施樣態7的半導體裝置從與第2圖相同的位置所見的剖面圖，第23圖是將本發明實施樣態7的半導體裝置從與第3圖相同 的位置所見的剖面圖。又，第24圖是在本發明實施樣態7中將半導體裝置構裝於基材的狀態概要表示的剖面圖。又，本實施樣態的半導體裝置71的平面圖與第1圖相同。又，第24圖是為表示構裝狀態之目的而簡化其圖示，各部分的形狀等和其他的圖示會有不同的情形。
如第22、23圖所示，半導體裝置71雖與前述實施樣態1相同構成，但是裝置基板2的背面2B上只有形成接地電極72，輸入電極73及輸出電極74則形成於蓋基板8的背面8B。因此，裝置基板2的背面2B上，如第23圖所示，由於沒有輸入電極及輸出電極存在，所以接地電極72作為全面覆蓋背面2B的平坦單一的導電膜而被形成，且透過一部分的路由部10而連接接地電極墊4。
一方面，蓋基板8上，如第22圖所示，設置有與裝置基板2的路由部10相同地被形成的複數路由部75。這些路由部75，係藉由將金屬材料充填至形成於蓋基板8的路由孔的內部而被形成，且貫通蓋基板8而露出表面8A及背面8B。輸入電極73透過一部分的路由部75及凸塊部14A而連接輸入電極墊5。又，輸出電極74透過其他的路由部75及凸塊部14A而連接輸出電極墊6。
此狀態中，凸塊部14A連結蓋基板8側的路由部75及裝置基板2，並構成第2凸塊部。一方面，凸塊部14B連結裝置基板2側的路由部10及蓋基板8，並構成第1凸塊部。於本實施樣態中例示的是，第2凸塊部14A被用於路由部75的補強及半導體電路3的外部連接，而第1凸塊部14B只被用於路由部10的 補強而沒有用於半導體電路3的外部連接。
此成構成的半導體裝置71，能將由單一導電膜所形成的接地電極72全體地設置於裝置基板2的背面2B，且能提昇散熱性。茲列舉具體例，半導體裝置71，如第24圖所示，係構裝於由例如Cu、CuW等的平坦金屬板所構成的基材76而被使用。特別的是，高輸出的半導體裝置71中，由於半導體電路3是發熱源，所以黏晶在散熱性良好的基76上而使用。例如AuSn等的銲劑被使用於黏晶。在將半導體裝置71黏晶時，將裝置基板2的背面2B側全體、亦即接地電極72全體，以面接觸狀態接合於基材76，能提昇半導體裝置71的散熱性。又，於基材76上設置整合基板77，輸入電極73及輸出電極74藉由銲線78而連接至整合基板77。
在此，第25圖是表示習知技術中的半導體裝置的構裝狀態的剖面圖。此圖概要表示例如專利文件1、2、3所記載的習知技術的構成。如第25圖所示，習知技術中，輸入電極、輸出電極及接地電極全部配置在裝置基板的背面側。因此，當將半導體裝置構裝於基材上時，輸入電極及輸出電極被連接至整合基板，只有接地電極被與基材接合。結果，習知技術中，從半導體裝置往基材的散熱路徑，被限制為裝置基板中的接地電極，與裝置基板的面積相比較，散熱路徑的面積變小，而有散熱性降低的問題。又，於專利文件4記載的習知技術中，搭載晶片的基板的背面側，由於不是接地電極等的單一電極，會產生與第25圖所示構成相同的問題。
對於此，在本實施樣態，能夠從裝置基板2的背面 2B全體對基材76散熱，且能提昇半導體裝置71的散熱性。又，如第25圖所示的習知技術中，連接輸入電極及輸出電極至整合基板上的高度位置與連接接地電極至基材的高度位置，是只有整合基板的厚度分量差異。因此，在基材上必須形成用以吸收連接位置的高度差異的凸部，而有基材的加工成本變高的問題。本實施樣態中，能解決此問題。因此，依據本實施樣態，除了有與前述實施樣態1相同的功效之外，能實現具有高散熱性能的半導體裝置71。
實施樣態8
接著，參照第26、27圖以說明本發明實施樣態8。本實施樣態的特徵在於，對前述實施樣態7的半導體裝置，形成覆蓋蓋基板的背面全體的導電膜。第26圖是本發明實施樣態8的半導體裝置從與第2圖相同的位置所見的剖面圖。第27圖是本發明實施樣態8的半導體裝置從與第3圖相同的位置所見的剖面圖。又，本實施樣態的半導體裝置81的平面圖與第1圖相同。
如第26、27圖所示，半導體裝置81雖與前述實施樣態7相同地構成，但是具有導電膜82，導電膜82是形成於蓋基板8的表面8A的電磁屏蔽膜。導電膜82與前述實施樣態2相同，將一部分的凸塊部14A的周圍除外而覆蓋蓋基板8的表面8A，且與該凸塊部14A及其接合墊16分離及絕緣。又，凸塊部14B透過接地電極墊4及接地電極72而被接地。
依據如此構成的本實施樣態，能得到將前述實施樣態2及7合併的功效。因此，能實現電磁屏蔽性及散熱性高的半導體裝置81。
實施樣態9
接著，參照第28圖以說明本發明實施樣態9。本實施樣態的特徵是在蓋基板的表面側設置其他半導體電路。第28圖是本發明實施樣態9的半導體裝置從與第2圖相同的位置所見的剖面圖。如圖所示，本實施樣態的半導體裝置91，藉由將例如2個半導體晶片92、93上下地積層而構成。半導體晶片92、93，例如是與在實施樣態1所說明的半導體裝置1同樣的構成。
共通基板94是將半導體晶片92的蓋基板及半導體晶片93的裝置基板共同化之物，具有表面94A及背面94B。共通基板94的背面94B側形成半導體晶片93的半導體電路3。又，半導體晶片93的蓋基板8的背面8B側，設有該半導體晶片93的接地電極95、輸入電極96、及輸出電極97。這些電極95、96、97透過凸塊部14連接半導體電路3。又，第28圖中，係例示將2個半導體晶片92、93積層的情形，但是本發明亦適用於將3個以上的任意數目的半導體晶片積層的構成。又，於本發明中，可以是在共通基板94形成路由部、且透過此路由部將半導體晶片92的半導體電路3及半導體晶片93的半導體電路3相互連接的構成。藉此，能縮短晶片92、93們的連接距離且提昇訊號傳輸效率。
依據此構成的本實施樣態，能實現將複數半導體晶片92、93堆疊的構成。於高頻裝置中，有物件需要複數半導體晶片。此情形下，如本實施樣態，能利用將各半導體晶片上下積層，降低訊號的損失及提昇半導體裝置91的性能。此外，對於此種積層的半導體晶片，藉由組合前述實施樣態2所例示 的電磁屏蔽結構，能抑制各半導體晶片間產生的相互干擾，且實現具有高可靠度的半導體裝置。
又，用於高頻電路的電晶體需要整合電路，因此將整合電路連接至半導體晶片上的情形很多。在此情形下，本實施樣態中，若將例如半導體晶片93作為整合電路的話，能將半導體晶片與整合電路上下地積層而形成。藉此，能減少半導體裝置91的構裝面積且促進成本降低。
實施樣態10
接著，參照第29圖以說明本發明實施樣態10。本實施樣態的特徵在於凸塊部是不帶來電極墊及接合墊的構成。第29圖是本發明實施樣態10的半導體裝置從與第2圖相同的位置所見的剖面圖。如圖所示，半導體裝置1'的凸塊部14G只由凸塊本體14a所構成。因此，凸塊本體14a的一端側和路由部10直接接合。凸塊部14a的他端側與蓋基板8的表面8a直接接合。此種構成的本實施樣態，能得到和前述實施樣態1相同的效果。
(實施樣態1至9中的路由部的構成)
接著，參照第30圖以說明前述實施樣態1至9中路由部的構成。第30圖是表示比較本發明實施樣態1至9的路由部的剖面圖30(A)與習知技術的路由部的剖面圖30(B)的說明圖。如第30圖的(A)所示，路由部10藉由在裝置基板2形成路由孔、且在此路由孔內順應性地形成導電層而構成。
在此，所謂「順應性(conformal)」表示，導電層並沒有完全地填充於路由孔內，而是對於路由孔的側壁(被鍍面)以均一厚度形成導電層。但是，厚度不均在不影響使用路由部 10傳輸訊號上的程度，則不會成為問題。具體而言，導電層合意的是，使用例如鍍膜等手段，形成1~3μm程度的厚度。如此而形成的路由部10的導電層，具有例如在裝置基板2的背面2B側開口的空洞10A。又，形成在蓋基板8上的路由部75，和路由部10同樣地被形成，且具有在蓋基板8的背面8B側開口的空洞。
接著，說明關於將導電層順應性地形成時的功效。首先，於例如專利文件1至3所述的習知技術，如第30圖的(B)所示，構成路由部的導電金屬成為完全地被充填於路由孔內的狀態。在此情形下，施加熱履歷時，隨著路由部的導電金屬膨脹及收縮，應力會在周圍的基板上產生。又，第30圖中，將應力的大小以箭號的尺寸大小表示。習知技術中，由於路由部的內部沒有空洞存在，所以導電金屬的熱變形所致的應力會原封不動地施加至周圍的基板，基板側的應力會變大。
對此，於實施樣態1至9的路由部10中，例如已熱膨脹的導電層能逃向空洞10A。藉此，能減低被施加至裝置裝置2、蓋基板8等的應力，及抑制基板2、8的龜裂、電極墊4、5、6的剝離等。結果，相較於習知技術，能防止中空部9的氣密破壞，且能提昇半導體裝置的可靠度。
實施樣態11
接著，參照第31至42圖以說明本發明實施樣態11。本實施樣態中，將凸塊部作為中空結構。第31、32圖是本發明實施樣態11的半導體裝置分別從與第2、3圖相同的位置所見的剖面圖。又，第33圖是將第31圖中的凸塊部等放大表示的主要部分放大剖面圖。第34圖是第33圖中的箭號Ⅲ-Ⅲ線剖面圖，表示 凸塊部的橫剖面圖。如這些圖所示，半導體裝置101，和前述實施樣態1相同，具有基板2、8、半導體電路3、電極墊4、5、6、路由部102、及凸塊部103等。
裝置基板2及蓋基板8，互相以表面2A、8A對向的狀態，透過封裝框7而對合。而且，各表面2A、8A之間，形成由封裝框7所包圍的中空部9。半導體電路3以氣密狀態被收容於中空部9。裝置基板2的表面2A上，形成有連接半導體電路3的接地電極墊4、輸入電極墊5及輸出電極墊6。又，蓋基板8的表面8A上，與實施樣態1相同，形成有作為電極墊的接合墊16。
路由部102，由路由孔102A、及充填金屬102B所構成。路由孔102A作為圓筒狀的貫通孔而被形成，在表面2A及背面2B之間貫通裝置基板2。又，路由孔102A在電極墊4、5、6的背面側開口，其開口端成為圓筒狀。充填金屬102B被充填於路由孔102A的內部並被連接(接合)至電極墊4、5、6，同時在裝置基板2的背面2B上延展。充填金屬102B，如第33圖所示，被形成為與實施樣態1相同的空洞102C。
凸塊部103，是裝置基板2的電極墊4、5、6的任一者與蓋基板8的接合墊16，相互地以一對一進行連結者。凸塊部103藉由例如Au、Ag、Cu、Pt、Pd或其合金，作為圓筒狀的中空結構而被形成。藉由使用此種材料，能提高凸塊部103的熱傳導性、且提昇半導體裝置101的散熱性。因此，降低半導體裝置101的動作溫度而能使動作穩定。
在凸塊部103的內部形成圓柱狀的空洞104。空洞104，軸方向的一端與電極墊4、5、6的任一者的表面對面，另 一端則和接合墊16的表面對面。又，本實施樣態與前述實施樣態1相同，凸塊部103之中，將連接至輸入電極墊5或輸出電極墊6、且透過接地電極墊4及路由部102沒有被接地的凸塊部標記為凸塊部103A。又，將透過接地電極4及路由部102而被接地的凸塊部標記為凸塊部103B。
又，凸塊部103，在連結該凸塊部103的電極墊4、5、6的背面側開口的路由孔102A的全圓周圍上，被配置於路由孔102A的開口端的更外側。列舉更具體的例子，於本實施樣態中，如第34圖所示，所形成凸塊部103的內徑尺寸，大於路由孔102A的孔徑尺寸。亦即，於從軸方向所見的俯視圖中，凸塊部103被配置於比路由孔102A更外圓周側，且在將路由孔102A的全圓周從外圓周側包圍的位置上被配置成同心圓狀。
又，第34圖中例示將空洞104形成圓柱狀的情形，但本發明並非限定於此，可以在凸塊部103的內部形成圓柱狀以外的空洞。茲舉一例，第35圖是於本發明實施樣態11中表示變化例的凸塊部的橫剖面圖。此圖所示的凸塊部103'被形成雙重筒狀，且凸塊部103'的內部形成被置成同心圓狀的2個空洞104'。
接著，參照第36至42圖，說明具有HEMT電晶體結構的半導體裝101的製造順序的一例。這些圖示是從與第3圖相同位置所見的剖面圖。首先，第36圖表示將裝置基板進行圖案化的步驟。在此步驟中，最初，對由例如Si、SiGe、SiC、InP、GaAs等的基板晶圓所製成的基板表面，利用磊晶成長、離子植入等手段，形成具有載子的半導體動作層(主動層)3D。接下來 的處理中，利用微影成像、蝕刻、金屬成膜等手段，形成包含電晶體結構的半導體電路3。於HEMT結構中，在半導體動作層3D上形成有由源極電極3A、汲極電極3B及閘極電極3C所構成的3種電極。
以此方式，形成具有半導體動作層的裝置基板2。又，於本實施樣態的一例中，由於將源極電極3A透過路由部102而在裝置基板2的背面2B側取出，所以在裝置基板2的表面2A形成與源極電極3A連接的接地電極墊4。接地電極墊4是例如藉由連續成膜兩個金屬層形成。此兩個金屬層的一部分是含有例如Ti、Pt、W、Ni等，與裝置基板2的密著性高，且擴散阻礙性良好的金屬層。又，另一部分的金屬層是含有例如Au、Ag、Cu、Pd、Pt等導電性良好的金屬之金屬層。又，在此步驟中，亦藉由與接地電極墊4相同的材料形成接合墊15。
其次，第37圖是表示薄板化裝置基板以形成路由孔之步驟的剖面圖。在此步驟中，首先，為減低裝置基板2的熱阻、電感而將裝置基板2薄板化。裝置基板2的厚度合意的是例如數10μm~數100μm程度。接著，用以將電極墊4、5、6在裝置基板2的背面2B側取出的路由孔102A，分別形成在裝置基板2的既定位置。路由孔102A例如從裝置基板2的背面2B，利用施加濕蝕刻、乾蝕刻等而形成。路由孔102A形成時，接地電極墊4也作為蝕刻的停止層，所以接地電極墊4的厚度，係取決於路由加工條件中電極的蝕刻速度。
其次，第38圖是表示在裝置基板上形成路由部及接地電極之步驟的剖面圖。此步驟中，在利用例如濺鍍、無電 解鍍膜等手段形成片層之後，在已施行光阻圖案之後，藉由電解鍍膜形成接地電極11及充填金屬102B而完成路由部102。此時，合意的是，利用與接地電極墊4之情形相同的2個金屬層連續地成膜而形成片層。電解鍍膜，將例如Au、Ag、Cu、Pd、Pt等的導電層形成1~5μm程度的厚度。使用電解鍍膜的理由是相較於使用濺鍍所形成的膜，容易在路由孔102A的內部附著厚度。又，形成在電極部外的片層，在去除光阻之後係藉由濕蝕刻或乾蝕刻去除。
又，於本實施樣態中，例如第42圖所示的其他變化例，可以是沒有形成接地電極墊4、而形成延伸至裝置基板2的表面2A的路由部102'。在此情形中，首先，在形成路由孔102A之後，將裝置基板2的表面2A及背面2B兩方上的光阻圖案化。而且，藉由形成電極墊5、6及接地電極11，能得到如第42圖所示的結構。
其次，第39圖表示形成凸塊部及封裝框的步驟。此步驟中，在電極墊4、5、6上形成凸塊部103，並且在接合墊15上形成封裝框7。凸塊部103任務是補強電極墊4、5、6，所以合意的是由硬質的材料形成。因此，作為凸塊部103的材料，可使用金屬、矽氧化膜等的無機絕緣膜、或聚酰亞胺等的有機膜。又，全部的路由部102上，通常必須要形成凸塊部103，但在路由部102不存在的部分上也形成凸塊部103不會有問題。
又，封裝框7可以用其他步驟形成，例如在同時形成凸塊部103及封裝框7的情形中，能使凸塊部103及封裝框7高度一致，且能在下個步驟容易地進行蓋基板8的接合。凸塊部 103的高度有必要比HEMT電晶體面的結構物(電極3A、3B、3C等)高，合意的是例如設定為3μm~20μm程度。凸塊部103及封裝框7是金屬的情形下，作為這些部位的形成方法，可以使用例如適於厚膜形成的鍍膜法。使用鍍膜法的情形下，在以光阻進行圖案化之後，利用電性鍍膜或無電解鍍膜形成凸塊部103及封裝框7。又，在進行電性鍍膜的情形下，在將光阻圖進行案化之前，須預先形成片層。
在此，由於凸塊部103是在中央部具有空洞104的結構，所以在用光阻進行圖案化的情形下，和裝置基板2的表面2A平行的剖面中的剖面形狀，成為像環狀(圓形狀)等的一定形狀。凸塊部103，以不受到路由部102的變形等所致影響之方式，在比路由孔102A的外徑更外側以寬幅形成。又，作為封裝框7的材料，合意的是像是例如金屬、矽氧化膜等能提高氣密性的無機絕緣膜。聚酰亞胺等的有機材料，相較於無機絕緣膜，其氣密性差。但是，在和裝置基板2接合時，有機材料能以簡易的程序進行接合。因此，合意的是對應於半導體裝置101所要求的氣密性的標準，以選擇封裝框7的材料。
其次，第40圖表示在蓋基板形成接合墊的步驟。於此步驟中，在蓋基板8的表面8A形成用以接受凸塊部103及封裝框7的接合墊16、17。接合墊16、17，為謀求凸塊部103們的絕緣，而以蝕刻等進行圖案化。
其次，第41圖是表示接合裝置基板及蓋基板之步驟的剖面圖。表示此步驟的一例，例如在使用像是Sn、SnAg銲劑等的低熔點金屬以形成凸塊部103及封裝框7時，在加熱至 超過熔點的200℃以上的溫度的狀態，將凸塊部130及封裝框7與接合墊16、17壓合。作為其他的接合方法，例如有在利用Au等相同金屬形成相互接合的接合面之後，再施加超音波將兩者接合的方法。又，可以在高真空下利用電漿將接合面活性化之後，再於高壓下將兩者接合。此外，可以利用將Au、Ag、Cu、Pd、Pt等細微金屬粒子混合於溶劑而形成奈米膏，並在將此奈米膏進行圖案化而形成凸塊部103及封裝框7之後，以高溫將此等壓合在接合墊16、17。
使用上述任何一種接合方法時，接合時的荷重、超音波、溫度等的參數越高則接合狀態越好。超音波、荷重等，凸塊部103及封裝框7的圖案面積越小，則越在這些部位有效率地作用。但是，圖案過細時，容易產生封裝性的惡化、強度不足等的缺陷，因此基於以不產生此等缺陷的最小限度的尺寸而決定圖案的面積。茲舉一例，成為圓筒狀的凸塊部103的徑方向的壁厚和封裝框7的寬度，合意的是分別設定為5μm~20μm。
作為蓋基板8的材料，可使用例如像是半導體基板、玻璃、藍寶石基板等之平坦性高的基板。因為，基板的平坦性愈高，接合狀態愈均一，能得到穩定的氣密封裝。又，合意的是，裝置基板2與蓋基板8由相同材料形成、或由相互線膨脹率相近的材料形成。藉此，能夠抑制熱履歷導致的應力。又，在使用環氧樹脂、聚酰亞胺膜的有機膜等材料的情形中，氣密性有下降的傾向。
又，於上述半導體裝置101的製造程序中，將裝置基板2薄板化以形成路由部102A的步驟(第37圖)、及在裝置基 板2上形成路由部102及接地電極11的步驟(第38圖)，可以在形成凸塊部103及封裝框7的步驟(第39圖)及在蓋基板8形成接合墊16、17的步驟(第40圖)之後進行。
又，上述製造程序的說明中，是以第32圖的剖面圖為基準，因此顯示接地電極墊4被連接至路由部102的表面側、且接地電極11被連接至路由部102的背面側的狀態。但是本發明並非限定於此，例如於第31圖中，關於被連接至路由部102的表面側的輸入電極墊5及輸出電極墊6、以及被連接至路由部102的背面側的輸入電極12及輸出電極13，是分別以和接地電極墊4、接地電極11相同的程序所形成。
此外，於HEMT以外的裝置中，將形成於基板的表面側的電極經由路由部而在背面側取出的結構，可以用和本實施樣態相同的方法實現。又，於實施樣態11中，例示只在裝置基板2側存在路由部102的情形。但是本發明並非限定於此，也適用只在蓋基板8側存在路由部102的情形、以及在基板2、8的兩方存在路由部102的情形。
此種構成的本實施樣態，也能得到與前述實施樣態1相同的功效。此外，於本實施樣態中，設假凸塊部103是具有空洞104的構成，相較於沒有空洞之中實的凸塊部，能得到如下的功效。在此，說明關於中實的凸塊部的問題點，當在每個路由部形成中實的凸塊部時，形成凸塊部的金屬等的材料使用量變得大幅增加，將招致成本上昇的問題。又，當將凸塊部及封裝框與對像方的基板接合時，凸塊部的個數越多高荷重越是必然的。然而，近年來，由於晶圓朝大直徑演進，中實的凸 塊部的個數一增加，由於接合裝置的荷重能力不足而容易產生接合不良的問題。
對於此，依據本實施樣態，由於將凸塊部103作為中空結構，所以一方面能維持實施樣態1所述的功效，一方面能降低凸塊部103的材料使用量。藉此，能抑制半導體裝置101的成本，且能以低成本將中空部9穩定地封裝。又，凸塊部103於路由部102A的全圓周圍，被設置在比成為圓形狀的路由孔102A的開口端更外側。亦即，本實施樣態中，將凸塊部103的內徑形成的比路由孔102A的外徑大。而且，凸塊部103與電極墊4、5、6接觸的接觸面是在路由孔102A的開口端的全圓周圍上，且設於比該開口端外側的位置的構成。
藉此，凸塊部103能在比路由孔102A內的充填金屬102B外側壓住電極墊4、5、6。因此，能抑制電極墊4、5、6因變形等而從裝置基板2剝離。又，在基板2、8接合時，壓縮凸塊部103而塊化，因此在電極墊4、5、6及充填金屬102B上被施加強力，容易發生這些部位的破損、剝離等。特別的是，充填金屬102B的上面部(電極墊4、5、6的接合部)是薄金屬層，由於強度低，所以在接合時一被施加來自凸塊部103的力，則可能變形破壞而發生外觀不良、接合異常等。但是於本實施樣態中，電極墊4、5、6一被施加來自凸塊部103的力，此力變成在路由孔102A的外側而由裝置裝置2承受。因此，降低在電極墊4、5、6及充填金屬102B上施加的力，能抑制這些破損、剝離等。
又，由於將凸塊部103形成圓筒狀，能減少凸塊部 103與蓋基板8側的接合墊16、17的接觸面積。藉此，在基板2、8接合時，即便以相同荷重，也能使施加至接合部的力增加。因此，接合裝置的最大荷重有限制時，能夠在基板2、8的接合部增加最大限度的荷重，且能夠穩定地接合基板2、8及抑制接合不良。又，因為凸塊部103的中央部成為空洞104，所以對於在製程及構裝步驟中因為熱履歷等所致使的基板2、8的變形、歪曲，能夠改善凸塊部103的追蹤性。
又，本實施樣態中，以投影到與基板2、8的表面2A、8A垂直的平面上的凸塊部103的形狀為長方形的方式而形成。藉此，於基板2、8的接合步驟中，將凸塊部103全體均等地加壓，能對基板2、8垂直地施力。因此，不會使接合時的力逃逸，而能有效地施加至基板2、8，且能提高中空部9的氣密性。
實施樣態12
接著，參照第43、44圖說明本發明實施樣態12。本實施樣態中，只將凸塊部的一部分作成中空結構。第43圖是將本發明實施樣態12的半導體裝置的凸塊部等放大表示的主要部分放大剖面圖。又，第44圖是主要部分放大剖面圖，係從與第43圖相同位置所見的在形成路由孔時發生過蝕刻的模樣。半導體裝置111和前述實施樣態11相同，具有基板2、8、半導體電路3、電極墊4、5、6、路由部102、凸塊部112等。
凸塊部112由第1凸塊層112a、第2凸塊層112b所構成，具有2層結構。第1凸塊層112a作為內部不存在空洞的圓柱狀的中實結構體而被形成。又，凸塊層112a接合至輸出電極墊 6、且和蓋基板8的接合墊16分開。一方面，第2凸塊層112b作為內部有空洞113的圓筒狀的中空結構體而被形成。又，凸塊層112b，在垂直於基板2、8的表面2A、8A的方向上與第1凸塊層112a被沈積，且與凸塊層112a和接合墊16接合。
作為凸塊部112的形成方法，例如在裝置基板2側將凸塊層112a圖案化及在蓋基板8側將凸塊層112b圖案化之後，將凸塊層112a、112b相互接合。又，可以利用在基板2、8其中之一方的基板上進行2次圖案化，且在沈積凸塊層112a和凸塊層112b之後，再與另一方的基板接合。又，考慮凸塊層112a、112b之間對準的差異，可將凸塊層112b的剖面面積形成的比凸塊層112a小。
依據此種構成的本實施樣態，除了有前述實施樣態11相同的功效之外，能得到如下的功效。首先，第44圖是主要部分放大剖面圖，係從與第43圖相同位置所見的在形成路由孔時發生過蝕刻的模樣。作為路由孔102A的蝕刻方法，當使用乾蝕刻時，如第44圖所示，依條件進行蝕刻，對於輸出電極墊6，過蝕刻而成的路由洞會有穿過輸出電極墊6的情形。因此，作為通常的對策，有將輸出電極墊6加厚的方法。但是，此方法須將半導體電路3的電極3A、3B、3C、其他電極墊4、5、接合墊15等全體加厚，有成本上昇的問題。
對此，依據本實施樣態，即使在已將輸出電極墊6薄化的狀態下，能由凸塊層112b承受過蝕刻。因此，一方面防止因過蝕刻導致路由孔102A和中空部9連通，一方面能將輸出電極墊6薄化以促進成本降低。此外，凸塊部112藉由部分的空 洞113能發揮與實施樣態11相同的功效。
又，於本實施樣態中，已例示將凸塊部112與輸出電極墊6接合的情形。但是本發明並非限定於此，凸塊部112亦能適用和其他的電極墊4、5接合的凸塊部。

Claims (19)

  1. 一種半導體裝置，包括：裝置基板，具有表面及背面；半導體電路，設置於前述裝置基板的表面側；封裝框，接合於前述裝置基板的表面、且包圍前述半導體電路；蓋基板，由具有表面及背面的基板所形成，前述基板的前述表面以覆蓋前述半導體電路的狀態而與前述封裝框的全周圍接合，在前述蓋基板與前述裝置基板之間形成以氣密狀態收容前述半導體電路的中空部；複數第1路由部，由導電性材料所形成用以將前述半導體電路連接至外部，且貫通前述裝置基板的表面和背面同時連接前述半導體電路；複數凸塊部，在前述中空部的內部分別設置於全部的前述第1路由部上，且連結該前述第1路由部與前述蓋基板。
  2. 如申請專利範圍第1項所述之半導體裝置，其中前述各凸塊部中至少一部分的凸塊部，由導電性材料所形成；於前述蓋基板的表面上設置覆蓋該表面的導電膜，前述一部分的凸塊部中透過前述第1路由部而沒有被接地的凸塊部則與前述導電膜絕緣。
  3. 如申請專利範圍第1項所述之半導體裝置，其中前述各凸塊部中至少一部分的凸塊部，由導電性材料所形成；前述一部分的凸塊部中透過前述第1路由部而沒有被接地的凸塊部，至少一部分由絕緣材料所形成；前述蓋基板的表面上，設置將該表面全面地覆蓋的導電膜。
  4. 如申請專利範圍第1至3項其中任一項所述之半導體裝置，其中更包括複數第2路由部，由導電性材料所形成，用以將前述半導體電路連接至外部，且貫通前述蓋基板的表面和背面、同時連接前述半導體電路；構成前述凸塊部的第1凸塊部以外的第2凸塊部，被配置在前述中空部，且被設置於前述蓋基板的前述第2路由部上、同時連結該第2路由部與前述裝置基板。
  5. 如申請專利範圍第4項所述之半導體裝置，其中前述各凸塊部中至少前述第2凸塊部，由導電性材料形成；在前述蓋基板的表面上設置覆蓋該表面的導電膜，前述導電膜與前述第2凸塊部絕緣。
  6. 如申請專利範圍第4項所述之半導體裝置，其中在前述裝置基板的背面，設置透過形成於該裝置基板的前述第1路由部而被連接至前述半導體電路的單一的導電膜。
  7. 一種半導體裝置，包括：裝置基板，具有表面及背面；半導體電路，設置於前述裝置基板的表面側；封裝框，接合於前述裝置基板的表面、且包圍前述半導體電路；蓋基板，由具有表面及背面的基板所形成，前述基板的前述表面以覆蓋前述半導體電路的狀態而被接合於前述封裝框，同時在前述蓋基板與前述裝置基板之間形成以氣密狀態收容前述半導體電路的中空部；複數第1路由部，由導電性材料所形成以將前述半導體電路連接至外部，且貫通前述裝置基板的表面和背面同時連接前述半導體電路；複數凸塊部，在前述中空部的內部分別設置於前述第1路由部上，且連結該前述第1路由部與前述蓋基板；複數第2路由部，由導電性材料所形成以將前述半導體電路連接至外部，且貫通前述蓋基板的表面和背面、同時連接前述半導體電路；構成前述凸塊部的第1凸塊部以外的第2凸塊部，被配置在前述中空部，且被設置於前述蓋基板的前述第2路由部上、同時連結該前述第2路由部與前述裝置基板；連接至前述半導體電路的輸入電極、輸出電極及接地電極；其中，前述各凸塊部中至少前述第2凸塊部由導電材料形成；前述輸入電極及前述輸出電極，設置在前述蓋基板的表面、同時透過前述蓋基板的前述第2路由部與第2凸塊部連接前述半導體電路；前述接地電極，由覆蓋前述裝置基板的背面的單一導電膜所形成、同時透過前述裝置基板的前述第1路由部連接前述半導體電路。
  8. 如申請專利範圍第1至3項其中任一項所述之半導體裝置，其中前述第1路由部，是在前述裝置基板或前述蓋基板上形成的貫通孔內順應性地形成者，且具有空洞的構成。
  9. 如申請專利範圍第1至3項中任一項所述之半導體裝置，其中前述封裝框由導電性材料形成。
  10. 如申請專利範圍第1至3項中任一項所述之半導體裝置，其中前述凸塊部及前述封裝框由Au、Ag、Cu、Pt、Pd或其合金所形成。
  11. 如申請專利範圍第1至3項中任一項所述之半導體裝置，其中前述封裝框和前述凸塊部由相同材料所形成。
  12. 如申請專利範圍第1至3項中任一項所述之半導體裝置，其中前述裝置基板和前述蓋基板由相同材料所形成。
  13. 如申請專利範圍第1至3項中任一項所述之半導體裝置，其中前述封裝框和前述凸塊部的高度以相同尺寸形成，且將前述裝置基板及前述蓋基板形成為不存在凹陷的平板狀。
  14. 如申請專利範圍第1至3項中任一項所述之半導體裝置，其中在前述蓋基板的表面側，設置其他的半導體電路。
  15. 一種半導體裝置，包括：2個基板，分別具有與對像方的基板對向的對向面，藉由在對向面對向狀態下相互地對合，而在前述各對向面之間形成中空部；電極墊，分別形成於前述各基板的對向面；半導體電路，被以氣密狀態收容於前述中空部，且連接至少一部分的前述電極墊；路由部，形成於前述各基板中至少一方的基板上，並且具有貫通前述一方的基板而在前述電極墊的背面側開口的路由孔、以及被充填於前述路由孔以連接前述電極墊的充填金屬；凸塊部，作為內部有空洞的中空結構體而被形成，且將前述一方的基板的前述電極墊與另一方的基板的前述電極墊連結。
  16. 如申請專利範圍第15項所述之半導體裝置，其中前述凸塊部，在與該凸塊部連結的前述電極墊的背面側開口的前述路由孔的全周圍，配置在比前述路由孔的開口端更外側。
  17. 如申請專利範圍第15或16項所述之半導體裝置，其中前述凸塊部，包括第1凸塊層，作為內部沒有空洞的中實結構體而被形成，且被連結至前述一方的基板的前述電極墊、同時與前述另一方的基板的前述電極墊分離；第2凸塊層，作為內部有空洞的中空結構體而被形成，在與前述基板的對向面垂直的方向上，與前述第1凸塊層被沈積、同時連結前述第1凸塊層與前述另一方的基板的前述電極墊。
  18. 如申請專利範圍第1至3、15、16項其中任一項所述之半導體裝置，其中前述凸塊部，以投影在與前述基板的對向面垂直的平面上的形狀為長方形的方式而形成。
  19. 如申請專利範圍第15項所述之半導體裝置，其中前述凸塊部由Au、Ag、Cu、Pt、Pd或其合金所形成。
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