TWI618222B - 使用整塊三維積體電路技術之完整系統晶片 - Google Patents

使用整塊三維積體電路技術之完整系統晶片 Download PDF

Info

Publication number
TWI618222B
TWI618222B TW103122569A TW103122569A TWI618222B TW I618222 B TWI618222 B TW I618222B TW 103122569 A TW103122569 A TW 103122569A TW 103122569 A TW103122569 A TW 103122569A TW I618222 B TWI618222 B TW I618222B
Authority
TW
Taiwan
Prior art keywords
levels
3dic
monolithic
level
providing
Prior art date
Application number
TW103122569A
Other languages
English (en)
Chinese (zh)
Other versions
TW201513299A (zh
Inventor
楊 杜
Original Assignee
高通公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 高通公司 filed Critical 高通公司
Publication of TW201513299A publication Critical patent/TW201513299A/zh
Application granted granted Critical
Publication of TWI618222B publication Critical patent/TWI618222B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/297Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW103122569A 2013-07-16 2014-06-30 使用整塊三維積體電路技術之完整系統晶片 TWI618222B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361846648P 2013-07-16 2013-07-16
US61/846,648 2013-07-16
US14/013,399 2013-08-29
US14/013,399 US9418985B2 (en) 2013-07-16 2013-08-29 Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology

Publications (2)

Publication Number Publication Date
TW201513299A TW201513299A (zh) 2015-04-01
TWI618222B true TWI618222B (zh) 2018-03-11

Family

ID=52343114

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103122569A TWI618222B (zh) 2013-07-16 2014-06-30 使用整塊三維積體電路技術之完整系統晶片

Country Status (9)

Country Link
US (2) US9418985B2 (https=)
EP (1) EP3022766A1 (https=)
JP (1) JP2016529702A (https=)
KR (1) KR101832330B1 (https=)
CN (1) CN105378918B (https=)
BR (1) BR112016000868B1 (https=)
CA (1) CA2917586C (https=)
TW (1) TWI618222B (https=)
WO (1) WO2015009614A1 (https=)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418985B2 (en) 2013-07-16 2016-08-16 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
ES2798115T3 (es) * 2014-06-20 2020-12-09 Nagravision Sa Módulo de interfaz física
US9256246B1 (en) * 2015-01-29 2016-02-09 Qualcomm Incorporated Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US9628077B2 (en) 2015-03-04 2017-04-18 Qualcomm Incorporated Dual power swing pipeline design with separation of combinational and sequential logics
CN105391823B (zh) * 2015-11-25 2019-02-12 上海新储集成电路有限公司 一种降低移动设备尺寸和功耗的方法
CN105742277B (zh) * 2016-04-13 2018-06-22 中国航天科技集团公司第九研究院第七七一研究所 一种大容量立体集成sram存储器三维扩展方法
US9523760B1 (en) * 2016-04-15 2016-12-20 Cognitive Systems Corp. Detecting motion based on repeated wireless transmissions
US9754923B1 (en) 2016-05-09 2017-09-05 Qualcomm Incorporated Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US9929149B2 (en) 2016-06-21 2018-03-27 Arm Limited Using inter-tier vias in integrated circuits
US9871020B1 (en) * 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
US10678985B2 (en) * 2016-08-31 2020-06-09 Arm Limited Method for generating three-dimensional integrated circuit design
US9712168B1 (en) * 2016-09-14 2017-07-18 Qualcomm Incorporated Process variation power control in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US10176147B2 (en) * 2017-03-07 2019-01-08 Qualcomm Incorporated Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods
US10727965B2 (en) * 2017-11-21 2020-07-28 Western Digital Technologies, Inc. System and method for time stamp synchronization
US10719100B2 (en) 2017-11-21 2020-07-21 Western Digital Technologies, Inc. System and method for time stamp synchronization
CN110069795A (zh) * 2018-01-23 2019-07-30 长芯半导体有限公司 快速定制芯片方法
GB2586049B (en) * 2019-07-31 2022-03-09 Murata Manufacturing Co Power supply output device
GB2586050B (en) * 2019-07-31 2021-11-10 Murata Manufacturing Co Power supply output device
US11270917B2 (en) * 2020-06-01 2022-03-08 Alibaba Group Holding Limited Scalable and flexible architectures for integrated circuit (IC) design and fabrication
CN112769402B (zh) * 2020-12-21 2024-05-17 中国航天科工集团八五一一研究所 基于TSV技术的X/Ku波段宽带变频组件
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
KR102443742B1 (ko) * 2021-02-08 2022-09-15 고려대학교 산학협력단 모놀리식 3d 집적 기술 기반 스크래치패드 메모리
US12308072B2 (en) * 2021-03-10 2025-05-20 Invention And Collaboration Laboratory Pte. Ltd. Integrated scaling and stretching platform for optimizing monolithic integration and/or heterogeneous integration in a single semiconductor die
US12230607B2 (en) * 2021-03-31 2025-02-18 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including power management die in a stack and methods of forming the same
KR102896801B1 (ko) * 2022-02-23 2025-12-05 한국과학기술원 3차원 집적형 고주파 혼성 회로 구조체 및 그의 제조 방법
KR20240033841A (ko) 2022-09-06 2024-03-13 삼성전자주식회사 반도체 장치
WO2025117577A1 (en) * 2023-12-01 2025-06-05 The Penn State Research Foundation Monolithic three-dimensional (3d) integration of two dimensional (2d) field effect transistors (fets)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046078A (en) * 1997-04-28 2000-04-04 Megamos Corp. Semiconductor device fabrication with reduced masking steps
JP2004165269A (ja) * 2002-11-11 2004-06-10 Canon Inc 積層形半導体装置
US7692448B2 (en) * 2007-09-12 2010-04-06 Neal Solomon Reprogrammable three dimensional field programmable gate arrays
TW201126694A (en) * 2010-01-29 2011-08-01 Nat Chip Implementation Ct Nat Applied Res Lab Three-dimensional SoC structure stacking by multiple chip modules

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131474A (ja) * 1984-11-30 1986-06-19 Agency Of Ind Science & Technol 積層型半導体装置
US20030015768A1 (en) 2001-07-23 2003-01-23 Motorola, Inc. Structure and method for microelectromechanical system (MEMS) devices integrated with other semiconductor structures
WO2003030252A2 (en) 2001-09-28 2003-04-10 Hrl Laboratories, Llc Process for producing interconnects
US7126214B2 (en) * 2001-12-05 2006-10-24 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
KR100569590B1 (ko) 2003-12-30 2006-04-10 매그나칩 반도체 유한회사 고주파 반도체 장치 및 그 제조방법
DE102006030267B4 (de) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US8136071B2 (en) 2007-09-12 2012-03-13 Neal Solomon Three dimensional integrated circuits and methods of fabrication
ATE512114T1 (de) * 2008-09-03 2011-06-15 St Microelectronics Tours Sas Dreidimensionale struktur mit sehr hoher dichte
US20110199116A1 (en) 2010-02-16 2011-08-18 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US7986042B2 (en) * 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8115511B2 (en) * 2009-04-14 2012-02-14 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8466610B2 (en) * 2009-05-14 2013-06-18 Sri International Low cost high efficiency transparent organic electrodes for organic optoelectronic devices
US8450779B2 (en) 2010-03-08 2013-05-28 International Business Machines Corporation Graphene based three-dimensional integrated circuit device
JP2012019018A (ja) * 2010-07-07 2012-01-26 Toshiba Corp 半導体装置及びその製造方法
CN102024782B (zh) * 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
EP2469597A3 (en) 2010-12-23 2016-06-29 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Multi-level integrated circuit, device and method for modeling multi-level integrated circuits
US8384215B2 (en) * 2010-12-30 2013-02-26 Industrial Technology Research Institute Wafer level molding structure
DE102011004581A1 (de) * 2011-02-23 2012-08-23 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Technik zur Reduzierung der plasmahervorgerufenen Ätzschäden während der Herstellung von Kontaktdurchführungen in Zwischenschichtdielektrika durch modifizierten HF-Leistungshochlauf
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
JP6019599B2 (ja) * 2011-03-31 2016-11-02 ソニー株式会社 半導体装置、および、その製造方法
WO2013052679A1 (en) 2011-10-04 2013-04-11 Qualcomm Incorporated Monolithic 3-d integration using graphene
US9496255B2 (en) * 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
JP5981711B2 (ja) * 2011-12-16 2016-08-31 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP2013215917A (ja) 2012-04-05 2013-10-24 Seiko Epson Corp 印刷装置、及び、印刷方法
CN103545275B (zh) * 2012-07-12 2016-02-17 中芯国际集成电路制造(上海)有限公司 硅通孔封装结构及形成方法
US8889491B2 (en) * 2013-01-28 2014-11-18 International Business Machines Corporation Method of forming electronic fuse line with modified cap
KR20140113024A (ko) * 2013-03-15 2014-09-24 에스케이하이닉스 주식회사 저항 변화 메모리 장치 및 그 구동방법
US9171608B2 (en) * 2013-03-15 2015-10-27 Qualcomm Incorporated Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
US9418985B2 (en) 2013-07-16 2016-08-16 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
US9070711B2 (en) * 2013-08-02 2015-06-30 Globalfoundries Inc. Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046078A (en) * 1997-04-28 2000-04-04 Megamos Corp. Semiconductor device fabrication with reduced masking steps
JP2004165269A (ja) * 2002-11-11 2004-06-10 Canon Inc 積層形半導体装置
US7692448B2 (en) * 2007-09-12 2010-04-06 Neal Solomon Reprogrammable three dimensional field programmable gate arrays
TW201126694A (en) * 2010-01-29 2011-08-01 Nat Chip Implementation Ct Nat Applied Res Lab Three-dimensional SoC structure stacking by multiple chip modules

Also Published As

Publication number Publication date
EP3022766A1 (en) 2016-05-25
CN105378918A (zh) 2016-03-02
CA2917586C (en) 2019-02-12
US20150022262A1 (en) 2015-01-22
KR101832330B1 (ko) 2018-02-26
JP2016529702A (ja) 2016-09-23
WO2015009614A1 (en) 2015-01-22
CN105378918B (zh) 2018-05-04
US9418985B2 (en) 2016-08-16
TW201513299A (zh) 2015-04-01
BR112016000868A2 (https=) 2017-07-25
CA2917586A1 (en) 2015-01-22
BR112016000868B1 (pt) 2022-08-16
KR20160032182A (ko) 2016-03-23
US20160351553A1 (en) 2016-12-01
US9583473B2 (en) 2017-02-28

Similar Documents

Publication Publication Date Title
TWI618222B (zh) 使用整塊三維積體電路技術之完整系統晶片
US11424195B2 (en) Microelectronic assemblies having front end under embedded radio frequency die
US11552055B2 (en) Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods
TW201943042A (zh) 於封裝基材中之積體電路結構
TWI880978B (zh) 具有電磁屏蔽之整合器件及其製造方法
KR20240076780A (ko) 백 엔드-오브-라인(beol) 구조에 추가 신호 경로들을 형성하기 위해 용도 변경된 시드층을 사용하는 반도체 다이 및 관련된 집적 회로(ic) 패키지들 및 제조 방법들
TW202133566A (zh) 阻抗匹配收發器
US20220028758A1 (en) Backside power distribution network (pdn) processing
US20080023824A1 (en) Double-sided die
CN105683864A (zh) 具有垂直存储器部件的单片式三维(3d)集成电路(ic)(3dic)
US20240162157A1 (en) Bumpless hybrid organic glass interposer
US20210249359A1 (en) Package with integrated structure
US20230299123A1 (en) Inductors for hybrid bonding interconnect architectures
US11832391B2 (en) Terminal connection routing and method the same
TW202207389A (zh) 具有嵌入絕緣層內的局部高密度佈線區域的封裝
TW202220153A (zh) 重分佈層連接
US20250219021A1 (en) Vertically embedded components in package substrates
US20240188212A1 (en) Package substrate architectures with improved cooling
TWI918705B (zh) 端子連接佈線
US20250300054A1 (en) Conformally plated through-vias in glass
US10892236B2 (en) Integrated circuit having a periphery of input/output cells

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees