BR112016000868B1 - Sistema-em-chip (soc) completo usando tecnologia de circuito integrado (ic) tridimensional (3d) (3dic) monolítico - Google Patents

Sistema-em-chip (soc) completo usando tecnologia de circuito integrado (ic) tridimensional (3d) (3dic) monolítico Download PDF

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BR112016000868B1
BR112016000868B1 BR112016000868-5A BR112016000868A BR112016000868B1 BR 112016000868 B1 BR112016000868 B1 BR 112016000868B1 BR 112016000868 A BR112016000868 A BR 112016000868A BR 112016000868 B1 BR112016000868 B1 BR 112016000868B1
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BR112016000868-5A
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BR112016000868A2 (https=
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Yang Du
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Qualcomm Incorporated
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
BR112016000868-5A 2013-07-16 2014-07-14 Sistema-em-chip (soc) completo usando tecnologia de circuito integrado (ic) tridimensional (3d) (3dic) monolítico BR112016000868B1 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361846648P 2013-07-16 2013-07-16
US61/846,648 2013-07-16
US14/013,399 2013-08-29
US14/013,399 US9418985B2 (en) 2013-07-16 2013-08-29 Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
PCT/US2014/046503 WO2015009614A1 (en) 2013-07-16 2014-07-14 Complete system-on-chip (soc) using monolithic three dimensional (3d) integrated circuit (ic) (3dic) technology

Publications (2)

Publication Number Publication Date
BR112016000868A2 BR112016000868A2 (https=) 2017-07-25
BR112016000868B1 true BR112016000868B1 (pt) 2022-08-16

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BR112016000868-5A BR112016000868B1 (pt) 2013-07-16 2014-07-14 Sistema-em-chip (soc) completo usando tecnologia de circuito integrado (ic) tridimensional (3d) (3dic) monolítico

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US (2) US9418985B2 (https=)
EP (1) EP3022766A1 (https=)
JP (1) JP2016529702A (https=)
KR (1) KR101832330B1 (https=)
CN (1) CN105378918B (https=)
BR (1) BR112016000868B1 (https=)
CA (1) CA2917586C (https=)
TW (1) TWI618222B (https=)
WO (1) WO2015009614A1 (https=)

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Also Published As

Publication number Publication date
EP3022766A1 (en) 2016-05-25
CN105378918A (zh) 2016-03-02
CA2917586C (en) 2019-02-12
US20150022262A1 (en) 2015-01-22
TWI618222B (zh) 2018-03-11
KR101832330B1 (ko) 2018-02-26
JP2016529702A (ja) 2016-09-23
WO2015009614A1 (en) 2015-01-22
CN105378918B (zh) 2018-05-04
US9418985B2 (en) 2016-08-16
TW201513299A (zh) 2015-04-01
BR112016000868A2 (https=) 2017-07-25
CA2917586A1 (en) 2015-01-22
KR20160032182A (ko) 2016-03-23
US20160351553A1 (en) 2016-12-01
US9583473B2 (en) 2017-02-28

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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