TWI616937B - 利用一氧化二氮作為氧氣來源，製作一個包括原子層結構之半導體裝置之方法 - Google Patents

利用一氧化二氮作為氧氣來源，製作一個包括原子層結構之半導體裝置之方法 Download PDF

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TWI616937B
TWI616937B TW105141224A TW105141224A TWI616937B TW I616937 B TWI616937 B TW I616937B TW 105141224 A TW105141224 A TW 105141224A TW 105141224 A TW105141224 A TW 105141224A TW I616937 B TWI616937 B TW I616937B
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史蒂芬生 羅勃
斯柯蒂 耐萊
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Abstract

一種用於製作半導體元件之方法可包括在一半導體處理室內，將複數個分隔結構形成在一半導體底材上，每一結構包含複數個堆疊之層群組。每一層群組可包含複數個堆疊之基底矽單層，其界定出一基底半導體部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層。此外，所述氧單層可使用N2 O作為氧源而形成。

Description

利用一氧化二氮作為氧氣來源，製作一個包括原子層結構之半導體裝置之方法
本發明一般而言與半導體領域有關，詳細而言，本發明與具有基於能帶工程之增強特性之半導體及其相關方法有關。
利用諸如增強電荷載子之遷移率（mobility）增進半導體元件性能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致性能劣退的無雜質區（impurity-free zones）。此等應變材料層在上部矽層中所造成的雙軸向應變（biaxial strain）會改變載子的遷移率，從而得以製作較高速與／或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變（tensile strain）。這樣，具有較小有效質量（effective mass）且已由施加於閘電極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其n通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層（monolayer）且含有一部分（fractional）或雙元（binary）半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射（alloy scattering）而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個能障區（barrier region）及夾於其間的一磊晶生長半導體薄層。每一能障區各係由厚度範圍大致在二至六個交疊之SiO2／Si單層所構成。能障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程（Applied Physics and Materials Science & Processing） pp. 391 – 402中，Tsu於一篇題為「矽質奈米結構元件中之現象」（Phenomena in silicon nanostructure devices）的文章中揭示了矽及氧之半導體-原子超晶格（semiconductor-atomic superlattice, SAS）。此矽／氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體（electroluminescence diode）結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種（adsorbed species） 及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1 nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊（Physics Review Letters），Vol. 89, No. 7 （2002年8月12日）中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」（Chemical Design of Direct-Gap Light-Emitting Silicon）的文章，更進一步地討論了Tsu的發光SAS結構。
已公開之Wang, Tsu及Lofgren等人的國際申請案WO 02/103,767 A1號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一能障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度（four orders of magnitude）。其絕緣層／能障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公開之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙 （aperiodic photonic band-gap, APBG）結構可應用於電子能帶間隙工程（electronic bandgap engineering）中。詳細而言，該申請案揭示，材料參數（material parameters），例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數（dielectric permittivity）或導磁係數（magnetic permeability），則被揭露亦有可能被設計於材料之中。
儘管在材料工程方面已付出相當大的努力來增加半導體元件中電荷載子的遷移率，但仍需要更大的改進。較大的遷移率可以增加元件速度及/或降低元件功耗。當遷移率較大時，即使元件特徵持續朝更小的方向改變，元件效能亦可獲得維持。
一種用於製作半導體元件之方法可包括在一半導體處理室內，將複數個分隔結構形成在一半導體底材上，每一結構包含複數個堆疊之層群組。每一層群組可包含複數個堆疊之基底矽單層，其界定出一基底半導體部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層。此外，所述氧單層可使用N2 O作為氧源而形成。
更詳細而言，所述複數個分隔結構可使用磊晶化學氣相沉積法(CVD)而形成。舉例而言，所述基底矽單層可在600℃至800℃範圍內的溫度下形成，更詳細而言，所述基底矽單層可在665℃至685℃範圍內的溫度下形成。
再舉例而言，所述氧單層可在500℃至750℃範圍內的溫度下形成。所述氧源之曝露時間可介於1與240秒之間，更詳細而言，所述氧源之曝露時間可介於，舉例而言，12與24秒之間，且所述氧源可包括具有少於2% N2 O之一氦源氣體。
所述方法可更包括在所述分隔結構之間形成淺溝槽隔絕（STI）區。更詳細而言，所述淺溝槽隔絕區係在形成所述分隔結構之前形成。此外，可在每一所述分隔結構上面形成各自的頂蓋半導體層。此外，形成所述頂蓋半導體層可包括在580℃至900℃範圍內的溫度下形成所述頂蓋半導體層。
茲參考本發明說明書所附圖式詳細說明本發明，圖式中所示者為本發明之實施方式。不過，本發明可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之實施方式。相反的，這些實施方式之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡，並向熟習本發明所屬技術領域者完整傳達本發明之範圍。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號（’）則用以標示替代實施方式中之類似元件。
以下實施例係關於在原子或分子等級控制半導體材料的性質，以在半導體元件內獲得更佳效能。此外，本發明與辨識、發明及使用更佳材料供半導體元件之導電路徑使用有關。
申請人之理論認為（但申請人並不欲受此理論所束縛），本說明書所述之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電洞使用了「導電性反有效質量張量」（conductivity reciprocal effective mass tensor）及：為電子之定義，且：為電洞之定義，其中f為費米-狄拉克分佈（Fermi-Dirac distribution），EF為費米能量（Fermi energy），T為溫度，E（k,n）為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區（Brillouin zone，B.Z.）內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量 （tensorial component）亦較大。申請人再度提出理論（但並不欲受此理論所束縛）認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子／電洞之導電性有效質量，便可用於分辨出較佳之材料。
較高的電荷載子遷移率可來自於電荷載子在平行方向上的導電性有效質量，低於原本會存在的電導性有效質量。前述的導電性有效質量可少於原本會發生的導電性有效質量的三分之二。當然，超晶格可更包括至少一種類型之導電性摻雜物在其中。
使用上述措施，可選定具有為特定目的而改進能帶結構之材料。一個示例就是用於半導體元件中通道區的超晶格25材料。以下參考圖2首先說明包含依照本發明的超晶格25之一半導體元件20。但熟習本發明所屬技術領域者應可理解，本說明書中所指出的材料可用於不同類型的半導體元件，例如分離式元件（discrete devices）及/或積體電路。半導體元件20示例性地包括一底材21，以及位於相鄰超晶格25間的複數個淺溝槽隔絕（STI）區。接著可在半導體元件20上實施進一步的處理，以產生各種半導體結構，例如在美國專利第6,897,472、6,993,222、7,202,494、7,432,524、7,586,165、7,612,366、7,659,539、7,781,827及 7,863,066號中所述者，這些專利均已轉讓予本受讓人，並在此透過引用將其全部內容併入本說明書。
申請人已辨識出可用於製作超晶格25之改進材料或結構及方法。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及／或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。
參考圖2及圖3，超晶格25之結構在原子或分子等級上受到控制，且可應用已知的原子或分子層沉積技術加以形成。該超晶格25包含複數個堆疊排列之層群組45a～45n，如圖3之示意剖視圖所示。
如圖所示，超晶格25之每一層群組45a～45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a ～46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖3中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。亦即，相鄰層群組45a～45n中相對的基底半導體單層46，係以化學方式鍵結在一起。以矽單層46舉例而言，層群組45a的上部或頂部單層中的部分矽原子，會與層群組45b的下部或底部單層中的矽原子共價鍵結。這讓晶格即便在非半導體單層（例如氧單層）存在的情況下，仍得以穿過層群組而延續。當然，在相鄰層群組45a～45n中相對的矽層46間，不會有完整或純粹的共價鍵結，因為各矽層中的部分矽原子會鍵合至非半導體原子（即本示例中的氧），熟習本發明所屬技術領域者應可理解。
在其他實施方式中，使用超過一個的此種單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成為主體，會是非半導體或半導體。亦即，一種材料（例如矽）之單一單層所顯現之特性，並不必然與形成為主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為（但申請人並不欲受此理論所束縛），能帶修改層50與相鄰之基底半導體部份46a～46n，可使該超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使該超晶格25具有一般之能帶結構。
本發明之理論亦認為，半導體元件，例如圖中所繪之MOSFET20，可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，該超晶格25可進一步具有對光電元件尤其有利之實質上之直接能帶間隙。
熟習本發明所屬技術領域者當可理解，MOSFET20的源極/汲極區22/26、23/27及閘極35可被認為是用於使電荷載子在相對於堆疊層群組45a～45n的平行方向上透過超晶格傳輸的區域。其他此類區域亦為本發明所考慮。
如圖所示，該超晶格25亦包含一上部層群組45n上面之一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部分46a～46n可包含由 IV 族半導體、 III-V 族半導體及 II-VI 族半導體所組成之群組中選定之一基底半導體。當然， IV 族半導體亦包含 IV-IV 族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層（monolayer）」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據之單層。舉例來說，參照圖3之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4／1重複結構。氧原子之可能位置僅有一半被佔據。
在其他實施方式及／或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為（但申請人並不欲受此理論所束縛），就一超晶格而言，例如矽／氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。但在其他實施方式中，亦可根據給定之應用而使用八層或更多層。圖3及圖4所示之矽／氧 4／1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子（就主體矽而言具等向性）之計算後導電性有效質量為0.26，而X方向上的4／1 矽／氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4／1 矽／氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先（directionally preferential）之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
該超晶格25之4／1 矽／氧實施方式之較低導電性有效質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，該超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖5說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3／1／5／1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽／氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖5中其他元件在此未提及者，係與前文參考圖3所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖6A-6C呈現應用密度功能理論（Density Functional Theory, DFT）計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」（scissors correction）加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖6A呈現主體矽 （以實線表示）及圖3-4之4／1 矽／氧超晶格25 （以虛線表示）兩者由迦碼點（G）計算出之能帶結構。圖中該些方向係指該4／1 矽／氧結構之單位晶格（unit cell）而非指矽之一般單位晶格，雖然圖中之方向（001）確實對應於一般矽單位晶格之方向（001），並因此而顯示出矽導帶最小值之預期位置。圖中方向（100）及方向（010）係對應於一般矽單位晶格之方向（110）及方向（-110）。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4／1 矽／氧結構之適當反晶格方向（reciprocal lattice directions）上表示。
由圖中可見，與主體矽相較，該4／1 矽／氧結構之導帶最小值係位於G點，而其價帶最小值則出現在方向（001）上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4／1 矽／氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾（perturbation）造成能帶分裂（band splitting）之故。
圖6B呈現主體矽（實線）及該4／1 矽／氧超晶格25 （虛線）兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向（100）上之增加曲率。
圖6C呈現主體矽（實線）及圖4之5／1／3／1 矽／氧超晶格25’ （虛線）兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5／1／3／1 矽／氧結構之對稱性，在 方向（100）及方向（010）上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向（001）上，導電性有效質量及遷移率可預期為等向性。請注意，在該5／1／3／1 矽／氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5／1／3／1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷（optical transition）之適當矩陣元素（matrix element）是區別直接及間接能帶間隙行為之另一指標。
以下另外參考圖1說明一種用於製作包含超晶格25之半導體元件20的方法。所述超晶格25可選擇性地形成在矽底材21上。舉例而言，底材21可為具有＜100＞定向之P型或N型單晶矽輕度摻雜之八吋晶圓，但其他合適底材亦可使用。
超晶格25的材料係選擇性地形成在底材21整個上表面的期望位置處，但在某些實施方式中可使用非選擇性製程。舉例而言，淺溝槽隔絕區22可形成在底材21上間隔開的位置處，以界定出要沉積超晶格25材料的期望位置。
從區塊100開始，在區塊101處，在一處理室中，通過連續的原子層沉積，將一個或多個基底半導體（此處為矽）單層46形成在底材21上的選定位置處。舉例而言，前述沉積可利用矽烷(silane)、二矽烷(disilane)、三矽烷(trisilane)或其他合適的沉積反應劑(deposition agent)在大約425至625℃的溫度範圍內，以及大約20至80 Torr的壓力範圍下進行。氮或氫可作為傳遞反應劑(delivery agent)，於大約20至40 SLM下進行。
在區塊102處，當特定群組中的所有矽單層46都已形成時，接著在區塊103處，可形成各別的氧單層，以使得氧單層被拘束在相鄰基底矽部分的晶格內，如前文所述。此外，一旦超晶格25的所有群組都已形成時，可選擇將一半導體（例如矽）頂蓋層52形成於其上（區塊105），如前文所述，這樣就說明性地總結了圖1的方法（區塊106）。作為示例，頂蓋層52可在580至900℃的溫度範圍內形成，更詳細而言，可在685至800℃的溫度範圍內形成。
在所繪示例中，氧單層係使用N2 O為氧源而形成。作為示例，所述氧源可包括具有少於2% N2 O之一氦源氣體，更詳細而言，所述氧源可包括具有大約1% N2 O之氦源氣體，但在不同實施方式中，亦可使用氦以外的其他惰性氣體源。所述氧單層可在500℃至750℃範圍內的溫度下形成，更詳細而言，可在650℃至700℃範圍內的溫度下形成。一般而言，當溫度降到低於650℃時，幾乎或完全沒有氧會結合，溫度高於700℃時，氧雖然會結合，但氧沉積後的矽生長可能會因為不同結合狀態開始支配的緣故而減少。這些結果描繪於圖7的圖表70，其係針對一單一晶圓處理室，從該圖表可看出，在示例實施方式（沒有N2 O分解）中，總劑量相對於溫度在接近650℃時變得無法重複，且在高於700℃時變得不安定（亦即鍵合至矽的氧有所改變）。在相同的單一晶圓處理實施方式中，示例性的氧源流量可在80至195 sccm的範圍內，且劑量時間可在1至240秒的範圍內，更詳細而言，可在12至24秒的範圍內，如圖8及圖9的圖表80及90分別所示。在圖表90中，可看出總劑量相對於時間（650℃及83 sccm）為線性。在此所示比例下，氧的總劑量會是1E15原子／平方公分，曝露時間則會減至3秒。
另參考圖10，一圖表110描繪在一單一晶圓室中製作矽／氧超晶格25之材料濃度相對於深度之曲線，在該單一晶圓室中，氧源為一氦氣流中大約1%之 N2 O，持續時間為12秒，流量為170 sccm，溫度為680℃。在所繪示例中，氧濃度以繪製線111表示，氮化矽濃度以繪製線112表示，碳-12濃度則以繪製線113表示。
一般而言，上述使用N2 O作為氧源之製程，對多晶圓處理以提供較佳均勻度尤其有用，因為N2 O的反應活性比O2 低。尤其，已發現N2 O的氧結合率（oxygen incorporation rate）比O2 低大約10倍。就多晶圓處理而言，較低反應活性表示溫度可稍微增加（保持在氧結合控制所必要的範圍內），且較長的曝露時間有助於均勻度。此外，由於N2 O反應活性較低的性質，在某些多晶圓室中，N2 O的氣相反應相對於H2 可減少，從而為晶圓帶來更佳的氣體輸送及改進的薄膜均勻度。此外，因為溫度較高，清洗時間可以減少而生產量可以增加。
另一方面，處理參數應如前文所述加以選定，以使製程仍具足夠反應活性以提供期望的氧覆蓋。更具體而言，在超晶格25的情況下，雖可以增加溫度以使氧源反應，但若溫度太高，氧可能在下一個矽單層降下前就脫附（desorb），或氧可能以不同組態（例如SiO2 ）鍵合，而使得矽的磊晶生長完全無法重新開始。
在得益於前述說明及相關圖式之教示下，熟習本發明所屬技術領域者將可想到許多修改例及其他實施方式。因此，應理解的是，本發明並不限於本說明書所揭露之特定實施方式，且修改例和實施例均落入後附請求項之範圍內。
20‧‧‧半導體元件
21‧‧‧底材
22‧‧‧淺溝槽隔絕區
25‧‧‧超晶格
25’‧‧‧超晶格
45a～45n‧‧‧層群組
45a’～45n’‧‧‧層群組
46‧‧‧基底半導體單層
46’‧‧‧基底半導體單層
46a～46n‧‧‧基底半導體部份
46a’～46n’‧‧‧基底半導體部份
50‧‧‧能帶修改層
50’‧‧‧能帶修改層
52‧‧‧頂蓋層
52’‧‧‧頂蓋層
70‧‧‧圖表
80‧‧‧圖表
90‧‧‧圖表
110‧‧‧圖表
111‧‧‧氧
112‧‧‧氮化矽
113‧‧‧碳-12
圖1為描繪依照本發明一種用於製作包含超晶格之半導體元件之方法的流程圖。
圖2為依照本發明所形成之一半導體元件之示意剖視圖，該半導體元件包含複數個選擇性形成之超晶格。
圖3為圖2所示超晶格之放大示意剖視圖。
圖4為圖2所示超晶格之一部分之透視示意原子圖。
圖5為可用於圖2所示元件之一超晶格之另一實施方式之放大示意剖視圖。
圖6A為習知技術之主體矽及圖2-4所示之4／1 矽／氧超晶格兩者從迦碼點（G）計算所得能帶結構之圖。
圖6B為習知技術之主體矽及圖2-4所示之4／1 矽／氧超晶格兩者從Z點計算所得能帶結構之圖。
圖6C為習知技術之主體矽及圖5所示之5／1／3／1 矽／氧超晶格兩者從G點與Z點計算所得能帶結構之圖。
圖7為圖1使用N2 O作為氧源製作超晶格結構之方法之一示例實施方式中劑量相對於溫度之圖表。
圖8為圖1使用N2 O作為氧源製作超晶格結構之方法之示例實施方式中劑量相對於流量之圖表。
圖9為圖1使用N2 O作為氧源製作超晶格結構之方法之示例實施方式中劑量相對於時間之圖表。
圖10為圖1使用N2 O作為氧源製作超晶格結構之方法之示例實施方式中材料濃度相對於深度之圖表。
如圖所示

Claims (25)

  1. 一種用於製作半導體元件之方法，該方法包括：在一半導體處理室內，將複數個分隔結構形成在一半導體底材上，每一結構包含複數個堆疊之層群組，且每一層群組包含複數個堆疊之基底矽單層，其界定出一基底半導體部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層；其中所述氧單層係使用N2O作為氧源而形成。
  2. 如申請專利範圍第1項之方法，其中形成所述複數個分隔結構包括使用磊晶化學氣相沉積法(CVD)形成所述複數個分隔結構。
  3. 如申請專利範圍第1項之方法，其中所述基底矽單層係在600℃至800℃範圍內的溫度下形成。
  4. 如申請專利範圍第3項之方法，其中所述基底矽單層係在665℃至685℃範圍內的溫度下形成。
  5. 如申請專利範圍第1項之方法，其中所述氧單層係在500℃至750℃範圍內的溫度下形成。
  6. 如申請專利範圍第1項之方法，其中所述氧源之曝露時間係介於1與240秒之間。
  7. 如申請專利範圍第1項之方法，其中所述氧源包括具有少於2% N2O之一氦源氣體。
  8. 如申請專利範圍第1項之方法，其更包括在所述分隔結構之間形成淺溝槽隔絕(STI)區。
  9. 如申請專利範圍第8項之方法，其中所述淺溝槽隔絕區係在形成所述分隔結構之前形成。
  10. 如申請專利範圍第1項之方法，其更包括在每一所述分隔結構上面形成各自的頂蓋半導體層。
  11. 如申請專利範圍第10項之方法，其中形成所述頂蓋半導體層包括在580℃至900℃範圍內的溫度下形成所述頂蓋半導體層。
  12. 一種用於製作半導體元件之方法，該方法包括：使用磊晶化學氣相沉積法在一半導體處理室內將複數個分隔結構形成在一半導體底材上，相鄰的結構之間具有淺溝槽隔絕(STI)區，每一結構包含複數個堆疊之層群組，且每一層群組包含複數個堆疊之基底矽單層，其界定出一基底半導體部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層；其中所述氧單層係使用N2O作為氧源而形成。
  13. 如申請專利範圍第12項之方法，其中所述基底矽單層係在600℃至800℃範圍內的溫度下形成。
  14. 如申請專利範圍第13項之方法，其中所述基底矽單層係在665℃至685℃範圍內的溫度下形成。
  15. 如申請專利範圍第12項之方法，其中所述氧單層係在500℃至750℃範圍內的溫度下形成。
  16. 如申請專利範圍第12項之方法，其中所述氧源之曝露時間係介於1與240秒之間。
  17. 如申請專利範圍第12項之方法，其中所述氧源包括具有少於2% N2O之一氦源氣體。
  18. 如申請專利範圍第12項之方法，其中所述淺溝槽隔絕區係在形成所述分隔結構之前形成。
  19. 如申請專利範圍第12項之方法，其更包括在每一所述分隔結構上面形成各自的頂蓋半導體層。
  20. 如申請專利範圍第12項之方法，其中形成所述頂蓋半導體層包括在580℃至900℃範圍內的溫度下形成所述頂蓋半導體層。
  21. 一種用於製作半導體元件之方法，該方法包括：在一半導體處理室內，將複數個分隔結構形成在一半導體底材上，每一結構包含複數個堆疊之層群組，且每一層群組包含複數個堆疊之基底矽單層，其界定出一基底半導體部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層；其中所述氧單層係使用N2O作為氧源在500℃至750℃範圍內的溫度下形成，且其中所述基底矽單層係在600℃至800℃範圍內的溫度下形成。
  22. 如申請專利範圍第21項之方法，其中形成所述複數個分隔結構包括使用磊晶化學氣相沉積法(CVD)形成所述複數個分隔結構。
  23. 如申請專利範圍第21項之方法，其中所述基底矽單層係在665℃至685℃範圍內的溫度下形成。
  24. 如申請專利範圍第21項之方法，其中所述氧源之曝露時間係介於1與240秒之間。
  25. 如申請專利範圍第21項之方法，其中所述氧源包括具有少於2% N2O之一氦源氣體。
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