TWI694613B - 包含垂直集成的光學與電子元件且包含超晶格之半導體元件及方法 - Google Patents

包含垂直集成的光學與電子元件且包含超晶格之半導體元件及方法 Download PDF

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TWI694613B
TWI694613B TW108112667A TW108112667A TWI694613B TW I694613 B TWI694613 B TW I694613B TW 108112667 A TW108112667 A TW 108112667A TW 108112667 A TW108112667 A TW 108112667A TW I694613 B TWI694613 B TW I694613B
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superlattice
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羅勃約翰 史蒂芬生
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美商安托梅拉公司
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Abstract

一種半導體元件，其可包含其上設有複數個波導之一底材，以及上覆於該底材及該些波導之一超晶格。該超晶格可包含堆疊之層群組，每一層群組包含堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包括設置在該超晶格上之一主動元件層，其包含至少一主動半導體元件。

Description

包含垂直集成的光學與電子元件且包含超晶格之半導體元件及方法
本發明與半導體領域有關，詳細而言，本發明涉及光學半導體元件及其相關方法。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件效能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致效能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與／或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其N型通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部份(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個阻障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一阻障區各係由厚度範圍大致在二至六個交疊之SiO2／Si單層所構成。阻障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing) pp. 391 – 402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice, SAS)。此矽／氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species) 及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1 nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol. 89, No. 7 (2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
授予Wang等人的美國專利第6,376,337號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一阻障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層／阻障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公開之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙 (aperiodic photonic band-gap, APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
除此之外，授予Wang等人的美國專利第6,376,337號揭示一種用於製作半導體元件絕緣或阻障層之方法，其包括在矽底材上沉積一層矽及至少一另外元素，使該沉積層實質上沒有缺陷，如此實質上無缺陷的磊晶矽便能沉積於該沉積層上。作為替代方案，一或多個元素構成之一單層，較佳者為包括氧元素，在矽底材上被吸收。夾在磊晶矽之間的複數絕緣層，形成阻障複合體。
儘管已有上述方法存在，但在某些應用中使用先進的半導體處理技術可能需要進一步的增強，這些應用包含涉及光學元件之應用。一種用於製作包含光學構件之集成電路之方法揭露於Mears等人的美國專利案第7,109,052號，其已讓與本發明申請人且其全部內容茲此併入成為本說明書之一部。此方法包含形成至少一主動光學元件及與其耦合之一波導。該波導可包含一超晶格，其包含複數個堆疊之層群組。該超晶格之每一層群組可包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份及其上之一能帶修改層。該能帶修改層可包含至少一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。
一種半導體元件，其可包含一底材，其上設有複數個波導，及上覆於該底材及該些波導之一超晶格。該超晶格可包含複數個堆疊之層群組，其中每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包括設置在該超晶格上之一主動元件層，其包含至少一主動半導體元件。
作為示例，該底材可包含一絕緣體上半導體(SOI)底材。該半導體元件可更包括該超晶格內的複數個光學調變器區(optical modulator regions)，以及穿過該主動元件層延伸至該些光學調變器區之通孔。此外，該些光學調變器區可包含一摻雜物。
在一示例性實施例中，該至少一主動光學元件可包含至少一金氧半導體場效電晶體(MOSFET)。作為示例，該基底半導體單層可包含矽，而該至少一非半導體單層可包含氧。
一種用於製作一半導體元件之方法，其可包含在一底材上形成複數個波導，及形成上覆於該底材及該些波導之一超晶格。該超晶格可包含複數個堆疊之層群組，其中每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該方法可更包括形成設置在該超晶格上之一主動元件層，其包含至少一主動半導體元件。
茲參考說明書所附圖式詳細說明示例性實施例，圖式中所示者為示例性實施例。不過，實施例可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之特定示例。相反的，這些實施例之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)則用以標示不同實施方式中之類似元件。
一般而言，本發明係關於透過使用改良半導體超晶格，在平面式及垂直式半導體元件中形成改良的結構。在本說明書中，經改良的半導體超晶格亦被稱為「MST」層或「MST技術」。
詳言之，MST技術涉及進階的半導體材料，例如下文將進一步說明之超晶格25。申請人之理論認為(但申請人並不欲受此理論所束縛)，本說明書所述之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)
Figure 02_image001
及
Figure 02_image003
：
Figure 02_image005
為電子之定義，且：
Figure 02_image007
為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量 (tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所束縛)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量(conductivity effective mass)。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子／電洞之導電性有效質量，便可用於分辨出較佳之材料。
申請人已辨識出可用於半導體元件之改進材料或結構。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及／或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。這些結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及／或鐵電特性，下文將進一步討論之。
參考圖1及圖2，所述材料或結構是超晶格25的形式，其結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。超晶格25包含複數個堆疊排列之層群組45a～45n，如圖1之概要剖視圖所示。
如圖所示，超晶格25之每一層群組45a～45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a～46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖1中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格內」一語，係指來自相對之基底半導體部份46a～46n之至少一些半導體原子，透過該些相對基底半導體部份間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部份46a～46n上面之非半導體材料之量而成為可能，這樣，可用之半導體鍵結位置便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論之。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時，新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位置。
在其他實施方式中，使用超過一個此種非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，能帶修改層50與相鄰之基底半導體部份46a～46n，可使超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為超晶格25垂直上下方多個層之間之摻雜物及／或材料擴散之阻擋。因此，這些特性可有利地允許超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進裝置行動性，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，超晶格25可進一步具有對諸如光電元件等尤其有利之實質上之直接能帶間隙。
超晶格25亦可在一上部層群組45n上面包含一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部份46a～46n可包含由 IV 族半導體、 III-V 族半導體及 II-VI 族半導體所組成之群組中選定之一基底半導體。當然， IV 族半導體亦包含 IV-IV 族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據之單層(亦即非完全或低於100%之涵蓋範圍)。舉例來說，參照圖15之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4／1重複結構。氧原子之可能位置僅有一半被佔據。
在其他實施方式及／或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，就一超晶格而言，例如矽／氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。圖1及圖2所示之矽／氧 4／1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4／1 矽／氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4／1 矽／氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
超晶格25之4／1 矽／氧實施方式之較低導電性有效質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3／1／5／1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽／氧之此種超晶格25’ 而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖4A-4C呈現使用密度功能理論(Density Functional Theory, DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖4A呈現主體矽 (以實線表示)及圖1之4／1 矽／氧超晶格25 (以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4／1 矽／氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然圖中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4／1 矽／氧結構之適當反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4／1 矽／氧結構之導帶最小值係位於G點，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4／1 矽／氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖4B呈現主體矽(實線)及該4／1 矽／氧超晶格25 (虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖4C呈現主體矽(實線)及圖3之5／1／3／1 矽／氧超晶格25’ (虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5／1／3／1 矽／氧結構之對稱性，在 方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5／1／3／1 矽／氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5／1／3／1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
應用上述教示，吾人可挑選出具有更佳能帶結構的材料，以滿足特定用途。現在參考圖5，例如3D光子／電子半導體元件60中的超晶格25材料即為一例。作為背景說明，極大型集成電路(Ultra Large Scale Integration, ULSI)晶片中的矽表面區通常很昂貴，因此不斷在尋求方法以提升晶圓上的元件密度。此外，與以毫米為單位測量作用長度(interaction length)的最新集成電路(IC)相較，光學構件的尺寸通常較大。能夠在單一晶片上垂直堆疊光子和IC元件，是降低成本及增加晶片上每個區域的功能的一種方法。
植氧分離(SIMOX)技術已被用來將MOSFET元件堆疊至光學波導上方。詳見，舉例而言，Appl.Phys.Lett 88, 121108 (2006)。然而，所述SIMOX方法會造成大量缺陷，從而導致MOSFET的元件特性劣化。重要的是，對於次臨界閘極電壓(sub-threshold gate voltage)，源極-汲極漏電流(source-drain leakage current)不為零。
在圖示之實施例中，本發明有利地使用超晶格材料25作為用於限制光學波導的低折射率(index of refraction)材料，並用於產生高品質的磊晶矽主動元件層61，從而使高品質MOSFET元件62堆疊在光學波導及／或光學元件上。參考圖6A至圖6E說明一種用於製作半導體元件60之方法，如圖所示，該半導體元件透過標準圖案化及蝕刻製程而在一SOI晶圓或底材63上包含一埋置光學元件層或晶片70(波導、分離器、光學發射器／接收器等可界定於其中)。
如圖所示，該SOI底材63包含一底部半導體層64(例如矽)、位於該底部半導體層上之一絕緣層65(例如二氧化矽)，及位於該絕緣層上之一上部半導體層66(例如矽)。將波導／波導溝槽67蝕刻至SOI晶圓63上的半導體層66內之後(圖6A至6B)，生長一相對厚的超晶格25在上部半導體層上(圖6C)，接著植入光學調變器區68等等，並進行化學機械研磨／平坦化(CMP)(圖6D)。應注意的是，該植入步驟在某些實施例中可視需要選擇在稍後的時間進行。
接著生長一磊晶半導體層61(例如矽)(圖6E)以覆蓋光學元件層70並為接下來的CMOS製程提供主動元件層，以在埋置光學晶片上方形成IC(此處為MOSFET 62)、接點通孔等，熟習本發明所屬技術領域者當可理解。此後，可蝕刻深導電通孔71，以在諸如光學元件層70中為光學調變器67等等提供接點。在圖示之實施例中，隔離區72(例如淺溝槽隔離(STI)氧化區)將主動元件層61中的電子元件(此處為MOSFET 62)隔開。此外，如圖所示，每一MOSFET 62包含源極與汲極區73、74(其分別具有金屬／矽化物接點75、76)及一閘極75，其如圖所示包含一閘極絕緣體77、閘電極78、金屬／矽化物接點79及側壁間隔物80。然而，應注意的是，其他FET組構及其他電氣／電子元件亦可用於不同的實施例中。
在某些實施例中，亦可有利地使用超晶格層25以製作底層低折射率區，從而無需使用SOI底材63而可使用標準半導體(例如矽)底材，其具有可作為光學隔離區使用之第一超晶格層，熟習本發明所屬技術領域者當可理解。使用本發明超晶格層25堆疊元件可有利地使頂部矽層的品質優於以習知技術(例如SIMOX)所製作之矽。如此將產生高品質MOSFET元件或其他元件堆疊在光學元件上，而非如習知技術那樣產生相對低品質的頂部矽層，從而使相對低品質的MOSFET元件堆疊在光學元件上。
熟習本發明所屬技術領域者將可受益於本說明書揭示之內容及所附圖式而構思出各種修改例及其他實施方式。因此，應了解的是，本發明不限於本說明書所述之示例性實施方式，且相關修改及其他實施方式均落入以下申請專利範圍所界定之範疇。
21、21’‧‧‧底材25、25’‧‧‧超晶格45a～45n、45a’～45n’‧‧‧層群組46、46’‧‧‧基底半導體單層46a～46n、46a’～46n’‧‧‧基底半導體部份50、50’‧‧‧能帶修改層52、52’‧‧‧頂蓋層60‧‧‧半導體元件61‧‧‧主動元件層62‧‧‧MOSFET63‧‧‧SOI晶圓或底材64‧‧‧底部半導體層65‧‧‧絕緣層66‧‧‧上部半導體層67‧‧‧波導68‧‧‧光學調變器區70‧‧‧光學元件層71‧‧‧深導電通孔72‧‧‧隔離區73、74‧‧‧源極與汲極區75、76、79‧‧‧金屬／矽化物接點77‧‧‧閘極絕緣體78‧‧‧閘電極80‧‧‧側壁間隔物
圖1為依照本發明用於半導體元件之超晶格之放大概要剖視圖。
圖2為圖1所示超晶格之一部份之透視示意原子圖。
圖3為依照本發明之超晶格另一實施例之放大概要剖視圖。
圖4A為習知技術之主體矽及圖1-2所示之4／1 矽／氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖4B為習知技術之主體矽及圖1-2所示之4／1 矽／氧超晶格兩者從Z點計算所得能帶結構之圖。
圖4C為習知技術之主體矽及圖3所示之5／1／3／1 矽／氧超晶格兩者從G點與Z點計算所得能帶結構之圖。
圖5為堆疊在一光學元件上且包含根據一示例性實施例之超晶格之MOSFET之示意剖視圖。
圖6A至圖6E為繪示一種用於製作圖5元件之方法之一系列示意剖視圖。
25‧‧‧超晶格
60‧‧‧半導體元件
61‧‧‧主動元件層
62‧‧‧MOSFET
63‧‧‧SOI晶圓或底材
64‧‧‧底部半導體層
65‧‧‧絕緣層
67‧‧‧波導
68‧‧‧光學調變器區
70‧‧‧光學元件層
71‧‧‧深導電通孔
72‧‧‧隔離區
73、74‧‧‧源極與汲極區
75、76、79‧‧‧金屬/矽化物接點
77‧‧‧閘極絕緣體
78‧‧‧閘電極
80‧‧‧側壁間隔物

Claims (23)

  1. 一種半導體元件，其包括： 一底材，其上設有複數個波導； 上覆於該底材及該些波導之一超晶格，該超晶格包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層；及 該超晶格上一主動元件層，其包含至少一主動半導體元件。
  2. 如申請專利範圍第1項之半導體元件，其中該底材包含一絕緣體上半導體(SOI)底材。
  3. 如申請專利範圍第1項之半導體元件，其更包括該超晶格內的複數個光學調變器區。
  4. 如申請專利範圍第3項之半導體元件，其更包括穿過該主動元件層延伸至該些光學調變器區之通孔。
  5. 如申請專利範圍第3項之半導體元件，其中該些光學調變器區包含一摻雜物。
  6. 如申請專利範圍第1項之半導體元件，其中該至少一主動光學元件包含至少一金氧半導體場效電晶體(MOSFET)。
  7. 如申請專利範圍第1項之半導體元件，其中該些基底半導體單層包含矽。
  8. 如申請專利範圍第1項之半導體元件，其中該至少一非半導體單層包含氧。
  9. 一種半導體元件，其包括： 一絕緣體上半導體(SOI)底材，其上設有複數個波導； 上覆於該SOI底材及該些波導之一超晶格，該超晶格包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層； 該超晶格內的複數個光學調變器區；及 該超晶格上一主動元件層，其包含至少一主動半導體元件。
  10. 如申請專利範圍第9項之半導體元件，其更包括穿過該主動元件層延伸至該些光學調變器區之通孔。
  11. 如申請專利範圍第9項之半導體元件，其中該些光學調變器區包含一摻雜物。
  12. 如申請專利範圍第9項之半導體元件，其中該至少一主動光學元件包含至少一金氧半導體場效電晶體(MOSFET)。
  13. 如申請專利範圍第9項之半導體元件，其中該些基底半導體單層包含矽。
  14. 如申請專利範圍第9項之半導體元件，其中該至少一非半導體單層包含氧。
  15. 一種用於製作一半導體元件之方法，其包括： 在一底材上形成複數個波導； 形成上覆於該底材及該些波導之一超晶格，該超晶格包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層；及 形成該超晶格上一主動元件層，其包含至少一主動半導體元件。
  16. 如申請專利範圍第15項之方法，其中該底材包含一絕緣體上半導體(SOI)底材。
  17. 如申請專利範圍第15項之方法，其更包括在該超晶格內形成複數個光學調變器區。
  18. 如申請專利範圍第17項之方法，其更包括形成通孔使其穿過該主動元件層延伸至該些光學調變器區。
  19. 如申請專利範圍第17項之方法，其更包括在形成該些光學調變器區之後平坦化該超晶格層。
  20. 如申請專利範圍第17項之方法，其中形成該些光學調變器區包括植入一摻雜物以界定出該些光學調變器區。
  21. 如申請專利範圍第15項之方法，其中該至少一主動半導體元件包含至少一金氧半導體場效電晶體(MOSFET)。
  22. 如申請專利範圍第15項之方法，其中該些基底半導體單層包含矽。
  23. 如申請專利範圍第15項之方法，其中該至少一非半導體單層包含氧。
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