CN107771355B - 具有超晶格和在不同深度处的穿通停止(pts)层的半导体装置和相关方法 - Google Patents

具有超晶格和在不同深度处的穿通停止(pts)层的半导体装置和相关方法 Download PDF

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CN107771355B
CN107771355B CN201680036091.1A CN201680036091A CN107771355B CN 107771355 B CN107771355 B CN 107771355B CN 201680036091 A CN201680036091 A CN 201680036091A CN 107771355 B CN107771355 B CN 107771355B
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semiconductor
superlattice
channel
layer
pts
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CN107771355A (zh
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R·J·梅尔斯
武内英树
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Atomera Inc
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Atomera Inc
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

半导体装置可以包括半导体衬底和具有第一操作电压的第一晶体管。每个第一晶体管可以包括半导体衬底中的第一穿通停止(PTS)层和第一沟道，并且第一PTS层可以在第一沟道下方的第一深度处。该半导体装置可以进一步包括具有高于第一操作电压的第二操作电压的第二晶体管。每个第二晶体管可以包括半导体衬底中的第二PTS层和第二沟道，并且第二PTS层在第二沟道下方的大于第一深度的第二深度处。此外，第一沟道可以包括第一超晶格并且第二沟道可以包括第二超晶格。

Description

具有超晶格和在不同深度处的穿通停止(PTS)层的半导体装 置和相关方法
技术领域
本公开总体涉及半导体装置，并且更具体地，涉及半导体装置的增强材料和掺杂剂注入技术。
背景技术
已经提出了结构和技术来增强半导体装置的性能，比如通过增强电荷载流子的迁移率来增强半导体装置的性能。例如，Currie等人的美国专利申请No.2003/0057416公开了硅的应变材料层、硅-锗以及松弛硅并且还包括无杂质区(否则将会引起性能退化)。上硅层中产生的双轴应变改变载流子迁移率，从而允许较高速和/或较低功耗装置。Fitzgerald等人的已公布的美国专利申请No.2003/0034529公开了同样基于类似应变硅技术的CMOS反相器。
Takagi的美国专利No.6,472,685B2公开了一种半导体装置，该半导体装置包括夹于硅层间的硅碳层，以使得第二硅层的导带和价带受到拉伸应变。具有较小的有效质量并且已被施加到栅极电极的电场感应的电子被限制在第二硅层中，因此，可以肯定n沟道MOSFET具有更高的迁移率。
Ishibashi等人的美国专利No.4,937,204公开了一种超晶格，其中多层(少于8个单层，且包含部分或双金属半导体层或二元化合物半导体层)交替地并且外延地生长。主电流流动方向垂直于超晶格层。
Wang等人的美国专利No.5,357,119公开了具有通过减少超晶格中的合金散射获得的较高迁移率的Si-Ge短周期超晶格。按照这些原则，Candelaria的美国专利No.5,683,934公开了包括沟道层的增强迁移率MOSFET，该沟道层包含硅和在硅晶格中以一定比例替代性出现的第二材料的合金，这将沟道层置于拉伸应力下。
Tsu的美国专利No.5,216,262公开了包括两个势垒区和夹于势垒之间的薄外延生长的半导体层的量子阱结构。每个势垒区包括厚度通常在2到6个单层范围内的交替的SiO2/Si层。硅的更厚部分夹于势垒之间。
同样Tsu于2000年9月6日在Appllied Physics and Materials Science&Processing的第391-402页在线发表的题目为“Phenomena in silicon nanostructuredevices”的文章公开了硅和氧的半导体-原子超晶格(SAS)。Si/O超晶格被公开为在硅量子以及发光装置中是有用的。具体地，构建和测试了绿色电致发光二极管结构。二极管结构中电流流动是垂直的，即垂直于SAS层。公开的SAS可以包括由吸附物(诸如氧原子以及CO分子)分开的半导体层。在超过吸收的氧单层的硅生长被描述为具有相当低缺陷密度的外延。一个SAS结构包括1.1nm厚的硅部分(即，大约8个硅原子层)以及具有两倍于此硅厚度的另一个结构。Luo等人在Physics Review Letters,Vol.89,No.7(2002年8月12日)发表的题目为“Chemical Design of Direct-Gap Light-Emitting Silicon”的文章进一步讨论了Tsu的发光SAS结构。
Wang、Tsu和Lofgren的已公开的国际申请WO 02/103,767A1公开了薄硅和氧、碳、氮、磷、锑、砷或者氢的势垒构成块，从而使垂直地流过晶格的电流降低了超过四个量级。绝缘层/势垒层允许低缺陷外延硅接着沉积到绝缘层。
Mears等人的已公开的英国专利申请2,347,520公开了非周期性光子带隙(APBG)结构的原理可能适合于电子带隙工程。具体地，该申请公开了可以修整材料参数(例如，能带极小值的位置、有效质量等等)来产生具有期望的能带结构特性的新非周期性材料。还公开了可以对材料进行设计的其它参数(诸如电导率、热导率和介电常数或者磁导率)。
尽管由这些结构提供了优点，但是用于在各种半导体装置中诸如相对于先进的半导体结构的掺杂集成先进半导体材料的进一步的发展可能是希望的。掺杂剂注入很长时间是半导体装置的重要技术。已经提出和阐明了用于在低温量子输运的掺杂所谓的确定性掺杂(参见例如Shinada et al.,Nature 437,1128(2005))的一种方法。然而，确定性掺杂的一个潜在问题是掺杂剂的后续扩散，使得室温稳定性非常具有挑战。
发明内容
半导体装置可以包括半导体衬底和具有第一操作电压的多个第一晶体管。每个第一晶体管可以包括半导体衬底中的第一穿通停止(PTS)层和第一沟道，并且第一PTS层可以在第一沟道下方的第一深度处。半导体装置可以进一步包括具有高于第一操作电压的第二操作电压的多个第二晶体管。每个第二晶体管可以包括半导体衬底中的第二PTS层和第二沟道，并且第二PTS层可以在第二沟道下方的大于第一深度的第二深度处。此外，第一沟道可以包括第一超晶格并且第二沟道可以包括第二超晶格。
更具体地，第一超晶格和第二超晶格可以各自包括相应的多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。举例来说，每个基础半导体部分可以包含硅，并且至少一个非半导体层可以包含氧。另外，来自相对的基础半导体部分的至少一些半导体原子通过其间的非半导体层可以被化学地束缚在一起。
根据示例实施例，多个第一晶体管可以包括多个核心晶体管，并且多个第二晶体管可以包括多个输入/输出晶体管。第一穿通停止层和第二穿通停止层可以各自包括高度掺杂的半导体层。
在示例实施例中，第一沟道可以包括半导体衬底在第一超晶格下方的相邻第一部分并且第二沟道可以包括半导体衬底在第二超晶格下方的相邻第二部分。此外，第一晶体管中的每一个可以包括覆于第一沟道上的第一栅极和在第一栅极的相对侧上的间隔开的第一源极区和第一漏极区。第二晶体管中的每一个可以包括覆于第二沟道上的第二栅极和在第二栅极的相对侧上的间隔开的第二源极区和第二漏极区。
还提供了制造半导体装置的相关方法。该方法可以包括形成具有第一操作电压的多个第一晶体管，每个第一晶体管包括半导体衬底中的第一穿通停止(PTS)层和第一沟道。第一PTS层可以在第一沟道下方的第一深度处，并且第一沟道可以包括第一超晶格。该方法还可以包括形成具有高于第一操作电压的第二操作电压的多个第二晶体管，每个第二晶体管包括半导体衬底中的第二PTS层和第二沟道。第二PTS层可以在第二沟道下方的大于第一深度的第二深度处，并且第二沟道可以包括第二超晶格。
附图说明
图1是根据本发明的用于在半导体装置中使用的超晶格的高倍放大的示意性截面图。
图2是图1中示出的超晶格的一部分的立体示意性原子图。
图3是根据本发明的超晶格的另一个实施例的高倍放大的示意性截面图。
图4A是对现有技术中的体硅和图1-图2中示出的4/1Si/O超晶格两者从伽马点(G)计算的能带结构的图示。
图4B是对现有技术中的体硅和图1-图2中示出的4/1Si/O超晶格两者从Z点计算的能带结构的图示。
图4C是对现有技术中的体硅和图3中示出的5/1/3/1Si/O超晶格两者从伽马点和Z点两者计算的能带结构的图示。
图5是根据示例实施例的其中超晶格层用于将穿通停止(PTS)层约束在不同深度处的半导体装置的示意性框图。
图6是根据示例实施例的其中多个超晶格层用于将晕圈注入峰值浓度限制在多个超晶格层之间的半导体装置的示意性框图。
图7是图6的半导体装置的示例实施方式的仿真晕圈注入浓度的图示。
具体实施方式
现在将参照附图在下文中更完整地描述本公开，附图中示出了示例实施例。然而，可以基于本文阐明的教导来实现多个不同的形式，并且本公开不应该被解释为局限于所提供的具体示例实施例。相反，提供这些实施例是为了使得本公开将是透彻且完整的，并且将向本领域技术人员完整地传达公开的概念。同样的附图标记始终指代同样的要素，并且主要符号被用来指示不同实施例中的类似要素。
申请人从理论上阐明(但不希望束缚于此)本文描述的特定超晶格降低了电荷载流子的有效质量，并且这从而导致更高的电荷载流子迁移率。在文献中，用各种定义来描述有效质量。作为有效质量的改进的测量，申请人分别针对电子和空穴使用“电导率倒数有效质量张量(conductivity reciprocal effective mass tensor)”Me -1和Mh -1，对于电子定义为：
Figure BDA0001515316490000051
以及对于空穴定义为：
Figure BDA0001515316490000052
其中f是费米狄拉克分布，EF是费米能级，T是温度，E(k，n)是电子在与波矢k和第n个能带对应的态中的能量，下标i和j指的是笛卡尔坐标系x、y、z，在布里渊区(B.Z.)进行积分，并且分别对于电子和空穴的能量在费米能级以上或以下的能带进行求和。
申请人对电导率倒数有效质量张量的定义使得材料的电导率的张量分量比电导率倒数有效质量张量的相应分量的较大值更大。再次，申请人从理论上阐明(但不希望束缚于此)本文描述的超晶格设置电导率倒数有效质量张量的值以便增强材料的导电性质(诸如一般针对电荷载流子输运的优选方向)。适当张量参数元(appropriate tensorelement)的逆也被称为电导率有效质量。换句话说，为了表征半导体材料结构，使用如上描述并在预期的载流子输运方向上计算的电子/空穴的电导率有效质量来区分改进的材料。
申请人已经确认了用于在半导体装置中使用的改进的材料或结构。更具体地，申请人已经确认了具有电子和/或空穴的适当的电导率有效质量比硅的相应值小得多的能带结构的材料或结构。除这些结构的增强的迁移率特性之外，如将会在下面进一步讨论的，还可以以它们提供压电、热电、和/或铁电的性质这样的方式来形成或使用它们，这些性质对于用在很多不同类型的装置中是有益的。
现在参照图1和图2，材料或结构以超晶格25的形式，超晶格25的结构被在原子或分子层面控制，并且可以使用已知的原子或分子层沉积的技术来形成。超晶格25包括以堆叠关系布置的多个层组45a-45n，也许具体参照图1的示意性截面图能最好理解。
超晶格25的每个层组45a-45n例示性地包括限定相应的基础半导体部分46a-46n的多个堆叠的基础半导体单层46和其上的能带修改层50。为了清晰地例示，通过图1中的点画指示能带修改层50。
能带修改层50例示性地包括约束在相邻的基础半导体部分的晶格内的一个非半导体单层。“约束在相邻的基础半导体部分的晶格内”意味着：来自相对的基础半导体部分46a-46n的至少一些半导体原子通过其间的非半导体单层50被化学地束缚在一起，如图2所示。如下面将进一步讨论的，一般来说，通过原子层沉积技术来控制沉积在半导体部分46a-46n上的非半导体材料的量以使得不是所有可用的半导体键合位点(即，小于全部或100％覆盖)被到非半导体原子的键占据，可以实现这种配置。因此，随着半导体材料的另外单层46沉积在非半导体单层50上或之上，新沉积的半导体原子将会占据在非半导体单层下方的半导体原子的其余空位键合位点。
在其它实施例中，可以是多于一个这样的非半导体单层。应该注意，在此对非半导体或半导体单层的引述意味着：用于该单层的材料以体形成则会是非半导体或半导体。也就是说，本领域技术人员将意识到，诸如硅的材料的单个单层可能并不必然展现出与它形成为体或相对厚的层的情况下的相同的性质。
申请人从理论上阐明(但不希望束缚于此)：能带修改层50和相邻的基础半导体部分46a-46n使得超晶格25在平行层的方向上对于电荷载流子具有比以其它方式出现的低的适当电导率有效质量。以另一种方式考虑，该平行方向与堆叠方向是正交的。能带修改层50还可以使得超晶格25具有常见能带结构，同时还有益地起在垂直地位于超晶格上方和下方的层或区之间的绝缘体的作用。
此外，该超晶格结构还可以有益地作为对在垂直地位于超晶格25上方和下方的层之间的掺杂剂和/或材料扩散的阻挡物。本领域技术人员将意识到，这些性质可以因此有益地允许超晶格25提供针对高K电介质的界面，该界面不仅减少高K材料扩散进入沟道区，而且还可以有益地降低不期望的散射效应并且改进装置迁移率。
还可以从理论上阐明，包括超晶格25的半导体装置基于比以其它方式存在的更低的电导率有效质量，可以享有更高的电荷载流子迁移率。在一些实施例中，作为由本发明获得的能带工程的结果，超晶格25可以进一步具有基本上直接带隙，这例如对光电装置尤其有益。
超晶格25还例示性地包括在上层组45n上的帽层52。该帽层52可以包含多个基础半导体单层46。帽层52可以具有2到100个基础半导体的单层，并且，更优选地具有10到50个单层。
每个基础半导体部分46a-46n可以包含选自包括IV族半导体、III-V族半导体以及II-VI族半导体的组的基础半导体。当然，本领域技术人员将意识到，术语“IV族半导体”还包括IV-IV族半导体。更具体地，例如，基础半导体可以包含硅和锗中的至少一种。
例如，每个能带修改层50可以包含选自包括氧、氮、氟、碳和碳-氧的组的非半导体。该非半导体通过下一层的沉积仍然是合乎期望地热稳定的，从而促进制造。在其它实施例中，非半导体可以是与给定半导体处理相兼容的另外的无机或有机的元素或化合物，如本领域技术人员将意识到的。更具体地，例如，基础半导体可以包含硅和锗中的至少一种。
应该注意的是，术语“单层”意在包括单原子层以及单分子层。还需注意的是，由单个单层提供的能带修改层50也意在包括其中不是所有可能的位点都被占据(即，少于全部或100％覆盖)的单层。例如，特别参照图2的原子图，例示了用于硅作为基础半导体材料和氧作为能带修改材料的4/1重复结构。在例示的示例中，用于氧的可能位点只有一半被占据。
在其它实施例和/或以不同的材料，这种一半占据将不一定会是本领域技术人员将会意识到的情况。事实上，甚至在这个示意图中也可以看到，给定单层中的个别氧原子并没有如原子沉积领域的普通技术人员将意识到的那样精确地沿着平面对齐。举例来说，优选的占据范围是从可能的氧位点被占满的大约八分之一到一半，尽管在其它特定实施例中可以使用其它数字。
当前在传统半导体处理中广泛使用硅和氧，并且因此，制造商们很容易能够使用本文描述的这些材料。原子或单层沉积现在同样被广泛使用。因此，本领域技术人员将意识到，根据本发明的包含超晶格25的半导体装置可以非常容易被采纳和实施。
申请人从理论上阐明(但不希望被束缚于此)，对于超晶格(诸如Si/O超晶格)，例如，硅单层的数量理想地应该是7或者更小以便超晶格的能带始终是一致或者相对均匀的，以获得期望的优点。图1和图2中示出的Si/O的4/1重复结构已经被模型化来指示电子和空穴在X方向的增强的迁移率。例如，电子的计算的电导率有效质量(对于体硅，各向同性)是0.26，且对于4/1Si/O超晶格它在X方向上是0.12，得到了0.46的比率。类似地，对于空穴的计算，对体硅产生了0.36的值以及对4/1Si/O超晶格产生0.16的值，得到了0.44的比率。
尽管这种方向性优选特征在某些半导体装置中可能是期望的，但是其它装置可能得益于在任何平行于层组的方向上的迁移率更加均匀地增加。本领域技术人员将意识到，具有对于电子和空穴两者或者仅仅这些类型的电荷载流子的一种的迁移率的增大也可以是有益的。
对于超晶格25的4/1Si/O实施例的较低电导率有效质量可以比以其它方式发生的电导率有效质量的2/3小，并且这适用于电子和空穴两者。当然，本领域技术人员将意识到，超晶格25可以进一步包含至少一种类型的导电性掺杂剂。
事实上，现在附加地参照图3，现在描述根据本发明的具有不同性质的超晶格25’的另一个实施例。在这个实施例中，例示了3/1/5/1的重复模式。更具体地，最低的基础半导体部分46a’具有三个单层，并且第二低的基础半导体部分46b’具有5个单层。在超晶格25’中始终以这个模式重复。能带修改层50’各自可以包括单个单层。对于这样的包括Si/O的超晶格25’，电荷载流子迁移率的增强独立于在层平面的取向。图3中未特别提到的那些其它项与以上参照图1讨论的项类似，并且不需要在此进一步的讨论。
在一些装置实施例中，超晶格的所有基础半导体部分可以是相同数量的单层那样厚。在其它实施例中，至少一些基础半导体部分可以是不同数量的单层那样厚。在另外的其它实施例中，所有的基础半导体部分可以是不同数量的单层那样厚。
在图4A-图4C中，呈现了使用密度泛函理论(DFT)计算的能带结构。在本领域众所周知，DFT低估了带隙的绝对值。因此带隙上方的所有能带可以被移动适当的“剪刀修正(scissors correction)”。然而，已知能带的形状是可靠得多的。应该考虑此来解释垂直能量轴。
图4A示出了对体硅(由连续线表示)和图1示出的4/1Si/O超晶格25(由虚线表示)从伽马点(G)计算的能带结构。各方向涉及4/1Si/O结构的单元晶胞而不是传统的硅晶胞，尽管图中的(001)方向确实对应于传统硅单元晶胞的(001)方向，并因此，示出了硅导带最小值的期望位置。图中的(100)和(010)方向对应于传统硅单元晶胞的(110)和(-110)方向。本领域技术人员将会意识到，图中硅的能带被折叠以将它们表示在4/1Si/O结构的适当倒格子方向上。
可以看到，4/1Si/O结构的导带最小值位于的伽马点处，与体硅(Si)形成对照，而价带最小值发生在(001)方向上布里渊区的边缘(我们称之为Z点)处。还应该注意到，相比于硅导带最小值的曲率，4/1Si/O结构的导带最小值的曲率更大，这是因为由附加的氧层引入的扰动导致的能带分裂。
图4B示出了对体硅(连续线)和4/1Si/O超晶格25(虚线)两者从Z点计算的能带结构。这个图例示了(100)方向上价带的增强的曲率。
图4C示出了对体硅(连续线)和图3的超晶格25’的5/1/3/1Si/O结构(虚线)两者从伽马点和Z点两者计算的能带结构。由于5/1/3/1Si/O结构的对称性，在(100)和(010)方向计算的能带结构是等价的。因此，预期电导率有效质量和迁移率在平行于层的平面(即，垂直于(001)堆叠方向)中是各向同性的。注意，在5/1/3/1Si/O示例中，导带最小值和价带最大值两者都在Z点处或者靠近Z点。
尽管增大的曲率是降低的有效质量的指示，但是也可以通过电导率倒数有效质量张量的计算来取得合适的对比和区别。这使得申请人进一步从理论上阐明：5/1/3/1超晶格25’应该大体上是直接带隙的。本领域技术人员将会理解，光跃迁的合适的矩阵元是直接和非直接带隙行为之间差别的另一个指示。
现在描述使用上述超晶格结构来提供掺杂层或区在半导体装置中的期望位置处的保持的示例方法。在下面描述的方法中，可以以各种方式形成超晶格25，例如在后续被蚀刻以形成用于不同装置的相应超晶格层的半导体晶片上的膜的毯覆形成来形成超晶格25。根据另一示例，例如，相应的超晶格25被选择性地形成在浅沟槽隔离(STI)区形成之后的衬底的不同的有源区域上。可以用这些超晶格沉积方法中的任一种来实现这里讨论的掺杂剂分布保持特征。
在上述超晶格25中，非半导体原子(例如氧)不在替代位点处，并且不生成载流子。而且，它们被化学地键合到相邻的半导体(例如，硅)原子，因此不能移动，但是仍然是热稳定的。超晶格25有益地提供与其相邻的局部掺杂剂堆积(pile-up)和扩散阻挡效应。更具体地说，掺杂剂原子(例如硼、砷、磷)优选停留在氧层附近。结果，在一个示例实施方式中，由于超晶格25的掺杂剂堆积和扩散阻挡效应，SSR(超陡后退(super-steep retrograde))沟道分布可以被自然地形成并且在热处理之后稳定。
然而，超晶格25还有益地提供了在不同的深度或距离处的与超晶格间隔开的掺杂剂层或区的保持。申请人从理论上阐明(但不希望束缚于此)：这可以通过超晶格25通过间隙储存效应(interstitial reservoir effect)来实现。具体而言，在Si-O超晶格25的示例情况下，氧层吸收硅间隙。如下面进一步讨论的，可以通过这种间隙储存效应来控制掺杂剂-间隙对(例如硼和磷)的扩散。结果，由沟道注入引入的PTS(穿通停止)掺杂分布可以被保持在期望的深度处，并且在注入之后的后续退火操作期间不被“抹除(smeared)”。
在图5的平面CMOS装置70中提供了这种方法的一个示例实施例，图5例示性地包括衬底71和多个第一晶体管72以及多个第二晶体管73(为了清楚地例示，在图5中仅示出了每种晶体管中的一个)。更具体地说，在例示的示例中，第一晶体管73是具有第一(低)操作电压的核心CMOS晶体管。此外，例示的示例中的第二晶体管73是具有第二(高)操作电压的输入/输出(I/O)晶体管，第二操作电压高于第一操作电压。
在例示的示例中，第一晶体管72和第二晶体管73由STI区74分开。每个第一晶体管72可以包括至少部分地包括其中的第一超晶格125a(其可以具有与以上参照超晶格25、25'所描述的相似的结构)的第一沟道，以及在第一沟道下方的第一深度处的半导体衬底71中的第一PTS层75。考虑另一种方式，可以根据超晶格125a与第一PTS层75之间的半导体区76的厚度来测量第一深度，在核心装置72以相对较低的第一电压操作的情况下，第一深度可以在例如
Figure BDA0001515316490000111
的数量级，但是在不同的实施例中可以使用不同的厚度。作为参照，第一PTS层75可以具有大约150nm的厚度，并且栅极电极78下面的栅极氧化物77可以具有大约
Figure BDA0001515316490000112
的厚度，但是这里不同的厚度也可以用于不同的配置。
第二晶体管73类似地具有至少部分地包括第二超晶格125b的第二沟道。第二晶体管73也例示性地包括在第二沟道下方的第二深度处的半导体衬底71中的第二PTS层80，第二深度大于第一深度。这里再一次，可以根据超晶格125b和第二PTS层80之间的半导体区81的厚度来测量第二深度，根据本示例，第二深度可以是大约
Figure BDA0001515316490000121
但是在这里再次不同的深度范围可以在不同的实施例中使用。同样作为示例，第二晶体管83的栅极电极83下面的栅极氧化物82可以具有大约
Figure BDA0001515316490000122
的厚度，并且第二PTS层80可以具有大约100nm的厚度，但是不同的厚度可以用在不同的实施例中。在例示的实施例中，第一晶体管72进一步包括在其栅极堆叠的相对侧上的源极区和漏极区84、85，而第二晶体管73例示性地包括在其栅极堆叠的相对侧上的源极区和漏极区86、86。如果需要，在某些实施例中，也可以在超晶格125a、125b中的一个或两个上形成半导体帽层。
一般来说，在NMOS装置中，诸如硼之类的掺杂剂可以用于PTS层，而诸如磷之类的掺杂剂可以用于PMOS装置中的PTS层。无论哪种情况，工艺形成都可以是相似的。首先，对于给定类型的装置并且在衬底71内的期望深度处使用适当的掺杂剂来执行沟道注入。接下来，可以执行快速热退火(RTA)以帮助将掺杂剂峰值集中或保持在期望的深度。接下来，可以执行超晶格膜沉积，作为跨所有有源装置区域的整体毯覆膜，或者选择性地在STI区74之间(如果之前形成的话)。使用到位的(一个或多个)超晶格膜，超晶格内的非半导体(例如氧)有益地吸收在后续栅极氧化(例如RTO)工艺期间形成的间隙(即“间隙储存”效应)，由此在栅极氧化和任何后续退火操作期间，将相应的PTS峰值保持在衬底71内的目标深度处。
如果没有到位的(一个或多个)超晶格膜125a、125b以及上述的间隙储存效应的优点，则PTS层将在这种热处理期间经受“抹除”。也就是说，通常通过每个装置的离子注入来引入PTS层，但是对于常规的硅沟道在热处理之后PTS层会被抹除，这会降低短沟道控制。然而，上述实施例的峰值保持特征使得能够通过单个超晶格膜相对精确地控制装置的PTS掺杂层，同时实现了表面未掺杂沟道、e-和h+迁移率改进以及栅极泄漏和GOI改进。
这样，这种方法的显着优点在于，可以在整个给定的半导体装置中使用相同的超晶格膜来为半导体装置的不同部分(例如在半导体装置70或其它配置中)提供不同的掺杂分布。而且，上述方法可以进一步允许多个掺杂层或区通过给定的MST层例如以横向或垂直布置被保持到位。
用于制造半导体装置70的方法可以包括形成具有第一操作电压的多个第一晶体管72，每个第一晶体管包括半导体衬底71中的第一PTS层75和第一沟道。该方法还可以包括形成具有高于第一操作电压的第二操作电压的多个第二晶体管73，每个第二晶体管包括半导体衬底中的第二PTS层80和第二沟道。如上所述，第二PTS层80处于大于第一PTS层75的第一深度的第二深度处，并且第一和第二沟道分别包括第一和第二超晶格125a、125b。还应当注意的是，还可以执行诸如栅极间隔物形成、源极/漏极/栅极接触形成等的附加的处理步骤。
现在转到图6-图7，除了PTS层或区的保持之外，上述超晶格膜还可以用于其它类型的掺杂剂注入的限制，例如口袋注入或晕圈注入的限制。作为背景，对于具有目标Lg<130nm的CMOS装置，通常使用晕圈注入来防止穿通，同时获得低表面沟道掺杂。然而，对于具有目标Lg<50nm的装置，由于垂直尺寸的减小，可能难以实现低表面掺杂。上述超晶格膜可以有益地用于成功地将晕圈掺杂剂限制在这样的装置中的两个分开的超晶格层之间。
更具体地说，现在相对于图6描述通过形成多个场效应晶体管70和相关联的晶体管结构来制造半导体装置的方法。作为示例，晶体管70可以用在CMOS(或其它)装置中，并且被实现在半导体衬底91上。晶体管70例示性地包括具有栅极氧化物92和栅极电极93的栅极堆叠以及在栅极堆叠的相对侧上的间隔开的源极区和漏极区94、95。此外，在本示例中，晶体管70进一步例示性地包括轻掺杂的源极和漏极延伸区96、97。此外，晶体管70进一步例示性地包括垂直堆叠的上和下超晶格层225a、225b以及在上和下超晶格层225a、225b之间的体半导体层96。可以在上超晶格225a上或上方形成半导体帽层101，其中可以限定晶体管90的沟道(但是在一些实施例中，沟道也可以包括上超晶格225a的至少一些部分)。再一次地，可以理解的是，还可以执行诸如栅极间隔物形成、源极/漏极/栅极接触形成等附加的处理步骤。
当如箭头98所指示的执行成角度的注入以引入晕圈掺杂剂时，则形成晕圈注入部100，晕圈注入部100具有垂直限制在上超晶格225a和下超晶格225b之间的体半导体层96中的峰值浓度。这里同样，超晶格225a、225b可以具有与上述超晶格25、25'类似的结构。
参照图7的110的图示将进一步理解前面的内容。在所例示的示例中，为控制晶体管提供绘图线111，其中在没有到位的超晶格225a、225b的情况下执行了硼晕圈注入。绘图线111的各点表示控制晶体管的相应深度(X轴)处的硼浓度(Y轴)。可以看出，没有硼的显着的峰值浓度，而是如上面进一步讨论的那样在各种不同的深度上被抹除。
作为对比，绘图线112示出了在图6的晶体管90的实施方式内，通过SIMS从在相应深度处的晕圈注入实验测量的硼浓度。而且，晶体管90的各个层被标记在图示110的顶部以供参照，以示出它们相应的深度。可以看出硼的峰值浓度出现在大约
Figure BDA0001515316490000141
处，并且该峰值被限制或保持在上和下超晶格225a、225b之间。在所例示的示例中，超晶格225a、225b和半导体层96、101各自具有大约
Figure BDA0001515316490000142
的厚度，但是不同的厚度可以用在不同的配置中。
受益于这里给出的教导，本领域技术人员将会想到许多修改和其它实施例。因此，应该理解，本公开不限于在此公开的具体示例性实施例。

Claims (7)

1.一种制造半导体装置的方法，包括：
形成具有第一操作电压的多个第一晶体管，每个第一晶体管包括：半导体衬底中的第一穿通停止PTS层和第一间隔开的源极区和漏极区，该第一间隔开的源极区和漏极区限定两者之间的第一沟道；所述第一沟道上方的第一栅极绝缘体；以及所述第一栅极绝缘体上方的第一栅极电极，所述第一PTS层在所述第一沟道下方的第一深度处，并且所述第一沟道包括第一超晶格；以及
形成具有高于所述第一操作电压的第二操作电压的多个第二晶体管，每个第二晶体管包括：所述半导体衬底中的第二PTS层和第二间隔开的源极区和漏极区，该第二间隔开的源极区和漏极区限定两者之间的第二沟道；所述第二沟道上方的第二栅极绝缘体；以及所述第二栅极绝缘体上方的第二栅极电极，所述第二PTS层在所述第二沟道下方的大于所述第一深度的第二深度处，并且所述第二沟道包括第二超晶格；
其中，第一超晶格和第二超晶格由半导体衬底上处于相同水平的单个超晶格膜形成；
其中形成第一晶体管和第二晶体管还包括：在形成第一超晶格和第二超晶格之前执行快速热退火RTA以在第一深度和第二深度处集中PTS掺杂峰，并且在形成超晶格之后执行快速热氧化RTO以在RTO期间保留第一深度和第二深度处的PTS掺杂峰。
2.根据权利要求1所述的方法，其中所述第一超晶格和所述第二超晶格各自包括相应的多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。
3.根据权利要求2所述的方法，其中每个基础半导体部分包含硅。
4.根据权利要求2所述的方法，其中来自相对的基础半导体部分的至少一些半导体原子通过其间的非半导体单层被化学地束缚在一起。
5.根据权利要求2所述的方法，其中所述至少一个非半导体单层包含氧。
6.根据权利要求1所述的方法，其中形成所述多个第一晶体管包括形成多个核心晶体管，并且形成所述多个第二晶体管包括形成多个输入/输出晶体管。
7.根据权利要求1所述的方法，其中所述第一穿通停止层和所述第二穿通停止层各自包括高度掺杂的半导体层。
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