TW201642459A - 具有提供環形植入尖峰侷限之超晶格層之半導體元件及其製作方法 - Google Patents

具有提供環形植入尖峰侷限之超晶格層之半導體元件及其製作方法 Download PDF

Info

Publication number
TW201642459A
TW201642459A TW105115095A TW105115095A TW201642459A TW 201642459 A TW201642459 A TW 201642459A TW 105115095 A TW105115095 A TW 105115095A TW 105115095 A TW105115095 A TW 105115095A TW 201642459 A TW201642459 A TW 201642459A
Authority
TW
Taiwan
Prior art keywords
semiconductor
layer
superlattice
gate
base
Prior art date
Application number
TW105115095A
Other languages
English (en)
Other versions
TWI621264B (zh
Inventor
羅勃Ｊ 米爾斯
竹內秀樹
Original Assignee
安托梅拉公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 安托梅拉公司 filed Critical 安托梅拉公司
Publication of TW201642459A publication Critical patent/TW201642459A/zh
Application granted granted Critical
Publication of TWI621264B publication Critical patent/TWI621264B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155—Comprising only semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/158—Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

一半導體元件可包含一半導體底材，以及該半導體底材上的複數個場效電晶體。每一場效電晶體可包含一閘極，分隔在該閘極相對兩側之源極區與汲極區，垂直堆疊的上部及下部超晶格層，與介於所述源極區與汲極區間之上部及下部超晶格層間之一主體半導體層，以及一環形摻雜物，其具有一尖峰濃度，該尖峰濃度在垂直方向上被侷限於該上部與下部超晶格層間之主體半導體層中。

Description

具有提供環形植入尖峰侷限之超晶格層之半導體元件及其製作方法
本申請案主張2015年5月15日提出之美國臨時專利申請案第62/162,296號之優先權，該臨時申請案之完整內容茲以此述及方式納入本說明書。
本發明一般而言與半導體元件有關，詳細而言，本發明與半導體元件之改進材料及摻雜植入技術有關。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件性能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致性能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與/或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基 礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘電極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其n通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部分(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個能障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一能障區各係由厚度範圍大致在二至六個交疊之SiO2/Si單層所構成。能障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及 製程(Applied Physics and Materials Science & Processing)pp.391-402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice,SAS)。此矽/氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species)及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol.89,No.7(2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
已公告之Wang,Tsu及Lofgren等人的國際申請案WO 02/103,767 A1號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一能障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層/能障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公告之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙(aperiodic photonic band-gap,APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而 言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
雖有此等結構所提供之優點，但對於將進階半導體材料與各種半導體元件結合而言，進一步發展是可能需要的，例如進階半導體結構的摻雜。就半導體元件而言，摻雜物植入一直以來都是一項重要的技術。一種稱為確定性摻雜(deterministic doping)的摻雜方式(參見諸如Shinada et al.,Nature 437,1128(2005))已被提出並證明可用於低溫下量子傳輸。但確定性摻雜的一個潛在問題是摻雜物的後續擴散，這會讓室溫穩定性變成一大挑戰。
一半導體元件可包含一半導體底材，以及該半導體底材上的複數個場效電晶體(FET)。每一場效電晶體可包含一閘極、分隔在該閘極相對兩側之源極區與汲極區、垂直堆疊的上部及下部超晶格層，與介於所述源極區與汲極區間之上部及下部超晶格層間之一主體半導體層，以及一環形摻雜物，其具有一尖峰濃度，該尖峰濃度在垂直方向上被侷限於該上部與下部超晶格層間之主體半導體層中。
更詳細而言，每一上部及下部超晶格可分別包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之 至少一非半導體單層。作為示例，每一基底半導體部份可包括矽，且該至少一非半導體層可包括氧。此外，來自相對基底半導體部分之至少一些半導體原子，可透過該些相對基底半導體部分間之所述非半導體層以化學方式鍵結在一起。
作為示例，該些場效電晶體可包含複數個平面CMOS電晶體。此外，每一場效電晶體可具有一通道，該通道被界定在該上部超晶格層之至少一部分當中。此外，每一閘極可包含位於該上部超晶格層上方之一閘極氧化物層，以及該閘極氧化物層上之一閘電極。
一種用於製作半導體元件之方法可包括在一半導體底材上形成複數個如前文所概述之場效電晶體。
25、25’‧‧‧超晶格
45a~45n、45a’~45n’‧‧‧層群組
46、46’‧‧‧基底半導體單層
46a~46n、46a’~46n’‧‧‧基底半導體部份
50、50’‧‧‧能帶修改層
52、52’‧‧‧頂蓋層
100‧‧‧半導體元件
105‧‧‧矽底材
106、109‧‧‧源極
107、110‧‧‧汲極
108、111‧‧‧通道區
112、115‧‧‧P型矽層
113、114‧‧‧N型矽層
116‧‧‧上部半導體層
117‧‧‧磊晶矽層
120‧‧‧STI區
121‧‧‧氧化物層
122‧‧‧閘電極
125‧‧‧超晶格層
圖1為依照本發明之一半導體元件所用一超晶格之放大示意剖視圖。
圖2為圖1所示超晶格之一部分之透視示意原子圖。
圖3為依照本發明之一超晶格之另一實施方式之放大示意剖視圖。
圖4A為習知技術之主體矽及圖1~2所示之4/1矽/氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖4B為習知技術之主體矽及圖1~2所示之4/1矽/氧超晶格兩者從Z點計算所得能帶結構之圖。
圖4C為習知技術之主體矽及圖3所示之5/1/3/1矽/ 氧超晶格兩者從迦碼點與Z點計算所得能帶結構之圖。
圖5為依照本發明一示例實施方式之半導體元件之概要區塊圖，在該半導體元件中，一超晶格層被用於拘束位在不同深度的貫穿中止層。
圖6為依照本發明一示例實施方式之半導體元件之概要區塊圖，在該半導體元件中，複數個超晶格層被用於侷限該些超晶格層之間的環形植入物(halo implant)的尖峰濃度(peak concentration)。
圖7為圖6所示半導體元件示例之模擬環形植入物濃度之圖表。
茲參考本發明說明書所附圖式詳細說明本發明，圖式中所示者為本發明之示例性實施方式。不過，依照本說明書之教示，本發明可以許多不同形式實施，因此本發明之範疇不應解釋為僅限於本說明書所提供之特定示例性實施方式。相反的，這些實施方式之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡，並向熟習本發明所屬技術領域者完整傳遞本發明所揭露之概念。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)則係用以標示不同實施方式中之類似元件。
申請人之理論認為(但申請人並不欲受此理論所束縛)，本說明書所說明之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電 洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)及： 為電子之定義，且： 為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量(tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所束縛)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子/電洞之導電性有效質量，便可用於分辨出較佳之材料。
申請人已辨識出可用於半導體元件之改進材料或結 構。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及/或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。這些結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及/或鐵電特性，下文將進一步討論之。
參考圖1及圖2，該些材料或結構之形式為一超晶格25，該超晶格25之結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。該超晶格25包含複數個堆疊排列之層群組45a~45n，如圖1之示意剖視圖所示。
如圖所示，超晶格25之每一層群組45a~45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a~46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖1中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格內」一語，係指來自相對之基底半導體部分46a~46n之至少一些半導體原子，透過該些相對基底半導體部分間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部分46a~46n上面之非半導體材料之量而成為可能，這樣，可用之半導體鍵結位置便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論之。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或 上方時，新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位置。
在其他實施方式中，使用超過一個非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，能帶修改層50與相鄰之基底半導體部份46a~46n，可使該超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使該超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為該超晶格25垂直上下方多個層之間之摻雜物及/或材料擴散之阻擋。因此，這些特性可有利地允許該超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進裝置行動性，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含該超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，該超晶格25可進一步具有對諸如光電元件等尤其有利之實質上之直接能帶間隙。
如圖所示，該超晶格25亦包含一上部層群組45n上面之一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部分46a~46n可包含由IV族半導體、III-V族半導體及II-VI族半導體所組成之群組中選定之一基底半導體。當然，IV族半導體亦包含IV-IV族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據(亦即非完全或低於100%之涵蓋範圍)之單層。舉例來說，參照圖2之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4/1重複結構。在圖示之實施例中，氧原子之可能位置僅有一半被佔據。
在其他實施方式及/或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實 上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，就一超晶格而言，例如矽/氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。。圖1及圖2所示之矽/氧4/1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4/1矽/氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4/1矽/氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
該超晶格25之4/1矽/氧實施方式之較低導電性有效 質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，該超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3/1/5/1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽/氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖4A~4C呈現應用密度功能理論(Density Functional Theory,DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖4A呈現主體矽(以實線表示)及圖1之4/1矽/氧超晶格25(以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4/1矽/氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然 圖中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4/1矽/氧結構之適當反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4/1矽/氧結構之導帶最小值係位於迦碼點(G)，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4/1矽/氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖4B呈現主體矽(實線)及該4/1矽/氧超晶格25(虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖4C呈現主體矽(實線)及圖3之5/1/3/1矽/氧超晶格25’(虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5/1/3/1矽/氧結構之對稱性，在方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5/1/3/1矽/氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5/1/3/1超晶格25’實質上應為直接能帶間隙。熟習本發 明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
以下說明利用上述超晶格結構以在半導體元件中將摻雜層或摻雜區保持在所欲位置的示例性方式。在下文所述方式中，超晶格25可以不同方式形成，例如在一半導體晶圓上以地毯式形成(blanket formation)該薄膜，之後對其進行蝕刻，以針對不同元件形成各自的超晶格層。依照另一示例，在淺溝槽隔絕(STI)區形成後，各別的超晶格25係選擇性地形成在一底材的不同主動區上。本說明書所討論的摻雜物輪廓保持(dopant profile retention)特點，可以上述超晶格沉積方式擇一而實現。
在上述該些超晶格25中，非半導體原子(例如氧)並不在替代點(substitution sites)處，且不會產生載子。再者，這些原子是以化學方式與相鄰的半導體原子(例如矽)鍵結，因此這些原子不能移動，但卻是熱穩定(thermally stable)的。超晶格25有利地為局部的摻雜物堆積及擴散阻擋作用作好了準備。詳言之，摻雜物原子(例如硼、砷、磷)比較喜歡停留在靠近氧層處。因此，在一示例性實施例中，因為超晶格25的摻雜物堆積及擴散阻擋作用，超陡峭逆向(super-steep retrograde，SSR)通道輪廓可自然地形成，且在熱處理後仍保持穩定。
然而，為將與超晶格分隔的摻雜層或摻雜區保持在不同深度或距離，超晶格25也有利地作好了準備。申請人之理論為(但申請人並不欲受此理論所束縛)，此可以透過一間隙貯庫作用(interstitial reservoir effect)而由超晶格25實現。詳言之，在矽-氧超晶格25的示例性情況中，氧層會吸收矽間隙(silicon interstitials)。摻雜物-間隙配對(例如硼 及磷)的擴散，可由此間隙貯庫作用控制，如下文所進一步討論。因此，因通道植入而引入的貫穿中止摻雜輪廓(doping profiles)，可被保持在一所欲深度，且不會在植入後的回火操作期間「糊掉(smeared)」。
前述方式之一示例性實施例提供於圖5的平面CMOS元件70中，該元件包含一底材71、複數個第一電晶體72及複數個第二電晶體73(為圖式清晰起見，兩種電晶體在圖5中僅分別繪出一個)。詳言之，在所繪示例中，該些第一電晶體72為核心CMOS電晶體，其具有一第一(低)操作電壓。此外，在所繪示例中，該些第二電晶體73為輸入/輸出(I/O)電晶體，其具有一第二(高)操作電壓，亦即，第二操作電壓高於第一操作電壓。
在所繪示例中，該些第一及第二電晶體72、73被淺溝槽隔絕區74分開。每一第一電晶體72可包含一第一通道，該第一通道在其當中至少局部地包含一第一超晶格125a(其可具有與前述超晶格25、25’相似的結構)，並在其下方的半導體底材71的一第一深度包含一第一貫穿中止層75。從另一角度思考，該第一深度可以該超晶格125a與該第一貫穿中止層75之間的半導體區76的厚度表示，例如，以在相對較低的第一電壓下操作的核心元件72而言，該厚度可為大約20~30Å(埃)，但不同實施方式可使用不同厚度。作為參考，該第一貫穿中止層75可具有大約為150nm的厚度，而閘電極78底下的閘極氧化物77可具有大約為20~30Å的厚度，但在此重申，不同組構可使用不同厚度。
同樣地，該第二電晶體73具有一第二通道，其至少局部地包含一第二超晶格125b。該第二電晶體73亦在其下方的半導體底材 71中的一第二深度包含一第二貫穿中止層80，該第二深度大於該第一深度。同理，該第二深度也可以該超晶格125b與該第二貫穿中止層80之間的半導體區81的厚度表示，就本示例而言，該深度可為大約40~50Å，但不同實施方式可使用不同深度範圍。作為示例，該第二電晶體73的閘電極83底下的閘極氧化物82可具有大約為130Å的厚度，且該第二貫穿中止層80可具有大約為100nm的厚度，但不同實施方式可使用不同厚度。在所繪實施例中，該第一電晶體72在其閘極堆疊的相對兩側更包含源極及汲極區84、85，而該第二電晶體73在其閘極堆疊的相對兩側更包含源極及汲極區86、87。如有需要，在某些實施方式中，一半導體頂蓋層亦可形成在該超晶格125a、125b當中一者或兩者上方。
一般而言，在一NMOS元件中，諸如硼之摻雜物可用於貫穿中止層，而在一PMOS元件中，諸如磷之摻雜物可用於貫穿中止層。不論何種情況，形成過程都是相似的。首先，使用適合給定元件類型的摻雜物，在該底材71內一所需深度進行通道植入。接著，可進行快速熱回火(rapid thermal anneal，RTA)以幫助摻雜物尖峰聚集或保持在該所需深度。接著，可進行超晶格薄膜沉積，其可以是涵蓋所有主動元件區的全面地毯式薄膜，或選擇性地沉積在該些淺溝槽隔絕區74之間(如果先前已形成)。在超晶格薄膜形成後，超晶格內的非半導體(例如氧)就會有利地吸收後續閘極氧化(例如RTO)製程期間所形成的間隙(即間隙貯庫作用)，這樣，在閘極氧化及任何後續回火操作期間，各別的貫穿中止尖峰便可在該底材71內保持在目標深度。
若沒有上述超晶格薄膜125a、125b及間隙貯庫作用 的優點，該些貫穿中止層在熱處理期間就會被「弄糊」。也就是，貫穿中止層通常是透過各元件的離子植入而導入，但在經過常規矽通道的熱處理後會糊掉，從而降低了短通道控制(short-channel control)。然而，上述實施方式的尖峰保持(peak retention)特點，使元件的貫穿中止摻雜層得以透過一單一超晶格薄膜而獲得相當精確的控制，同時改善了表面未摻雜的通道、電子與電洞的遷移率，以及閘極漏電與GOI(閘極氧化物完整性)。
因此，本發明一重要優點為，相同的超晶格薄膜可在整個給定的一半導體元件中使用，以為該半導體元件的不同部分(例如在該半導體元件70或其他組構中)提供不同的摻雜輪廓。上述方式更可進一步讓多個摻雜層或摻雜區透過一給定MST層而在一橫向或垂直設置中保持在適當位置。
一種用於製作半導體元件70的方法可包含，形成具有第一操作電壓的複數個第一電晶體72，每一第一電晶體包含一第一通道及該半導體元件70中一第一貫穿中止層75。該方法亦可包含形成具有第二操作電壓的複數個第二電晶體73，該第二操作電壓大於前述第一操作電壓，每一第二電晶體包含一第二通道及該半導體元件70中一第二貫穿中止層80。如前所述，該第二貫穿中止層80所在的第二深度大於該第一貫穿中止層75所在的第一深度，且該第一及第二通道分別包含第一及第二超晶格125a、125b。應注意的是，該方法亦可進行額外的處理步驟，例如形成閘極間隔層(gate spacer)、形成源極/汲極/閘極接點等等。
參考圖6~7，除了保持貫穿中止層或貫穿中止區外，上述超晶格薄膜亦可用於侷限其他類型的摻雜植入物，例如袋形 (pocket)或環形植入物。作為背景資訊，對於具有小於130nm目標長度的CMOS元件而言，環形植入通常用於防止貫穿，同時獲得低度表面通道摻雜。但對於具有小於50nm目標長度的元件而言，因垂直尺度的縮減，所以很難達成低度表面摻雜。在此類元件中，上述超晶格薄膜可有利地用於將環形摻雜物成功地侷限在兩個分開的超晶格層之間。
以下參考圖6說明一種透過形成複數個場效電晶體90及關聯電晶體結構而製作半導體元件之方法。作為示例，該電晶體90可使用於CMOS或其他元件中，且係提供在一半導體底材91上面。該電晶體90包含一閘極堆疊，其具有一閘極氧化物92與一閘電極93，以及該閘極堆疊相對兩側的分隔的源極及汲極區94、95。此外，在此示例中，該電晶體90更包括輕度摻雜的源極及汲極延伸區96、97。此外，該電晶體90更包括垂直堆疊的上部及下部超晶格層225a、225b，以及介於兩者間的一主體半導體層96。一半導體頂蓋層101可形成在該上部超晶格225a上面或上方，該電晶體90的一通道可被界定在該頂蓋層中(但在某些實施例中，該通道亦可包含該上部超晶格225a的至少某部分)。應理解的是，該方法亦可進行額外的處理步驟，例如形成閘極間隔層、形成源極/汲極/閘極接點等等。
當進行一有角度植入(angled implant)以導入環形摻雜物時，如圖中箭頭98所示，會形成一環形植入物100，其具有一尖峰濃度，該尖峰濃度在垂直方向上被侷限於該主體半導體層96中，介於該上部及下部超晶格225a、225b之間。該上部及下部超晶格225a、225b可具有相似於前述超晶格25、25’之結構。
參照圖7之圖表110可更了解前述內容。在所繪示例 中，一繪製線111代表一控制組電晶體，該電晶體已進行硼原子的環形植入，但沒有超晶格225a、225b。該繪製線111的各點代表在該控制組電晶體中，位於不同深度(X軸)之硼濃度(Y軸)。從圖中可看出，所植入的硼沒有顯著的尖峰濃度，而是在不同深度都被弄糊了，如前文所討論。
相較之下，一繪製線112呈現一環形植入在圖6所示電晶體90內不同深度的硼濃度，該些濃度係根據實驗以SMIS(二次離子質譜儀)測量。此外，該電晶體90的不同層被標示在圖表110的最上方作為參考，以顯示其各別的深度。從圖中可看出，硼的尖峰濃度發生在深度大約120Å處，亦即，該尖峰被侷限或保持在上部超晶格225a與下部超晶格225b之間。在所繪示例中，該些超晶格225a、225b及該些半導體層96、101每一層都具有大約50Å的厚度，但不同組構可使用不同厚度。
在得益於本說明書之教示下，熟習本發明所屬技術領域者將可想到許多變化及其他實施方式。因此，應理解的是，本發明並不限於本說明書所揭露之特定示例性實施方式。
90‧‧‧電晶體
91‧‧‧半導體底材
92‧‧‧閘極氧化物
93‧‧‧閘電極
94‧‧‧源極區
95‧‧‧汲極區
96‧‧‧主體半導體層
96‧‧‧源極延伸區
97‧‧‧汲極延伸區
98‧‧‧環形摻雜物
100‧‧‧環形植入物
101‧‧‧半導體頂蓋層
225a‧‧‧超晶格層
225b‧‧‧超晶格層

Claims (21)

  1. 一半導體元件，其包括：一半導體底材；及該半導體底材上的複數個場效電晶體，且每一場效電晶體包含一閘極，分隔在該閘極相對兩側之源極區與汲極區，垂直堆疊的上部及下部超晶格層，與介於所述源極區與汲極區間之上部及下部超晶格層間之一主體半導體層，以及一環形摻雜物，其具有一尖峰濃度，該尖峰濃度在垂直方向上被侷限於該上部與下部超晶格層間之主體半導體層中。
  2. 如申請專利範圍第1項之半導體元件，其中該上部及下部超晶格分別包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。
  3. 如申請專利範圍第2項之半導體元件，其中每一基底半導體部分包括矽。
  4. 如申請專利範圍第2項之半導體元件，其中來自相對基底半導體部分之至少一些半導體原子，係透過該些相對基底半導體部分間之所述非 半導體層以化學方式鍵結在一起。
  5. 如申請專利範圍第2項之半導體元件，其中所述至少一非半導體層包括氧。
  6. 如申請專利範圍第1項之半導體元件，其中該些場效電晶體包括複數個平面CMOS電晶體。
  7. 如申請專利範圍第1項之半導體元件，其中所述每一場效電晶體具有一通道，該通道被界定在該上部超晶格層之至少一部分當中。
  8. 如申請專利範圍第1項之半導體元件，其中所述每一閘極包括位於該上部超晶格層上方之一閘極氧化物層，以及該閘極氧化物層上之一閘電極。
  9. 一半導體元件，其包括：一半導體底材；及該半導體底材上的複數個CMOS電晶體，且每一CMOS電晶體包含一閘極，分隔在該閘極相對兩側之源極區與汲極區，垂直堆疊的上部及下部超晶格層，與介於所述源極區與汲極區間之上部及下部超晶格層間之一主體半導體層，以及一環形摻雜物，其具有一尖峰濃度，該尖峰濃度在垂直方向上被侷 限於該上部與下部超晶格層間之主體半導體層中；該上部及下部超晶格分別包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。
  10. 如申請專利範圍第9項之半導體元件，其中每一基底半導體部分包括矽。
  11. 如申請專利範圍第9項之半導體元件，其中來自相對基底半導體部分之至少一些半導體原子，係透過該些相對基底半導體部分間之所述非半導體層以化學方式鍵結在一起。
  12. 如申請專利範圍第9項之半導體元件，其中所述至少一非半導體層包括氧。
  13. 如申請專利範圍第9項之半導體元件，其中該些CMOS電晶體包含複數個平面CMOS電晶體。
  14. 如申請專利範圍第9項之半導體元件，其中所述每一CMOS電晶體具有一通道，該通道被界定在該上部超晶格層之至少一部分當中。
  15. 如申請專利範圍第9項之半導體元件，其中所述每一閘極包括位於該上部超晶格層上方之一閘極氧化物層，以及該閘極氧化物層上之一閘 電極。
  16. 一種用於製作半導體元件之方法，該方法包括：在一半導體底材上形成複數個場效電晶體，每一場效電晶體包括一閘極，分隔在該閘極相對兩側之源極區與汲極區，垂直堆疊的上部及下部超晶格層，與介於所述源極區與汲極區間之上部及下部超晶格層間之一主體半導體層，以及一環形摻雜物，其具有一尖峰濃度，該尖峰濃度在垂直方向上被侷限於該上部與下部超晶格層間之主體半導體層中。
  17. 如申請專利範圍第16項之方法，其中所述上部及下部超晶格分別包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。
  18. 如申請專利範圍第17項之方法，其中每一基底半導體部分包括矽。
  19. 如申請專利範圍第17項之方法，其中來自相對基底半導體部分之至少一些半導體原子，係透過該些相對基底半導體部分間之所述非半導體層以化學方式鍵結在一起。
  20. 如申請專利範圍第17項之方法，其中所述至少一非半導體層包括氧。
  21. 如申請專利範圍第16項之方法，其中形成該些場效電晶體包括形成複數個平面CMOS電晶體。
TW105115095A 2015-05-15 2016-05-16 具有提供環形植入尖峰侷限之超晶格層之半導體元件及其製作方法 TWI621264B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562162296P 2015-05-15 2015-05-15
US62/162,296 2015-05-15
US15/154,296 US9899479B2 (en) 2015-05-15 2016-05-13 Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US15/154,296 2016-05-13

Publications (2)

Publication Number Publication Date
TW201642459A true TW201642459A (zh) 2016-12-01
TWI621264B TWI621264B (zh) 2018-04-11

Family

ID=57276164

Family Applications (3)

Application Number Title Priority Date Filing Date
TW105115096A TWI597845B (zh) 2015-05-15 2016-05-16 在不同深度具有超晶格及貫穿中止（ｐｔｓ）層之半導體元件及其製作方法
TW105115095A TWI621264B (zh) 2015-05-15 2016-05-16 具有提供環形植入尖峰侷限之超晶格層之半導體元件及其製作方法
TW106125349A TWI660430B (zh) 2015-05-15 2016-05-16 在不同深度具有超晶格及貫穿中止（pts）層之半導體元件及其製作方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW105115096A TWI597845B (zh) 2015-05-15 2016-05-16 在不同深度具有超晶格及貫穿中止（ｐｔｓ）層之半導體元件及其製作方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW106125349A TWI660430B (zh) 2015-05-15 2016-05-16 在不同深度具有超晶格及貫穿中止（pts）層之半導體元件及其製作方法

Country Status (5)

Country Link
US (2) US9899479B2 (zh)
EP (2) EP3284106B1 (zh)
CN (2) CN107810549B (zh)
TW (3) TWI597845B (zh)
WO (2) WO2016187038A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI747377B (zh) * 2019-07-17 2021-11-21 美商安托梅拉公司 設有含超晶格之突陡接面區之半導體元件及相關方法
US11183565B2 (en) 2019-07-17 2021-11-23 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017197108A1 (en) 2016-05-11 2017-11-16 Atomera Incorporated Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US10170604B2 (en) 2016-08-08 2019-01-01 Atomera Incorporated Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
US10107854B2 (en) 2016-08-17 2018-10-23 Atomera Incorporated Semiconductor device including threshold voltage measurement circuitry
TWI723262B (zh) 2017-05-16 2021-04-01 美商安托梅拉公司 包含超晶格作為吸除層之半導體元件及方法
US10636879B2 (en) 2017-06-13 2020-04-28 Atomera Incorporated Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
US10109479B1 (en) 2017-07-31 2018-10-23 Atomera Incorporated Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
WO2019036572A1 (en) 2017-08-18 2019-02-21 Atomera Incorporated SEMICONDUCTOR DEVICE AND METHOD COMPRISING NON-MONOCRYSTALLINE OCCLUSIONS ADJACENT TO AN ITS SUPER-NETWORK INTERFACE
US10461118B2 (en) 2017-12-15 2019-10-29 Atomera Incorporated Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10529757B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated CMOS image sensor including pixels with read circuitry having a superlattice
US10355151B2 (en) 2017-12-15 2019-07-16 Atomera Incorporated CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10396223B2 (en) 2017-12-15 2019-08-27 Atomera Incorporated Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
US10608043B2 (en) 2017-12-15 2020-03-31 Atomera Incorporation Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
WO2019118840A1 (en) 2017-12-15 2019-06-20 Atomera Incorporated Cmos image sensor including stacked semiconductor chips and readout circuitry including a superlattice and related methods
US10361243B2 (en) 2017-12-15 2019-07-23 Atomera Incorporated Method for making CMOS image sensor including superlattice to enhance infrared light absorption
US10529768B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated Method for making CMOS image sensor including pixels with read circuitry having a superlattice
US10276625B1 (en) 2017-12-15 2019-04-30 Atomera Incorporated CMOS image sensor including superlattice to enhance infrared light absorption
US10367028B2 (en) 2017-12-15 2019-07-30 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10608027B2 (en) 2017-12-15 2020-03-31 Atomera Incorporated Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10615209B2 (en) * 2017-12-15 2020-04-07 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10304881B1 (en) 2017-12-15 2019-05-28 Atomera Incorporated CMOS image sensor with buried superlattice layer to reduce crosstalk
WO2019173668A1 (en) 2018-03-08 2019-09-12 Atomera Incorporated Semiconductor device including enhanced contact structures having a superlattice and related methods
WO2019173630A1 (en) * 2018-03-09 2019-09-12 Atomera Incorporated Semiconductor device and method including compound semiconductor materials and an impurity and point defect blocking superlattice
US10468245B2 (en) 2018-03-09 2019-11-05 Atomera Incorporated Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
US10727049B2 (en) 2018-03-09 2020-07-28 Atomera Incorporated Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
US11664459B2 (en) 2018-04-12 2023-05-30 Atomera Incorporated Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
WO2019199923A1 (en) 2018-04-12 2019-10-17 Atomera Incorporated Semiconductor device and method including vertically integrated optical and electronic devices and comprising a superlattice
US11189699B2 (en) * 2018-06-01 2021-11-30 Samsung Electronics Co., Ltd. Superlattice structure including two-dimensional material and device including the superlattice structure
US10566191B1 (en) 2018-08-30 2020-02-18 Atomera Incorporated Semiconductor device including superlattice structures with reduced defect densities
US10811498B2 (en) 2018-08-30 2020-10-20 Atomera Incorporated Method for making superlattice structures with reduced defect densities
CN110970369B (zh) * 2018-09-30 2022-08-02 中芯国际集成电路制造(上海)有限公司 Cmos反相器结构及其形成方法
US20200135489A1 (en) * 2018-10-31 2020-04-30 Atomera Incorporated Method for making a semiconductor device including a superlattice having nitrogen diffused therein
US10854717B2 (en) 2018-11-16 2020-12-01 Atomera Incorporated Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
US10818755B2 (en) 2018-11-16 2020-10-27 Atomera Incorporated Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10580866B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10580867B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
CN113228300A (zh) * 2018-11-16 2021-08-06 阿托梅拉公司 包括源极和漏极区域与掺杂剂扩散阻挡超晶格层以减小接触电阻的finfet和相关方法
US10840335B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
US10593761B1 (en) * 2018-11-16 2020-03-17 Atomera Incorporated Method for making a semiconductor device having reduced contact resistance
US10840337B2 (en) * 2018-11-16 2020-11-17 Atomera Incorporated Method for making a FINFET having reduced contact resistance
CN113228295A (zh) * 2018-11-16 2021-08-06 阿托梅拉公司 包括源极/漏极掺杂剂扩散阻挡超晶格以减小接触电阻的半导体器件和相关方法
US10840336B2 (en) * 2018-11-16 2020-11-17 Atomera Incorporated Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
US10847618B2 (en) 2018-11-16 2020-11-24 Atomera Incorporated Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
US10916642B2 (en) 2019-04-18 2021-02-09 Globalfoundries U.S. Inc. Heterojunction bipolar transistor with emitter base junction oxide interface
US11329154B2 (en) 2019-04-23 2022-05-10 Atomera Incorporated Semiconductor device including a superlattice and an asymmetric channel and related methods
US10868120B1 (en) 2019-07-17 2020-12-15 Atomera Incorporated Method for making a varactor with hyper-abrupt junction region including a superlattice
US10879357B1 (en) 2019-07-17 2020-12-29 Atomera Incorporated Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
US10937888B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
US10937868B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
US10825901B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including a superlattice
TWI747378B (zh) * 2019-07-17 2021-11-21 美商安托梅拉公司 設有含分隔超晶格之突陡接面區之半導體元件及相關方法
US10840388B1 (en) 2019-07-17 2020-11-17 Atomera Incorporated Varactor with hyper-abrupt junction region including a superlattice
US10825902B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Varactor with hyper-abrupt junction region including spaced-apart superlattices
US11264499B2 (en) 2019-09-16 2022-03-01 Globalfoundries U.S. Inc. Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
CN111430307B (zh) * 2019-12-17 2021-06-25 合肥晶合集成电路股份有限公司 半导体集成器件的阱制备方法和阱注入光罩组
US11158722B2 (en) 2019-12-30 2021-10-26 Globalfoundries U.S. Inc. Transistors with lattice structure
US11437486B2 (en) 2020-01-14 2022-09-06 Atomera Incorporated Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
US11302823B2 (en) 2020-02-26 2022-04-12 Atomera Incorporated Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers
US11177351B2 (en) 2020-02-26 2021-11-16 Atomera Incorporated Semiconductor device including a superlattice with different non-semiconductor material monolayers
US11075078B1 (en) 2020-03-06 2021-07-27 Atomera Incorporated Method for making a semiconductor device including a superlattice within a recessed etch
KR20210134445A (ko) 2020-04-29 2021-11-10 삼성전자주식회사 반도체 소자
US11569368B2 (en) 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
TWI789780B (zh) * 2020-06-11 2023-01-11 美商安托梅拉公司 包含超晶格且提供低閘極漏電之半導體元件及相關方法
US11469302B2 (en) 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage
US11837634B2 (en) 2020-07-02 2023-12-05 Atomera Incorporated Semiconductor device including superlattice with oxygen and carbon monolayers
WO2022187462A1 (en) 2021-03-03 2022-09-09 Atomera Incorporated Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice and associated methods
TWI806553B (zh) 2021-04-21 2023-06-21 美商安托梅拉公司 包含超晶格及富集矽２８磊晶層之半導體元件及相關方法
US11923418B2 (en) 2021-04-21 2024-03-05 Atomera Incorporated Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11810784B2 (en) 2021-04-21 2023-11-07 Atomera Incorporated Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
WO2022245889A1 (en) 2021-05-18 2022-11-24 Atomera Incorporated Semiconductor device including a superlattice providing metal work function tuning and associated methods
US11682712B2 (en) 2021-05-26 2023-06-20 Atomera Incorporated Method for making semiconductor device including superlattice with O18 enriched monolayers
US11728385B2 (en) 2021-05-26 2023-08-15 Atomera Incorporated Semiconductor device including superlattice with O18 enriched monolayers
US11862717B2 (en) 2021-08-24 2024-01-02 Globalfoundries U.S. Inc. Lateral bipolar transistor structure with superlattice layer and method to form same
US11631584B1 (en) 2021-10-28 2023-04-18 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to define etch stop layer
US11721546B2 (en) 2021-10-28 2023-08-08 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms

Family Cites Families (137)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485128A (en) 1981-11-20 1984-11-27 Chronar Corporation Bandgap control in amorphous semiconductors
JPH0656887B2 (ja) 1982-02-03 1994-07-27 株式会社日立製作所 半導体装置およびその製法
US4594603A (en) 1982-04-22 1986-06-10 Board Of Trustees Of The University Of Illinois Semiconductor device with disordered active region
US4590399A (en) 1984-02-28 1986-05-20 Exxon Research And Engineering Co. Superlattice piezoelectric devices
JPS6127681A (ja) 1984-07-17 1986-02-07 Res Dev Corp Of Japan 超格子構造のチヤネル部をもつ電界効果トランジスタ
US4882609A (en) 1984-11-19 1989-11-21 Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. Semiconductor devices with at least one monoatomic layer of doping atoms
JPS61145820A (ja) 1984-12-20 1986-07-03 Seiko Epson Corp 半導体薄膜材料
JPS61210679A (ja) 1985-03-15 1986-09-18 Sony Corp 半導体装置
JPS61220339A (ja) 1985-03-26 1986-09-30 Nippon Telegr & Teleph Corp <Ntt> 半導体材料特性の制御方法
JPS62219665A (ja) 1986-03-20 1987-09-26 Fujitsu Ltd 超格子薄膜トランジスタ
US4908678A (en) 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US5081513A (en) 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5216262A (en) 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices
JPH0643482A (ja) 1992-07-24 1994-02-18 Matsushita Electric Ind Co Ltd 空間光変調素子およびその製造方法
US5955754A (en) 1992-10-23 1999-09-21 Symetrix Corporation Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US5606177A (en) 1993-10-29 1997-02-25 Texas Instruments Incorporated Silicon oxide resonant tunneling diode structure
US5466949A (en) 1994-08-04 1995-11-14 Texas Instruments Incorporated Silicon oxide germanium resonant tunneling
US5627386A (en) 1994-08-11 1997-05-06 The United States Of America As Represented By The Secretary Of The Army Silicon nanostructure light-emitting diode
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5577061A (en) 1994-12-16 1996-11-19 Hughes Aircraft Company Superlattice cladding layers for mid-infrared lasers
FR2734097B1 (fr) 1995-05-12 1997-06-06 Thomson Csf Laser a semiconducteurs
US6326650B1 (en) 1995-08-03 2001-12-04 Jeremy Allam Method of forming a semiconductor structure
US6344271B1 (en) 1998-11-06 2002-02-05 Nanoenergy Corporation Materials and products using nanostructured non-stoichiometric substances
EP0843361A1 (en) 1996-11-15 1998-05-20 Hitachi Europe Limited Memory device
JPH10173177A (ja) 1996-12-10 1998-06-26 Mitsubishi Electric Corp Ｍｉｓトランジスタの製造方法
WO1998026316A1 (en) 1996-12-13 1998-06-18 Massachusetts Institute Of Technology Tunable microcavity using nonlinear materials in a photonic crystal
US5994164A (en) 1997-03-18 1999-11-30 The Penn State Research Foundation Nanostructure tailoring of material properties using controlled crystallization
US6255150B1 (en) 1997-10-23 2001-07-03 Texas Instruments Incorporated Use of crystalline SiOx barriers for Si-based resonant tunneling diodes
US6376337B1 (en) 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
JP3443343B2 (ja) 1997-12-03 2003-09-02 松下電器産業株式会社 半導体装置
JP3547037B2 (ja) 1997-12-04 2004-07-28 株式会社リコー 半導体積層構造及び半導体発光素子
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
JP3854731B2 (ja) 1998-03-30 2006-12-06 シャープ株式会社 微細構造の製造方法
US6888175B1 (en) 1998-05-29 2005-05-03 Massachusetts Institute Of Technology Compound semiconductor structure with lattice and polarity matched heteroepitaxial layers
RU2142665C1 (ru) 1998-08-10 1999-12-10 Швейкин Василий Иванович Инжекционный лазер
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
JP3592981B2 (ja) 1999-01-14 2004-11-24 松下電器産業株式会社 半導体装置及びその製造方法
EP1168539B1 (en) 1999-03-04 2009-12-16 Nichia Corporation Nitride semiconductor laser device
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
GB9905196D0 (en) 1999-03-05 1999-04-28 Fujitsu Telecommunications Eur Aperiodic gratings
GB2385944B (en) 1999-03-05 2003-10-29 Nanovis Llc Optic fibre aperiodic Bragg grating
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6281532B1 (en) 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6570898B2 (en) 1999-09-29 2003-05-27 Xerox Corporation Structure and method for index-guided buried heterostructure AlGalnN laser diodes
US6501092B1 (en) 1999-10-25 2002-12-31 Intel Corporation Integrated semiconductor superlattice optical modulator
RU2173003C2 (ru) 1999-11-25 2001-08-27 Септре Электроникс Лимитед Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств
KR100675316B1 (ko) 1999-12-22 2007-01-26 엘지.필립스 엘시디 주식회사 세정장비 일체형 에치/스트립 장치
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
US7902546B2 (en) 2000-08-08 2011-03-08 Translucent, Inc. Rare earth-oxides, rare earth -nitrides, rare earth -phosphides and ternary alloys with silicon
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6375337B1 (en) 2000-10-11 2002-04-23 Ching-Chao Chen Ornamental display lamp assembly
US6521549B1 (en) 2000-11-28 2003-02-18 Lsi Logic Corporation Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6690699B2 (en) 2001-03-02 2004-02-10 Lucent Technologies Inc Quantum cascade laser with relaxation-stabilized injection
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6831292B2 (en) 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7060632B2 (en) 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6816530B2 (en) 2002-09-30 2004-11-09 Lucent Technologies Inc. Nonlinear semiconductor light sources
JP2004311891A (ja) * 2003-04-10 2004-11-04 Seiko Instruments Inc 半導体装置
US7023010B2 (en) 2003-04-21 2006-04-04 Nanodynamics, Inc. Si/C superlattice useful for semiconductor devices
US20040266116A1 (en) 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20070063186A1 (en) 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US20050282330A1 (en) 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20060267130A1 (en) 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20060231857A1 (en) 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20060292765A1 (en) 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US20070020860A1 (en) 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20060273299A1 (en) 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20050279991A1 (en) 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US20070020833A1 (en) 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US7033437B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20070015344A1 (en) 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20060263980A1 (en) 2003-06-26 2006-11-23 Rj Mears, Llc, State Of Incorporation: Delaware Method for making a semiconductor device including a floating gate memory cell with a superlattice channel
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20040262594A1 (en) 2003-06-26 2004-12-30 Rj Mears, Llc Semiconductor structures having improved conductivity effective mass and methods for fabricating same
US20060243964A1 (en) 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20060220118A1 (en) 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US20060011905A1 (en) 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US20060223215A1 (en) 2003-06-26 2006-10-05 Rj Mears, Llc Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice
US20070063185A1 (en) 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US20060289049A1 (en) 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US20070012910A1 (en) 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
EP1644983B1 (en) 2003-06-26 2008-10-29 Mears Technologies, Inc. Semiconductor device including mosfet having bandgap-engineered superlattice
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US20070010040A1 (en) 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
JP4035502B2 (ja) 2003-11-28 2008-01-23 キヤノン株式会社 照明光学系および撮影装置
KR100549008B1 (ko) 2004-03-17 2006-02-02 삼성전자주식회사 등방성식각 기술을 사용하여 핀 전계효과 트랜지스터를제조하는 방법
US7176530B1 (en) * 2004-03-17 2007-02-13 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor
JP2009529780A (ja) 2005-06-20 2009-08-20 メアーズ テクノロジーズ， インコーポレイテッド 超格子を間に有するシャロー・トレンチ・アイソレーション（ｓｔｉ）領域を含む半導体デバイス、及びその製造方法
JP2008544581A (ja) 2005-06-30 2008-12-04 メアーズ テクノロジーズ， インコーポレイテッド 絶縁体上半導体（ｓｏｉ）構造を有し且つ薄い半導体層上の超格子を含む半導体デバイス、及びその製造方法
TW200746421A (en) 2005-07-15 2007-12-16 Mears R J Llc Semiconductor device including a channel with a non-semiconductor monolayer and associated methods
JP2007088054A (ja) * 2005-09-20 2007-04-05 Nec Electronics Corp 半導体装置
US20070166928A1 (en) 2005-12-22 2007-07-19 Rj Mears, Llc Method for making an electronic device including a selectively polable superlattice
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
WO2007098138A2 (en) 2006-02-21 2007-08-30 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer and associated methods
US20080012004A1 (en) 2006-03-17 2008-01-17 Mears Technologies, Inc. Spintronic devices with constrained spintronic dopant
US7625767B2 (en) 2006-03-17 2009-12-01 Mears Technologies, Inc. Methods of making spintronic devices with constrained spintronic dopant
US7741699B2 (en) 2006-06-09 2010-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having ultra-shallow and highly activated source/drain extensions
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) * 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
JP2009054705A (ja) 2007-08-24 2009-03-12 Toshiba Corp 半導体基板、半導体装置およびその製造方法
JP5159413B2 (ja) 2008-04-24 2013-03-06 株式会社東芝 半導体装置及びその製造方法
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US20110215299A1 (en) * 2010-03-08 2011-09-08 Mears Technologies, Inc. Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods
CN102870195A (zh) 2010-04-28 2013-01-09 日本碍子株式会社 外延基板以及外延基板的制造方法
US8933488B2 (en) * 2010-12-03 2015-01-13 The Board Of Trustees Of The Leland Stanford Junior Univerity Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS
US8748270B1 (en) * 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
JP5708187B2 (ja) 2011-04-15 2015-04-30 サンケン電気株式会社 半導体装置
US8994002B2 (en) 2012-03-16 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET having superlattice stressor
US8497171B1 (en) 2012-07-05 2013-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET method and structure with embedded underlying anti-punch through layer
EP3072158A1 (en) 2013-11-22 2016-09-28 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
WO2015191561A1 (en) 2014-06-09 2015-12-17 Mears Technologies, Inc. Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI747377B (zh) * 2019-07-17 2021-11-21 美商安托梅拉公司 設有含超晶格之突陡接面區之半導體元件及相關方法
US11183565B2 (en) 2019-07-17 2021-11-23 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods

Also Published As

Publication number Publication date
TWI597845B (zh) 2017-09-01
EP3281231A1 (en) 2018-02-14
TW201737348A (zh) 2017-10-16
EP3284106A1 (en) 2018-02-21
WO2016187038A1 (en) 2016-11-24
CN107810549A (zh) 2018-03-16
EP3281231B1 (en) 2021-11-03
CN107771355B (zh) 2022-01-14
TWI621264B (zh) 2018-04-11
WO2016187042A1 (en) 2016-11-24
EP3284106B1 (en) 2021-12-22
US9899479B2 (en) 2018-02-20
US9941359B2 (en) 2018-04-10
CN107771355A (zh) 2018-03-06
US20160336406A1 (en) 2016-11-17
TWI660430B (zh) 2019-05-21
US20160336407A1 (en) 2016-11-17
TW201642473A (zh) 2016-12-01
CN107810549B (zh) 2021-12-17

Similar Documents

Publication Publication Date Title
TWI597845B (zh) 在不同深度具有超晶格及貫穿中止（ｐｔｓ）層之半導體元件及其製作方法
TWI722398B (zh) 包含具有超晶格之改良接觸結構之半導體元件及相關方法
TWI624004B (zh) 包含超晶格空乏層堆疊之半導體元件及其相關方法
TWI543362B (zh) 包含超晶格貫穿中止層之垂直式半導體元件及其相關方法
WO2020102288A1 (en) Method for making a semiconductor device having reduced contact resistance
TWI761725B (zh) 具有包含用於限制摻雜物之氧插入層之金屬半導體接點的半導體元件及相關方法
WO2020102291A1 (en) Method for making a finfet having reduced contact resistance
WO2020102283A1 (en) Finfet including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance and associated methods
TWI751609B (zh) 設有含超晶格之突陡接面區之可變電容器及相關方法
TWI772839B (zh) 設有含分隔超晶格之突陡接面區之可變電容器及相關方法
EP4331017A1 (en) Semiconductor device including superlattice with o18 enriched monolayers and associated methods
EP3871268A1 (en) Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance and associated methods
EP3871265A1 (en) Semiconductor device and method including body contact dopant diffusion blocking superlattice having reduced contact resistance and related methods