TWI712172B - 包含與超晶格-sti界面相鄰的非單晶縱樑的半導體元件及其方法 - Google Patents

包含與超晶格-sti界面相鄰的非單晶縱樑的半導體元件及其方法 Download PDF

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TWI712172B
TWI712172B TW107128841A TW107128841A TWI712172B TW I712172 B TWI712172 B TW I712172B TW 107128841 A TW107128841 A TW 107128841A TW 107128841 A TW107128841 A TW 107128841A TW I712172 B TWI712172 B TW I712172B
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semiconductor
superlattice
sti
silicon
layer
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羅勃約翰 史蒂芬生
史考特 Ａ. 克雷帕斯
羅勃Ｊ. 米爾斯
克理帕腩維克 羅
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美商安托梅拉公司
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Abstract

一半導體元件，其可包含一半導體底材及當中隔開的第一及第二淺溝槽隔離(STI)區，以及設置在該半導體底材上且在該第一與第二STI區之間延伸之一超晶格。該超晶格可包含堆疊之層群組，其中每一層群組包含堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包含一第一半導體縱樑，其在該超晶格之第一端與該第一STI區之界面包含一非單晶體，以及該超晶格上方一閘極。

Description

包含與超晶格-STI界面相鄰的非單晶縱樑的半導體元件及其方法
本發明一般而言與半導體領域有關，詳細而言，本發明與具有基於能帶工程之增強特性之半導體及其相關方法有關。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件效能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致效能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與/或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘極上的 電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其N型通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部分(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個阻障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一阻障區各係由厚度範圍大致在二至六個交疊之SiO2/Si單層所構成。阻障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing)pp.391-402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice,SAS)。此矽/氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸 如氧原子等被吸附物種(adsorbed species)及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol.89,No.7(2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
授予Wang等人的美國專利第7,105,895號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一阻障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層/阻障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公告之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙(aperiodic photonic band-gap,APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
除此之外，授予Wang等人的美國專利第6,376,337號揭示一種用於製作半導體元件絕緣或阻障層之方法，其包括在矽底材上沉積一層矽及至少一另外元素，使該沉積層實質上沒有缺陷，如此實質上無缺陷的磊晶矽便能沉積 於該沉積層上。作為替代方案，一或多個元素構成之一單層，較佳者為包括氧元素，在矽底材上被吸收。夾在磊晶矽之間的複數絕緣層，形成阻障複合體。
儘管已有上述方法存在，若要使用進階的半導體材料及製作方法以提升半導體元件之效能，進一步的增強是有必要的。
一半導體元件，其可包含一半導體底材及當中隔開的第一及第二淺溝槽隔離(STI)區，以及設置在該半導體底材上且在該第一與第二STI區之間延伸之一超晶格。該超晶格可包含複數個堆疊之層群組，其中每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包含一第一半導體縱樑(semiconductor stringer)，其在該超晶格之第一端與該第一STI區之界面包含一非單晶體，以及該超晶格上方一閘極。
更詳細而言，該第一半導體縱樑可在該超晶格之上。此外，該底材及該超晶格內可包含摻雜劑以界定出隔開的源極區與汲極區。在某些實施例中，該半導體元件可更包括一第二半導體縱樑，其鄰接該超晶格之第二端與該第二STI區之界面。在一示例性實施例中，該第一半導體縱樑可分隔該超晶格之第一端與該第一STI區。
此外，該半導體縱樑可包含非晶矽。該半導體元件可更包括該第一半導體縱樑中一通道阻絕植入物(channel stop implant)。該半導體元件亦可包括該第一半導體縱樑上一氧化物頂蓋。作為示例，該基底半導體單層可包含矽，而該至少一非半導體單層可包含氧。
一種用於製作半導體元件之方法，其可包含在半導體底材中形成第一及第二淺溝槽隔離(STI)區，以及形成設置在該半導體底材上且在該第一與第二STI區之間延伸之一超晶格。該超晶格可包含複數個堆疊之層群組，其中每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該方法亦可包含形成一第一半導體縱樑，其在該超晶格之第一端與該第一STI區之界面包含一非單晶體，以及在該超晶格上方形成一閘極。
更詳細而言，該第一半導體縱樑可在該超晶格之上。該方法亦可包括摻雜該底材及該超晶格以在當中界定出隔開的源極區與汲極區。此外，該方法亦可包括形成一第二半導體縱樑，使其鄰接該超晶格之第二端與該第二STI區之界面。在一示例性實施例中，該第一半導體縱樑可分隔該超晶格之第一端與該第一STI區。
舉例而言，該半導體縱樑可包含非晶矽。該方法可更包括在該第一半導體縱樑中植入一通道阻絕摻雜劑。此外，亦可在該第一半導體縱樑上形成一氧化物頂蓋。同樣舉例而言，該基底半導體單層可包含矽，而該至少一非半導體單層可包含氧。
20:半導體元件
21、21”、200、200’、200”:底材
21n’:N型主動區
21p’:P型主動區
22:源極延伸區
23:汲極延伸區
22’:LDD
25、25’、25”、225、225’、225”:超晶格
26、26’:源極區
27、27’:汲極區
30:源極矽化物層
31:汲極矽化物層
34:矽化物層
35:閘極
36、36’、36”、218”:閘電極層
37、217”:閘極介電層
37’:閘極氧化物
40、40’、41、41’:側壁間隔物
42、43:環形植入區
42，、43’:環狀物
45a-45n、45a’-45n’:層群組
46、46’:基底半導體單層
46a-46n、46a’-46n’:基底半導體部份
50、50’:能帶修改層
52、52’:頂蓋層
78”:頂蓋薄膜
79n’:反向N型井
79p’:反向P型井
80、80’、80”、80'''、81、81’、81”、81'''、201、201’、201”:STI區
82、82’、83、83’:非單晶縱樑
84:VT植入物
85:犧牲氧化物層
85:墊氧化物
86、86’、86”、86'''、87、87’、87”、87''':非單晶矽沉積物
88、210’、211”、211”:光阻劑光罩
88n’:過大N型光罩
88p’:過大P型光罩
89:間隙
130n''':NFET通道阻絕光罩
130p''':PFET通道阻絕光罩
202、204、204’、212’:氧化物層
203、205、205’:氮化物層
206:氧化物頂蓋
207:縱樑
213”:深井植入
214”:臨界電壓植入
215”:氧化物/氮化物硬光罩
216”:主動區環體氧化物
219”、222”:間隔物
220”:源極/汲極延伸植入物
221”:環形植入物
223”:源極/汲極植入物
226”:源極/汲極矽化物區
227”:閘極矽化物區
圖1為依照本發明包含超晶格之半導體元件之剖視圖。
圖2A至圖2D為描繪形成圖1半導體元件之剖視圖及其相關的潛在困難。
圖3為圖1所示半導體元件於閘電極圖案化及蝕刻後之一部分之頂視圖。
圖4為呈現圖1半導體元件製作之流程圖。
圖5A及圖5B為在圖4所示方法中使用之NFET及PFET通道阻絕光罩(channel-stop mask)之頂視圖。
圖6A至圖6B為描繪圖4所示方法中使用之光罩步驟及通道阻絕植入步驟之剖視圖。
圖7為所述元件結構在閘電極圖案化與蝕刻後之頂視圖，其繪示元件中將受益於通道阻絕植入之目標區域，此為圖4所示方法之一部分。
圖8A至圖8C為描繪圖4所示方法之抗蝕劑剝離、閘極摻雜、間隔物形成及源極/汲極摻雜步驟之剖視圖。
圖9為描繪製作圖1所示半導體元件之替代方法之流程圖。
圖10A至圖10B為描繪圖9所示方法之非單晶半導體蝕刻、通道阻絕植入和閘極沉積/植入步驟之剖視圖。
圖11為所述元件結構在圖9所示方法之隔物形成步驟後之頂視圖。
圖12A及圖12B分別為所述元件結構在平行於與垂直於閘極層之矽化物形成後之剖視圖。
圖13A及圖13B為描繪依照製作圖1所示半導體元件之另一替代製作流程中以光罩遮蔽主動區及凸舌通道阻絕之步驟之頂視圖。
圖14為圖1所示之超晶格之放大示意剖視圖。
圖15為圖14所示超晶格之一部分之透視示意原子圖。
圖16為可用於圖1所示元件之另一實施方式之超晶格放大示意剖視圖。
圖17A為習知技術之主體矽及圖14所示之4/1矽/氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖17B為習知技術之主體矽及圖14所示之4/1矽/氧超晶格兩者從Z點計算所得能帶結構之圖。
圖17C為習知技術之主體矽及圖16所示之5/1/3/1矽/氧超晶格兩者從G點與Z點計算所得能帶結構之圖。
圖18至圖24為描繪根據一示例性實施方式在STI形成後進行無光罩超晶格沉積之方法之示意剖視圖。
圖25至圖27為描繪在STI形成後進行無光罩超晶格沉積之一替代實施方式之示意剖視圖。
圖28A、圖28B、圖29至圖31、圖32A、圖32B及圖33至圖34為描繪在STI形成後進行無光罩超晶格沉積之另一替代實施方式之示意剖視圖。
圖35為描繪與圖28A、圖28B、圖29至圖31、圖32A、圖32B及圖33至圖34所示方法相關之製作方式之流程圖。
茲參考說明書所附圖式詳細說明本發明，圖式中所示者為本發明之較佳實施例。不過，本發明可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之實施例。相反的，這些實施例之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡，並將本發明的範圍完全傳達給熟習本發明所屬技 術領域者。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)及多重撇號則用以標示不同實施方式中之替代元件。
本發明係關於在原子或分子等級上控制半導體材料之性質，以在半導體元件內部實現改進的效能。此外，本發明亦涉及用於半導體元件傳導路徑之改進材料之辨識、製作及使用。
申請人之理論認為(但申請人並不欲受此理論所束縛)，本說明書所述之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)
Figure 107128841-A0305-02-0010-3
及
Figure 107128841-A0305-02-0010-4
：
Figure 107128841-A0305-02-0010-1
 為電子之定義，且：
Figure 107128841-A0305-02-0010-2
 為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度(克氏溫度，Kelvin)，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量(tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所束縛)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量(conductivity effective mass)。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子/電洞之導電性有效質量，便可用於分辨出較佳之材料。
使用上述方法可選擇具有更佳能帶結構的材料以滿足特定用途。例如用於半導體元件中的通道區之超晶格25材料即為一例。茲參考圖1說明依照本發明之包含超晶格25之平面式MOSFET 20。然而，熟習本發明所屬技術領域者當可理解，本說明書提及之材料可用於許多不同類型之半導體元件，例如分離式元件及/或集成電路。
如圖所示，MOSFET 20包括一底材21，其中設有淺溝槽隔離(STI)區80、81。更詳細而言，MOSFET元件20可為互補MOS(CMOS)元件，其包含各自具有超晶格通道之N型及P型通道電晶體，該元件之STI區係用於與相鄰電晶體絕緣，熟習本發明所屬技術領域者當可理解。作為示例，底材21可為半導體底材(例如矽底材)或絕緣體上矽(SOI)底材。STI區80、81可包含一氧化物，例如矽，但在其他實施例中也可使用其他適合的材料。
如圖所示，MOSFET20更包含輕摻雜的源極/汲極延伸區22、23，較重摻雜之源極/汲極區26、27，及介於其間並由超晶格25提供之通道區。如圖所示，環形植入區42、43(halo implant region)被包含在超晶格25下方之源極 區26和汲極區27間。源極/汲極矽化物層30、31覆蓋在源極/汲極區上，熟習本發明所屬技術領域者當可理解。如圖所示，閘極35包含與超晶格25所提供通道鄰接之閘極介電層37，及位於該閘極介電層上之閘電極層36。如圖所示，MOSFET 20亦設有側壁間隔物40、41(sidewall spacer)，及閘電極層36上之矽化物層34。
在將超晶格25集成至最先進CMOS的流程中，可能需要去除在STI區80、81上形成之超晶格薄膜25，以避免相鄰元件結構間發生短路或漏電。更詳細而言，茲參照圖2A至2D至圖3，製作流程可始於底材21，該底材中設有STI區80、81，且上面設有犧牲氧化物層85，且具有VT植入物84(由一行「+」的符號表示)。在晶質矽超晶格的情況下(此將於下文進一步描述)，在去除犧牲氧化物層85並在底材21上形成超晶格25時，矽沉積會造成非單晶(即多晶或非晶)矽沉積物86、87覆蓋在STI區80、81上。然而，如上所述，非單晶矽沉積物86,87通常需要被去除以避免相鄰之元件結構間發生短路或漏電。
雖然在一些實施方式中可使用單一基線(single baseline)主動區(active area，AA)光阻劑光罩88(圖2C)並接著蝕刻非單晶矽沉積物86、87(圖2D)這種相對簡單的方法進行遮蔽，但在其他情況下這麼做可能會造成某些困難。更詳細而言，若光罩未對準(導致STI邊緣上的一部分非單晶矽沉積物86被光阻劑88遮蔽)，或因電漿蝕刻期間過度蝕刻(over-etch)不足，便可能使STI邊緣處和STI凹陷中的部分非單晶矽沉積物保持未蝕刻，從而被保留為與主動元件相鄰之寄生元件，然而與STI區相鄰之主動元件區則會意外被蝕刻(因通道阻絕光罩未對準造成)而留下一間隙89。其結果便是摻雜物潛變(dopant creep)可能會非刻意地發 生在鄰接非單晶矽部份86之處，而不均勻的矽化物和源極/汲極接面漏電(junction leakage)底材則可能會發生在鄰接間隙89之處。
因此，本發明有利地修改了光罩與蝕刻操作，以在STI區80、81之凹陷與邊緣提供具通道阻絕植入物之非單晶半導體縱樑或未蝕刻凸舌(tab)82、83，如圖1所示。此外，在超晶格25之半導體單層磊晶生長過程中於STI區80、81上所產生的非單晶半導體沉積會形成非單晶矽。非單晶縱樑82、83可有利地以諸如一通道阻絕植入摻雜物(channel-stop implant dopant)予以摻雜，如下文透過不同製作示例所進一步討論。
茲參考圖4至圖8說明用於製作半導體元件20之第一製作整合流程。從步驟方塊90的STI晶圓開始，VT井在步驟方塊91被植入(穿過150Å之墊氧化物85)，接著在步驟方塊92進行乾蝕刻(120Å之氧化物)。接著在步驟方塊93暴露於氫氟酸(HF)中(SC1/100：1，50Å)。詳細而言，墊氧化物85之部分乾蝕刻及相對短的HF暴露時間可有助於，舉例而言，降低STI凹陷之深度。接著，在步驟方塊94沉積超晶格薄膜25’(此將在下文進一步討論)，然後在步驟方塊95進行清潔步驟(SPM/200：1，HF/RCA)。
本示例不採用上述單一基線AA光罩，而是在步驟方塊96形成一第一較大N型通道AA光罩(圖5A與圖6A)，接著電漿蝕刻鄰接N型通道區之STI區上方之非單晶半導體材料(步驟方塊97)，然後在步驟方塊98以該較大N型通道AA光罩進行NFET通道阻絕植入(圖9B)。在圖5A與圖5B中，較大(over-sized)之N型與P型光罩分別以編號88n’與88p’表示，而N型與P型主動區則分別以編號21n’與21p’表示。此外，反向N型井與P型井係分別以編號79n’與79p’表示。
接著，在步驟方塊99形成一較大P型通道光罩(圖5B)，接著電漿蝕刻鄰接P型通道區之STI區上方之非單晶半導體材料(步驟方塊100)，並在步驟方塊101進行PFET通道阻絕植入。NFET及FET通道阻絕植入較佳者為以一角度或斜度進行，例如三十度角，如圖6B所示，但其他角度也可使用。如圖所示，通道阻絕植入物係以箭頭符號表示。作為示例，硼可用於NFET通道阻絕植入，而砷或磷可用於PFET通道阻絕植入。STI區80’、81’之凹陷中的縱樑82’、83’及STI邊緣的未蝕刻矽凸舌，最好以通道阻絕植入物高度反向摻雜(highly counter-doped)以抵銷或減輕摻雜物從源極-汲極區擴散至STI凹陷中的非單晶矽或元件通道角落之凸舌之擴散潛變(diffusion creep)，從而有利地讓此寄生邊緣元件具有較高的二極體崩潰電壓、較高的臨界電壓及較低的關閉電流(off current)。針對P型與N型通道元件採用二種相異之較大光罩可有利地在非單晶矽蝕刻期間保護AA的對準標記，並讓每一主動元件在其相反型元件進行通道阻絕植入時受到保護。
在PFET通道阻絕植入完成後，於步驟方塊102(圖8A)進行預先閘極清潔(SPM/HF/RCA)，接著在步驟方塊103形成閘極氧化物37’(約20Å)，並在步驟方塊104(圖8B)進行非單晶矽閘電極36之沉積與植入摻雜。在步驟方塊105賦予閘極圖案並進行蝕刻，接著在步驟方塊106形成側壁間隔物40’、41’(例如100Å之氧化物)，並在步驟方塊107(圖8C)進行輕摻雜汲極(LDD)22’、23及環狀物42’、43’之植入。接著在步驟方塊108蝕刻側壁間隔物40’、41’(例如1900Å之氧化物)。間隔物40、41形成後，接著在步驟方塊109進行源極/汲極26’、27’植入與回火(例如在1000℃的溫度下持續10秒)，並在步驟方塊110形成矽化物以提供圖1所示之 元件20。更詳細而言，該矽化物可為TiSi2(例如沉積鈦、植入鍺、在690℃溫度下進行RTA、選擇性剝離，然後在750℃溫度下進行RTA)。
圖12A及圖12B為分別形成與閘極層36’平行和垂直之矽化物後之元件結構之剖視圖。在該些圖式中，以雜點繪示的非單晶縱樑82’、83’表示其已被摻雜了通道阻絕植入物。應注意的是，源極/汲極區中矽凹入(recess)之深度將取決於過蝕刻的量，該過蝕刻係用於去除因使用較大主動區通道阻絕光罩而在STI凹陷與STI邊緣中造成之非單晶縱樑及未蝕刻凸舌82’、83’。另外，熟習本發明所屬技術領域者當可理解，過多的凹入可能會使RSD串聯電阻增加或讓源極/汲極與LDD區之間失去接觸。因此，該些凹入的深度可能需要視所給定之植入進行調整。
在上述製作流程中，遮蔽NFET與PFET、蝕刻STI區80’、81’上方之非單晶矽86’、87’，和通道阻絕植入等步驟係於閘極氧化前進行。茲參照圖9至圖11說明一替代製作流程，其修改上述方法以使非單晶矽86’、87’蝕刻在間隔物蝕刻步驟(步驟方塊108’)之後進行。另外，此替代製作流程亦在閘電極層36”上方使用氧化物或氮化物頂蓋薄膜78”(圖10B)以保護閘極多晶矽，避免其在非單晶矽86”、87”蝕刻期間被蝕刻。
在乾蝕刻(步驟方塊92’)後，於步驟方塊120’進行一清潔步驟(SPM/200：1，HF(50Å)/RCA)，接著進行HF預清潔(100：1)約一分鐘。在此示例中，NFET與PFET光罩沉積步驟(步驟方塊96’及步驟方塊99’)係使用較大混合光阻劑光罩(圖10A)。此外，在非單晶矽閘電極層36”沉積(步驟方塊104’)後，圖示之方法包括一NSD光罩步驟(步驟方塊122’)，接著在步驟方塊123’及步驟方塊124’進行N+型閘極植入及頂蓋氧化物沉積。其他與上述方法相異之流程包括在步驟方 塊125’蝕刻位於STI區80”、81”上面的非單晶矽86”、87”(例如300Å)，接著在步驟方塊126’蝕刻頂蓋氧化物層(其對矽具有高選擇性)。其餘製程步驟在此未提及者，係與前文參考圖4所討論者類似。
茲參考圖13A及圖13B說明另一替代製作流程。此製作流程使用一常規較大AA光罩以蝕刻位於STI區80'''、81'''上之非單晶矽86'''、87'''，接著透過二獨立之光罩步驟賦予凸舌開口(tab opening)圖案。更詳細而言，其係使用NFET通道阻絕光罩130n'''及PFET通道阻絕光罩130p'''(圖13B)。在NFET與PFET光罩步驟後，接著進行通道阻絕植入步驟以摻雜凸舌開口中之非單晶矽。前述步驟可於閘極氧化前進行。
應了解的是，上述示例性之製作流程有利地允許在生長閘極氧化物前，先蝕刻位於STI區上之非單晶半導體材料。此外，以適當能量及劑量植入之通道阻絕植入物可電中和(electrically neutralize)來自鄰接源極區與汲極區之摻雜物，避免其擴散至任何未蝕刻之超晶格縱樑中，該些超晶格縱樑係不經意隱藏在STI氧化物上非單晶矽的主動區邊緣或凸舌的STI凹陷中，其因較大的主動區光罩而包圍主動區。當然，應了解的是，除了上述示例中提及的材料和製作流程參數外，在不同的實施方式中也可使用其他合適的材料及參數。
MOSFET 20通道區所用改進材料或結構所具有之能帶結構，其電子及/或電洞之適當導電性有效質量之值，實質上小於下文所述之對應於矽之值。參考圖14及圖15，超晶格25所具有之結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。如前所述，超晶格25包含複數個堆疊排列之層群組45a-45n，如圖14之示意剖視圖所示。
如圖所示，超晶格25之每一層群組45a-45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a-46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖14中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。換言之，在相鄰的層群組45a-45n中相對之基底半導體單層46係以化學方式鍵結在一起。舉例而言，在矽單層46的情況下，單層群組46a之半導體單層較上端或頂端中的某些矽原子，會與群組46b較下端或底端之單層中的矽原子共價鍵結。這會使晶格即使在有非半導體單層(例如氧單層)存在的情況下，仍可透過這些層群組延續下去。當然，熟習本發明所屬技術領域者當可理解，相鄰群組45a-45n之相對之矽層46間將不會有完整或純粹的共價鍵結，因為該些層之每一層中的某些矽原子會被鍵合至非半導體原子(即本示例中的氧)。
在其他實施方式中，使用超過一個非半導體單層是可能的。舉例而言，能帶修改層50中的非半導體單層數目較佳者可少於約5個單層，從而提供所需要之能帶修改特性。
應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如半導體)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，能帶修改層50與相鄰之基底半導體部份46a~46n，可使超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向 即正交於堆疊方向。該能帶修改層50亦可使超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。如上所述，該結構也有利地提供超晶格25垂直上下方多層間之摻雜物及/或材料滲透或擴散之阻擋，以及載子流動之阻擋。
本發明之理論亦認為，包含超晶格25之半導體元件可因為較原本為低之導電性有效質量，而提供較高之電荷載子遷移率。當然，不需要在每種應用方式中用到所有上述超晶格25特性。舉例而言，某些應用可以只使用超晶格25之摻雜物阻擋/絕緣特性或其增強之遷移率，其他應用可同時使用兩者，熟習本發明所屬技術領域者當能理解。
超晶格25可在其上部層群組45n上面設有一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。其他厚度亦可使用。
每一基底半導體部分46a~46n可包含由IV族半導體、III-V族半導體及II-VI族半導體所組成之群組中選定之一基底半導體。當然，IV族半導體亦包含IV-IV族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據之單層。舉例來說，參照圖15之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4/1重複結構。氧原子之可能位置僅有一半被佔據。
在其他實施方式及/或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，就一超晶格而言，例如矽/氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。圖14及圖15所示之矽/氧4/1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4/1矽/氧超晶格之計算後導電性有效質量則為0.12，兩者之比為 0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4/1矽/氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。在垂直於層群組的方向上具有降低的載子遷移率也可能是有益的。
超晶格25之4/1矽/氧實施方式之較低導電性有效質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。在一些實施例中，舉例而言當超晶格是為了在元件20中提供通道的一部分時，摻雜部分之超晶格25是特別適合的。在其他實施例中，較佳者為根據其在元件中的位置而使超晶格25的一個或多個層群組45實質上無摻雜。
茲另參考圖16說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3/1/5/1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽/氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖16中其他元件在此未提及者，係與前文參考圖14所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格25之每一基底半導體部份46a-46n可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些 基底半導體部份46a-46n可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份46a-46n可為相異數目之單層之厚度。
圖17A-17C呈現應用密度功能理論(Density Functional Theory,DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖17A呈現主體矽(以實線表示)及圖14之4/1矽/氧超晶格25(以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4/1矽/氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然圖中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4/1矽/氧結構之適當反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4/1矽/氧結構之導帶最小值係位於G點，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4/1矽/氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖17B呈現主體矽(實線)及圖14之4/1矽/氧超晶格25(虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖17C呈現主體矽(實線)及圖16之5/1/3/1矽/氧超晶格25’(虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5/1/3/1矽/氧結構之對稱性，在方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5/1/3/1矽/氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5/1/3/1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
茲另參考圖18至圖24說明在形成STI結構201後於底材200上沉積無光罩超晶格之實施方式。如圖18所示，稍厚之氮化物阻擋層203形成在底材200上的氧化物層202上方，且鄰接被氧化物充滿之STI區的部分，該STI區201是在CMP步驟後所留下。更詳細而言，剩餘的STI區201可具有約450Å或更大之厚度X，而不是習知約200Å之厚度。如以下將進一步討論之內容，此額外厚度可留下足夠空間以在其上形成超晶格225及保護氧化物204。氧化物層202覆蓋氮化物層203下方之底材200，且一般而言應夠厚以作為CMP阻擋層使用(例如厚度大於150Å，更詳細而言大於200Å)。熟習本發明所屬技術領域者應當理解設置CMP停止點以形成稍厚之氮化物層203之合適技術。
如圖19所示，接著可從底材200剝離氧化物層202及氮化物層203，並在其上形成超晶格層225。此外，可在超晶格層225上方熱生長或沉積保護氧化物層204。
如圖20及圖21所示，可在該結構上沉積一氮化物層205至，舉例而言，約450Å之厚度。如圖21所示，可透過化學機械研磨法將氮化物層205平坦化至氧化物層204處。如圖所示，在CMP期間可能會發生一些凹陷，但這不會影響製程，熟習本發明所屬技術領域者當可理解。
如圖22所示，可使用，舉例而言，電漿蝕刻去除STI結構201頂部之超晶格層225和氧化物層204。在一些實施方式中，前述CMP步驟也可用於去除STI結構201上全部或部分之超晶格層225和氧化物層204。
超晶格層225之暴露邊緣可進行再氧化(re-oxidized)以形成氧化物頂蓋206，從而產生圖23所示之中間結構。根據一示例性方法，可對矽縱樑或「晶鬚」(whisker)207進行濕蝕刻(例如目標不完全蝕刻，target under-etch)，接著進行濕式氧化。接著，可透過諸如濕蝕刻法去除氮化物層205的剩餘部分，以留下如圖24所示之結構。熟習本發明所屬技術領域者當可理解，其可進行植入穿過氧化物等以接續該製作過程。如有需要，可在去除硬質氧化物光罩後進行平滑回火，以去除STI結構201邊緣上的剩餘超晶格薄膜縱樑207，熟習本發明所屬技術領域者當可理解。
與前文參考圖21所述CMP步驟相異之一替代方案為重新使用STI光阻劑光罩210’並以濕蝕刻氮化物205’，如圖25所示。在此情況下，可去除該光阻劑光罩210’，並使用電漿蝕刻以暴露原本的STI 201’，如圖26之虛線211’所繪示。這將使上述之縱樑207，以及底材200’的底層部分、相鄰的超晶格225’部分 和氧化物層204’部分被去除，如圖27之「疊合偏差」(registration error)所示。接著可對暴露出的矽(即底材200’及超晶格225’尾端)進行再氧化以形成氧化物層212’，並接著進行氮化物層205’的濕式剝離及後續加工步驟。亦可進行一去光(deglazing)步驟，以蝕刻去除氧化物層212’。
茲參考圖28至圖34、下文之表格及圖35之流程圖360說明另一後STI超晶格集成方法(post-STI superlattice integration scheme)。初始處理步驟可包括一STI製程(步驟方塊361)以在底材200”中形成STI區201”，接著穿過墊氧化物(例如150Å之墊氧化物)進行深井植入213”及臨界電壓(VT)植入214”(步驟方塊362)。其他初始處理步驟可包括步驟方塊363之氧化物乾蝕刻(例如120Å)、硫酸/過氧化物混合物之SPM/RCA清潔(步驟方塊364)、SC1/HF預清潔(步驟方塊365)、超晶格225”沉積(步驟方塊366)及步驟方塊367之清洗(incoming clean)。
如圖所示，本發明之方法更包括在超晶格225”上方形成一薄的氧化物/氮化物硬光罩215”，以及一較小尺寸(undersized)反向主動區(AA)光阻劑光罩211”，如圖28A至圖28B所示。然後，光阻劑光罩211”以外的超晶格225”的部分可使用，舉例而言，電漿蝕刻加以蝕去(步驟方塊370)，接著在步驟方塊371剝離該光阻劑光罩，如圖29所示。用於清除STI區201”上非晶薄膜的過蝕刻的量可設為零，因為後續的環體氧化(ring oxidation)步驟將使未被遮蔽的剩餘超晶格225”矽轉換成氧化物。
接著，於步驟方塊372，可環繞AA區形成一主動區環體氧化物216”(詳見圖30)，然後進行氧化物/氮化物硬光罩215”之剝離(步驟方塊373)、預先閘極清潔(步驟方塊374)，並在步驟方塊375形成閘極介電質217”(例如20Å)(詳見圖31)。閘極介電層217”與STI區201”頂部間之階差(step height)係根據 光罩遮蔽氧化步驟、預先閘極清潔量和初始STI凸出/凹入等條件而設定。接著，在步驟方塊376可形成一多晶矽閘電極層218”(詳見圖32A、圖32B)，然後進行N+/P+型多晶矽光罩遮蔽及N+/P+型閘極植入(步驟方塊377至步驟方塊380)。圖32A為垂直於閘極之剖視圖，而圖32B為之在STI區201”邊緣沿著閘極之剖視圖。
本發明的方法可更包含於步驟方塊381進行硬光罩CVD氧化物沉積、閘極圖案化及蝕刻(步驟方塊382)，以及在步驟方塊383形成間隔物219”(例如125Å之氧化物)。接著，在步驟方塊384，可形成環形植入物221”和源極/汲極延伸區植入物220”(詳見圖33)，然後形成氮化物或氧化物間隔物222”(步驟方塊385)，該間隔物之形成可視STI區201”邊緣處之缺口深度是否過大而選擇性進行。在步驟方塊386，如有必要，可選擇在源極/汲極區中蝕刻超晶格225”，接著形成屏蔽氧化物(步驟方塊387)，並於步驟方塊388形成源極/汲極植入物223”。
如圖所示，後續加工步驟包括濕蝕刻頂蓋氧化物(步驟方塊389)、RTA/尖峰回火(步驟方塊400)及矽化物製程401以形成源極/汲極和閘極矽化物區226”,227”(詳見圖34)。更詳細而言，圖34為垂直於閘極並顯示STI區201”邊緣之剖視圖，其中虛線箭頭代表依據本實施方式之較小的矽化物至接面(silicide-to-junction)距離(~355Å以下)，此將在下文進一步討論。
應注意避免STI 201”邊緣處的缺口深度，否則可能造成源極/汲極接面至井短路(垂直)。垂直方向比較沒有問題，但對角角度在矽化物形成後可能具有最大風險。一般而言，接面假設是~1000A。此外，應小心避免缺口區中 的矽化物於閘極下方短路(厚氧化物區下方之源極至汲極)。本發明可有利地減少閘極下方的源極至汲極摻雜物擴散。
以下表格包括示例性之表面位置，其相對於上述方法之原始表面，但應了解的是，在不同的實施例中可使用不同的尺寸。如上所述，在本示例中的淨結果是使用本發明之方法可沿著STI區201”邊緣在源極/汲極的表面至接面(surface-to-junction)位置獲得約355A(垂直)的薄化。
Figure 107128841-A0305-02-0026-5
上述方法可有利地在STI邊緣的閘極下方製作出相對厚的氧化物。另外，此方法也可用於雙閘極製程，因為雙閘極之步驟可用於上述氧化環體步驟中。這種方法的好處是在有需要時可不使用非晶矽凸舌、不使用CS植入，且可能減少超晶格225”薄膜蝕刻的次數(亦即，若超晶格薄膜被留在源極/汲極區中，則只需蝕刻一次而不是兩次)。
熟習本發明所屬技術領域者可受益於本說明書揭示之內容及所附圖式而構思出各種修改及其他實施方式。因此，應瞭解的是，這些修改及實施方式均落入以下申請專利範圍所界定之範疇。
20‧‧‧半導體元件
21‧‧‧底材
22‧‧‧源極延伸區
23‧‧‧汲極延伸區
25‧‧‧超晶格
26‧‧‧源極區
27‧‧‧汲極區
30‧‧‧源極矽化物層
31‧‧‧汲極矽化物層
34‧‧‧矽化物層
35‧‧‧閘極
36‧‧‧閘電極層
37‧‧‧閘極介電層
40、41‧‧‧側壁間隔物
42、43‧‧‧環形植入區
80、81‧‧‧STI區
82、83‧‧‧非單晶縱樑

Claims (10)

  1. 一種用於製作一半導體元件之方法，該方法包括：使用一STI光阻劑光罩在一半導體底材中形成隔開的第一及第二淺溝槽隔離(STI)區；形成設置在該半導體底材上且在該第一與第二STI區之間延伸之一超晶格，該超晶格包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層；形成一第一半導體縱樑，使其在該超晶格之第一端與該第一STI區之界面包含一非單晶體；再次使用該STI光阻劑光罩以移除該第一半導體縱樑；以及在該超晶格上方形成一閘極。
  2. 如申請專利範圍第1項之方法，其中該第一半導體縱樑在該超晶格之上。
  3. 如申請專利範圍第1項之方法，其更包括摻雜該半導體底材及該超晶格，以在當中界定出隔開的源極區與汲極區。
  4. 如申請專利範圍第1項之方法，其更包括形成一第二半導體縱樑，使其鄰接該超晶格之第二端與該第二STI區之界面。
  5. 如申請專利範圍第1項之方法，其中該第一半導體縱樑分隔該超晶格之第一端與該第一STI區。
  6. 如申請專利範圍第1項之方法，其中該半導體縱樑包含非晶矽。
  7. 如申請專利範圍第1項之方法，其更包括在該第一半導體縱樑中植入一通道阻絕摻雜劑。
  8. 如申請專利範圍第1項之方法，其更包括在該第一半導體縱樑上形成一氧化物頂蓋。
  9. 如申請專利範圍第1項之方法，其中該些基底半導體單層包含矽。
  10. 如申請專利範圍第1項之方法，其中該至少一非半導體單層包含氧。
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