JPS61145820A - 半導体薄膜材料 - Google Patents

半導体薄膜材料

Info

Publication number
JPS61145820A
JPS61145820A JP26941584A JP26941584A JPS61145820A JP S61145820 A JPS61145820 A JP S61145820A JP 26941584 A JP26941584 A JP 26941584A JP 26941584 A JP26941584 A JP 26941584A JP S61145820 A JPS61145820 A JP S61145820A
Authority
JP
Japan
Prior art keywords
gap
thin film
super
light
lattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26941584A
Other languages
English (en)
Inventor
Hideaki Iwano
岩野　英明
Hiroyuki Oshima
弘之 大島
Hiroshi Komatsu
博志 小松
Yoshifumi Tsunekawa
吉文 恒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26941584A priority Critical patent/JPS61145820A/ja
Publication of JPS61145820A publication Critical patent/JPS61145820A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は超格子構造を用いた半導体材料に関するもので
ある。
〔従来の技術〕
従来の硅素（Ｓｌ）を用いた超格子構造の半導体材料は
例えば文献＠Ｅｌｅｃｔｒｏｎ　ｍｏｂｉｌｉｔｙｅｎ
ｈａｎｃｅｍｅｎｔ　　ｉｎ　　ｅｐｉｔａｚｉｔｉａ
ｌ　ｍｕｌｔｉｌａｙｅｒ　　Ｓｉ　−８ｉ４−一＠Ｚ
　ａｌｌｏｙ　ｆｉｌｍｓ　ｏｎ　（１００）　８１　
’　Ａｐｐｌ　−Ｐｈｙｓ、Ｌｅｔｔ　、４１　（５）
　、　１９８２　　に見られるように、Ｓｌのエピタキ
シャル薄層と８１１−２Ｇｅｌ：混晶系薄層を順次積層
して形成されるものでありた。このような超格子構造を
形成することにより電子及び正孔の有効質量は減少し、
界面方向の移動度が増大することが示されている。また
Ｓｌのバンド間遷移は間接型であるのに対して！１ｉ−
８ｉｌ−。
Ｇｏ、ｒ　超格子構造には直接型遷移の遷移確率が増え
、発光素子としての可能性も期待できる。
〔発明が解決しようとする問題点〕
しかし前述の従来技術では、Ｓｉと５１ｘ−ｘＧｅ＆　
を積層するためには、両層の格子定数が近くなければ、
結晶性のよい薄膜成長はできない。
即ち、Ｓｌの格子定数は！Ｌ４３Ｘであり、Ｇｏの格子
定数は翫６６にであるので、格子整合させるためにはＳ
　ｉ　１−２ＧＵ　Ｚ　層の２の値はｎ、１以下程度に
おさえる必要がある。その為、ＳｌとＳ　ｉ　１−。
Ｇｏｓ　　の間のバンドギャップ差が小さくなり、超格
子構造にする効果が小さいという問題点を有する。
また８　Ｌ　−８４１１−２Ｇ＠Ｚ超格子構造では発光
性も期待できるが、発光したとしても発光波長はｔ１μ
馬より長く、可視域波長の光は発光しないという問題点
を有する。
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、結晶性が良く、高移動度であり
、可視域の発光性の高い半導体材料を提供するところ′
にある。
〔問題点を解決するための手段〕
本発明の半導体材料は、超格子構造の半導体材料におい
て８１から成る単結晶薄膜とガリウムリン（Ｇａｐ）化
合物からなる単結晶薄膜を順次積層して超格子構造とし
たことを特徴とする。
〔作用〕 本発明の上記の構成によれば、ｓｌの格子定数は五４３
裏であり、ＧａＰの格子定数は翫４５１であり、格子定
数が近接している為、超格子構造を形成する際、Ｓｉ層
、ＧａＰ層が結晶性よくエピタキシャル成長をする。更
に、Ｓｌのバンドギャップ（ｍＧ）は、１．１２ｅＶ、
％ＧａＰのＩＣＧは２．２４・Ｖであるため超格子間の
ＫＧの差が大きく、移動度の増大、発光遷移確率の増大
が大きい更に、８１．ＧａＰ共に間接遷移型の半導体で
あるが、超格子構造とすることで両層のバンドで直接遷
移型の遷移確率が生じ、１．１μ溝の波長の赤外域の発
光、５ｓｓｏＸの波長の可視域の発光をし得る発光材料
となる。
〔実施例〕
第１図は、本発明の実施例における８ｌ−ＧａＰ超格子
構造の半導体材料の主要断面図である。
単結晶シリコン基板（１０１）の（１００）面上に、　
５ｉ（１０２）、ＧＮＰ（１０！Ｓ）を交互に順次積層
する。！ｉｉ、ＧｓＰの層厚は薄い程望ましいが、材料
製作可能な範囲では、約２０Ｘ以上である。薄膜の製造
方法には、化学ｆｆｉ論的気相成長方法（ＣＶＤ法）を
用い、反応管の中に設置された８１基板を誘導加熱法に
より、９００〜１０００℃に加熱し、最初にモノシラン
（１９１１ｉ、）ガスを、水素、ヘリウム、アルゴン等
のキャリアガスと共に反応管中に導入し、１９１薄膜を
エピタキシャル成長させる。所定時間後、（０１！、　
）、Ｇａｗ　（０＊Ｈｍ　）ｓ　Ｇａ等の有機金属化合
物の蒸気と、アオスフィン（ＰｌＫｍ）ガスあるいは（
Ｏｌｉｓ）ｓ″Ｐ等の有機金属化合物の蒸気を水素、ヘ
リウム、アルゴン等のキャリアガスと共に反応管中に導
入しＧａＦ薄膜をエピタキシャル成長させる。これらの
操作を交互に繰り返して超格子構造の半導体材料を得る
ことができた。この薄膜は格子整合しているために、結
晶性が良く、電子移動度が単層の８１薄膜の移動度の１
０倍程度に向上した。更に、フォトルミ車ッセンス法に
よる測定では１．１２・Ｖ、の赤外部と、２．２４ｅＶ
の可視部の発光が１４８され１間接遷移型から直接遷移
型へのバンド間遷移の確率が発生したことが確認された
。これらのことは、１ｇ２図に示すように、膜厚方向に
、バンドギャップの繰り返しが生ずるため、結晶の対称
性が膜厚方向に低下するため、直接遷移型の一〇 バンドが混合するために起こり、更に電子の有効質量が
減少するためである。
〔発明の効果〕
以上述べたように本発明によれば、次のような効果を有
する。
ＮＥｌに、高移動度の半導体材料を８１基板を用いて製
造できることである。従って、高速の集積回路の製造に
適し、且つ結晶性が良く安価な基板材料であるので、歩
留シ、製造コストの面でも有利である。
ｔｓ２に、格子定数の合った半導体を積層するので成長
膜の結晶性が良く、このことがデバイスに形成した場合
の信頼性を著しく向上させる。
第５に、ＳｉとＧａＰという共に間接遷移型の半導体を
積層して、直接遷移型の遷移確率を発生させるので、単
層Ｓ１あるいは単層ＧａＰでは決りして得られなかりた
発光素子が製造可能となり更に、更に１素子で赤外と可
視部の２波長の発光が可能である。その為、本発明の半
導体材料は、赤外、可視部共に発振可能な半導体レーザ
を製造一 することが可能である。
【図面の簡単な説明】
第１図は本発明の牛導体材料の一実施例を示す主要断面
図。 第２図（α）（ｊ）は第１図の牛導体材料のエネルギー
バンド構成図。 （１０１）−・・・・・シリコン基板 （１０２）−−−−−・Ｓ１工ピタキシヤル層（１０Ｓ
　）・−−−−−Ｇ　ａ　Ｐ：ｃビタキシャル層（２０
１）・・・・−ＧａＰ伝導帯エネルギーレベル（２０２
）・・・・・−８ｉ伝ａｌｌｆＪ−ネルギーレベル（２
０５ン・・・・・・Ｇ　ａ　Ｐ（ｉｌｌｉｉｇ子帯エネ
ルギーレベル （２０４）・・・・・・Ｓｉ価電子帯エネルギーレベル
以上

Claims (1)

    【特許請求の範囲】
  1. 第１の半導体薄膜と第２の半導体薄膜を順次積層して成
    る超格子構造の半導体材料において、前記第１の半導体
    薄膜が硅素から成る単結晶薄膜であり、前記第２の半導
    体薄膜がガリウムリン化合物から成る単結晶薄膜である
    ことを特徴とする半導体薄膜材料。
JP26941584A 1984-12-20 1984-12-20 半導体薄膜材料 Pending JPS61145820A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26941584A JPS61145820A (ja) 1984-12-20 1984-12-20 半導体薄膜材料

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26941584A JPS61145820A (ja) 1984-12-20 1984-12-20 半導体薄膜材料

Publications (1)

Publication Number Publication Date
JPS61145820A true JPS61145820A (ja) 1986-07-03

Family

ID=17472096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26941584A Pending JPS61145820A (ja) 1984-12-20 1984-12-20 半導体薄膜材料

Country Status (1)

Country Link
JP (1) JPS61145820A (ja)

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897367A (en) * 1988-03-18 1990-01-30 Fujitsu Limited Process for growing gallium arsenide on silicon substrate
US4963508A (en) * 1985-09-03 1990-10-16 Daido Tokushuko Kabushiki Kaisha Method of making an epitaxial gallium arsenide semiconductor wafer using a strained layer superlattice
US6830964B1 (en) 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US6833294B1 (en) 2003-06-26 2004-12-21 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7018900B2 (en) 2003-06-26 2006-03-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9972685B2 (en) 2013-11-22 2018-05-15 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US10381242B2 (en) 2017-05-16 2019-08-13 Atomera Incorporated Method for making a semiconductor device including a superlattice as a gettering layer

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963508A (en) * 1985-09-03 1990-10-16 Daido Tokushuko Kabushiki Kaisha Method of making an epitaxial gallium arsenide semiconductor wafer using a strained layer superlattice
US4897367A (en) * 1988-03-18 1990-01-30 Fujitsu Limited Process for growing gallium arsenide on silicon substrate
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US7435988B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US6878576B1 (en) 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US6891188B2 (en) 2003-06-26 2005-05-10 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6897472B2 (en) 2003-06-26 2005-05-24 Rj Mears, Llc Semiconductor device including MOSFET having band-engineered superlattice
US6927413B2 (en) 2003-06-26 2005-08-09 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6952018B2 (en) 2003-06-26 2005-10-04 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US7018900B2 (en) 2003-06-26 2006-03-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7034329B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US7033437B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7071119B2 (en) 2003-06-26 2006-07-04 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US7109052B2 (en) 2003-06-26 2006-09-19 Rj Mears, Llc Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
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US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9941359B2 (en) 2015-05-15 2018-04-10 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US10381242B2 (en) 2017-05-16 2019-08-13 Atomera Incorporated Method for making a semiconductor device including a superlattice as a gettering layer
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