CN111937119A - 包括具有超晶格的增强接触结构的半导体器件和相关方法 - Google Patents

包括具有超晶格的增强接触结构的半导体器件和相关方法 Download PDF

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CN111937119A
CN111937119A CN201980021335.2A CN201980021335A CN111937119A CN 111937119 A CN111937119 A CN 111937119A CN 201980021335 A CN201980021335 A CN 201980021335A CN 111937119 A CN111937119 A CN 111937119A
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semiconductor
superlattice
metal
trench
semiconductor device
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R·J·史蒂芬森
R·伯顿
D·康奈利
N·W·寇迪
R·J·梅尔斯
D·筹托夫
E·特洛特曼
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Atomera Inc
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Abstract

半导体器件(30)可包括其中具有沟槽(32)的半导体衬底(31)，和至少部分覆盖沟槽的底部和侧壁部分的超晶格衬层(25)。超晶格衬层可包括堆叠的层组，其中每个层组包括限定了基础半导体部分的堆叠的基础半导体单层，和被约束在相邻的基础半导体部分的晶体晶格内的至少一个非半导体单层。半导体器件还可包括在超晶格衬层上并且具有被超晶格衬层约束在其中的掺杂剂(34)的半导体盖层(33)，和在沟槽内的传导体(36、37)。

Description

包括具有超晶格的增强接触结构的半导体器件和相关方法
技术领域
本公开内容大体上涉及半导体器件，并且更特别地涉及具有增强接触结构的半导体器件和相关方法。
背景
提出了结构和技术来增强半导体器件的性能，例如通过增强载流子的迁移率。例如，Currie等人的美国专利申请号2003/0057416公开硅、硅-锗和弛豫硅的应变材料层并且应变材料层还包括无杂质区域(否则将引起性能劣化)。在上部硅层中产生的双轴应变改变载流子迁移率，使较高速度和/或较低功率的器件成为可能。Fitzgerald等人已公布的美国专利申请号2003/0034529公开了也基于类似应变硅技术的CMOS逆变器。
Takagi的美国专利号6,472,685B2公开了半导体器件，其包括夹在硅层之间的硅和碳层，使得第二硅层的导带和价带接收拉伸应变。具有较小有效质量并由施加至栅极的电场引起的电子被限制在第二硅层中，因此声称n-通道MOSFET具有较高的迁移率。
Ishibashi等人的美国专利号4,937,204公开了超晶格，其中交替和外延生长多个层(小于八个单层)，并且含有分数(fractional)或二元或二元化合物半导体层。主电流的方向与超晶格的层垂直。
Wang等人的美国专利号5,357,119公开了通过在超晶格中减小合金散射而实现的具有较高迁移率的Si-Ge短周期超晶格。按照这些方法，Candelaria的美国专利号5,683,934公开了包括通道层的增强迁移率MOSFET，所述通道层包含硅和第二材料的合金，第二材料以将通道层置于拉伸应力下的百分比置换存在于硅晶格中。
Tsu的美国专利号5,216,262公开了量子井结构，其包含两个阻隔区域和夹在阻隔体之间的薄的外延生长半导体层。每个阻隔区域由SiO2/Si的交替层组成，具有通常在2至6个单层的范围内的厚度。硅的厚得多的部分夹在阻隔体之间。
也是Tsu的题目为“Phenomena in silicon nanostructure devices”并在2000年9月6日由Applied Physics and Materials Science&Processing第391-402页在线公布的文章公开了硅和氧的半导体-原子超晶格(SAS)。公开Si/O超晶格可用在硅量子和发光器件中。特别地，构造并测试了绿色电致发光二极管结构。二极管结构中的电流是竖直的，即与SAS的层垂直。公开的SAS可包括由吸附物质例如氧原子和CO分子分开的半导体层。将超过吸附的氧单层的硅生长描述为具有相当低缺陷密度的外延。一种SAS结构包括1.1nm厚的硅部分(其为约八个原子层的硅)，且另一种结构具有两倍的这个硅厚度。在Physical ReviewLetters，第89卷，第7期(2002年8月12日)中公布的Luo等人题目为“Chemical Design ofDirect-Gap Light-Emitting Silicon”的文章还讨论了Tsu的发光SAS结构。
Wang、Tsu和Lofgren已公布的国际申请WO 02/103,767 A1公开了薄硅和氧、碳、氮、磷、锑、砷或氢的阻隔结构单元，由此将垂直流过晶格的电流减小大于四个数量级。绝缘层/阻隔层允许紧挨着绝缘层沉积低缺陷的外延硅。
Mears等人已公布的英国专利申请2,347,520公开了非周期光子带隙(APBG)结构的原理可适用于电子带隙工程学。特别地，该申请公开了可调整材料参数例如能带最小值位置、有效质量等从而产生具有期望带结构特性的新的非周期材料。公开了其它参数例如电导率、热导率和电介常数或磁导率也能够被设计在材料中。
此外，Wang等人的美国专利号6,376,337公开了用于生产半导体器件的绝缘或阻隔层的方法，其包括沉积硅和至少一种另外的元素的层在硅衬底上，由此沉积层基本上没有缺陷使得可将基本上没有缺陷的外延的硅沉积在沉积层上。或者，一种或多种元素的单层(优选包含氧)吸附在硅衬底上。夹在外延的硅之间的多个绝缘层形成阻隔复合材料。
尽管存在这样的途径，但是对于在某些应用中使用先进半导体加工技术而言进一步的改进是期望的。
概述
半导体器件可包括其中具有沟槽(trench)的半导体衬底，和至少部分覆盖沟槽的底部和侧壁部分的超晶格衬层。超晶格衬层可包括多个堆叠的层组，其中每个层组包含限定了基础半导体部分的多个堆叠的基础半导体单层，和被约束在相邻的基础半导体部分的晶体晶格内的至少一个非半导体单层。半导体器件还可包括在超晶格衬层上并且包含被超晶格衬层约束在其中的掺杂剂的半导体盖层，和在沟槽内的传导体。
传导体可包括与半导体盖层相邻并包含第一金属的金属衬层，和与金属衬层相邻、填充沟槽并包含第二金属的金属体。此外，传导体还可包含硅化物。通过示例的方式，半导体盖层可包含硅，第一金属可包含钛、钴和镍中至少一种，和第二金属可包含钨。
按照示例实施方案，传导体可限定源/漏接触。通过示例的方式，基础半导体单层可包含硅，和至少一个非半导体单层可包含氧。还通过示例的方式，掺杂剂可包含硼、砷和磷中至少一种。
另一方面涉及用于制备半导体器件的方法，其可包括在半导体衬底中形成沟槽，和形成覆盖沟槽的底部和侧壁部分的超晶格衬层。超晶格衬层可包括多个堆叠的层组，其中每个层组包含限定了基础半导体部分的多个堆叠的基础半导体单层，和被约束在相邻的基础半导体部分的晶体晶格内的至少一个非半导体单层。该方法还可包括形成在超晶格衬层上并包含被超晶格衬层约束在其中的掺杂剂的半导体盖层，和在沟槽内形成传导体。
在示例实施方案中，形成传导体可包括形成与半导体盖层相邻并包含第一金属的金属衬层，和形成与金属衬层相邻、填充沟槽并包含第二金属的金属体。形成传导体还可包括将金属衬层退火。在又一个示例实施方案中，将金属衬层退火可至少部分消耗超晶格衬层。通过示例的方式，半导体盖层可包含硅，和第一金属可包含钛、钴和镍中至少一种。此外，第二金属可包含例如钨。
该方法还可包括在凹槽内形成传导体前清洁半导体盖层。在示例实施方案中，传导体可限定源/漏接触。通过示例的方式，基础半导体单层可包含硅，和至少一个非半导体单层可包含氧。还通过示例的方式，该方法还可包括使用在2-20keV范围内的注入能量在半导体盖层中注入掺杂剂，并且掺杂剂可包含硼、砷和磷中至少一种。
附图简要描述
图1是用于在按照示例实施方案的半导体器件中使用的超晶格的大幅放大的示意横截面图。
图2是图1中显示的超晶格的一部分的透视示意原子图。
图3是按照示例实施方案的超晶格的另一实施方案的大幅放大的示意横截面图。
图4A是由现有技术中的大块硅和如图1-2中显示的4/1Si/O超晶格的γ点(G)计算的带结构图。
图4B是由现有技术中的大块硅和如图1-2中显示的4/1Si/O超晶格的Z点计算的带结构图。
图4C是由现有技术中的大块硅和如图3中显示的5/1/3/1Si/O超晶格的γ点和Z点计算的带结构图。
图5和6是说明分别在形成钨塞之前和之后在包括超晶格沟槽衬层的半导体器件中形成沟槽接触的横截面图。
图7a-7c是说明包括超晶格衬层的平面源/漏栅接触构造的示意横截面图。
图8是在硅化工艺过程中部分消耗了超晶格沟槽衬层的图6的沟槽接触的横截面图。
图9是说明按照示例实施方案的制备半导体器件的方法的流程图。
详细描述
现在将在下文中参考其中显示了示例实施方案的附图更完整地描述示例实施方案。然而，实施方案可以许多不同的形式实施并且不应被解释为限制于本文列出的具体实施例。相反，提供这些实施方案使得本公开内容将是完全和完整的。相同的数字始终指代相同的要素，并且使用撇号来表示不同实施方案中的类似要素。
一般来讲，本公开内容涉及通过使用增强半导体超晶格在平坦和竖直半导体器件中形成增强接触结构从而在期望的接触区域中有利地约束接触掺杂剂。增强半导体超晶格在本公开内容中还称作“MST”层或“MST技术”。
更特别地，MST技术涉及先进半导体材料例如以下进一步描述的超晶格25。申请人从理论上说明(不希望受束缚于此)：如本文描述的某些超晶格减小载流子的有效质量并且这由此导致较高的载流子迁移率。使用文献中的各种定义来描述有效质量。作为有效质量改进的量度，申请人对于电子和空穴分别使用“传导率倒易有效质量张量”
Figure BDA0002696031460000051
和
Figure BDA0002696031460000052
定义如下：
Figure BDA0002696031460000053
对于电子，和
Figure BDA0002696031460000054
对于空穴，
其中f是费米-狄拉克分布，EF是费米能，T是温度，E(k,n)是在对应于波矢量k和第n能带的状态下电子的能量，指数i和j是指笛卡尔坐标x、y和z，在布里渊区(B.Z.)内进行积分，并且在能量分别大于和小于电子和空穴的费米能的能带内求和。
申请人对传导率倒易有效质量张量的定义是这样的，材料的传导率的张量分量越大，传导率倒易有效质量张量的相应分量的值越大。再次，申请人从理论上说明(不希望受束缚于此)：本文描述的超晶格确立了传导率倒易有效质量张量的值从而增强材料的传导性质，例如通常用于载流子传输的优选方向。适当张量元素的倒数被称作传导率有效质量。换句话说，为了表征半导体材料结构，使用如以上描述并在预期的载流子传输方向上计算的电子/空穴的传导率有效质量来区分改进的材料。
申请人确认了用于在半导体器件中使用的改进材料或结构。更具体地，申请人确认了具有能带结构的材料或结构，对于该能带结构而言电子和/或空穴的适当传导率有效质量显著小于硅的相应值。除了这些结构增强的迁移率特性之外，它们还可以这样的方式形成或使用，使得它们提供压电、热电和/或铁电性质，这些性质有利于在各种不同类型的器件中使用，如将在下面进一步讨论。
现在参考图1和2，材料或结构处于超晶格25的形式，它的结构被控制在原子或分子水平并可使用原子或分子层沉积的已知技术形成。超晶格25包括以堆叠关系布置的多个层组45a-45n，如具体参考图1的示意横截面图可能最好理解。
超晶格25的每个层组45a-45n说明性地包括多个堆叠的基础半导体单层46(限定各自的基础半导体部分46a-46n)和在其上的能带改性层50。为了清楚地说明，能带改性层50在图1中由点画表示。
能带改性层50说明性地包括被约束在相邻基础半导体部分的晶体晶格内的一个非半导体单层。通过“被约束在相邻基础半导体部分的晶体晶格内”意味着来自相对基础半导体部分46a-46n的至少一些半导体原子通过它们之间的非半导体单层50化学结合在一起，如图2中所示。一般来说，通过控制通过原子层沉积技术沉积在半导体部分46a-46n上的非半导体材料的量使这种构造成为可能，使得不是所有的(即小于全部或100％覆盖率)的可用的半导体结合位点被与非半导体原子的结合填充(polulate)，如将在以下进一步讨论。因此，因为半导体材料的另外的单层46沉积在非半导体层50上或上方，新沉积的半导体原子将填充在非半导体单层下方的半导体原子的剩余空缺结合位点。
在其它实施方案中，多于一个这样的非半导体单层可为可能的。应注意本文提到非半导体或半导体单层意指用于该单层的材料如果大批形成则是非半导体或半导体。即，材料例如硅的单个单层可不必表现出与其以大块或相对厚的层形成时的相同性质，如本领域技术人员将理解的那样。
申请人从理论上说明(不希望受束缚于此)：能带改性层50和相邻的基础半导体部分46a-46n引起超晶格25具有在平行层方向上比其它方式会存在的更低的适合于载流子的传导率有效质量。以另一种方式考虑，这种平行方向与堆叠方向正交。能带改性层50还可引起超晶格25具有常见能带结构，其同时还有利地充当在超晶格上方和下方竖直的区域或层之间的绝缘体。
此外，这种超晶格结构还可有利地充当在超晶格25上方和下方竖直的层之间对掺杂剂和/或材料扩散的阻隔。这些性质因此可有利地使超晶格25提供高K-电介质的界面，其不仅减小高K-材料扩散进入通道区域，还可有利地减小不需要的散射效应并改进器件迁移率，如本领域技术人员将理解的那样。
还从理论上说明：包括超晶格25的半导体器件可享有基于比其它方式会存在的更低传导率有效质量的更高载流子迁移率。在一些实施方案中，并且作为本发明实现的能带工程学的结果，超晶格25还可具有可特别有利于例如光电子器件的基本上直接的能带隙。
超晶格25还说明性地包括在上层组45n上的盖层52。盖层52可包含多个基础半导体单层46。盖层52可具有在2至100个之间的基础半导体单层，和更优选在10至50个之间的单层。
每个基础半导体部分46a-46n可包含选自以下的基础半导体：第IV族半导体、第III-V族半导体和第II-VI族半导体。当然，术语第IV族半导体还包括第IV-IV族半导体，如本领域技术人员将理解的那样。更特别地，基础半导体可包含例如硅和锗中至少一种。
每个能带改性层50例如可包含选自以下的非半导体：氧、氮、氟、碳和碳-氧。非半导体通过下一层的沉积还期望是热稳定的从而促进制造。在其它实施方案中，非半导体可为与本领域技术人员将理解的给出的半导体加工相容的另一种无机或有机元素或化合物。更特别地，基础半导体可包含例如硅和锗中至少一种。
应注意术语单层意味着包括单个原子层并且还包括单个分子层。还注意由单个单层提供的能带改性层50还意味着包括其中不是所有的可能位点都被占据(即存在小于全部或100％覆盖率)的单层。例如，特别参考图2的原子图，说明了硅作为基础半导体材料和氧作为能带改性材料的4/1重复结构。在说明的示例中对于氧而言仅一半的可能位点被占据。
在其它实施方案中和/或使用不同的材料，如本领域技术人员将理解的那样，这一半的占据不一定如此。确实，甚至可在这个示意图中看出在给定单层中的氧的单个原子没有沿着平坦平面精确对齐，如原子沉积领域中的技术人员还将理解的。通过示例的方式，优选的占据范围是从约八分之一至二分之一的全部可能的氧位点，但是可在一些实施方案中使用其它数量。
硅和氧目前广泛使用在常规半导体加工中，并因此制造者将容易能够使用如本文描述的这些材料。现在还广泛使用原子或单层沉积。因此，如本领域技术人员将理解的那样，可容易采用和实施按照本发明包括超晶格25的半导体器件。
申请人从理论上说明(不希望受束缚于此)：对于超晶格例如Si/O超晶格，硅单层数应期望为七或更小使得超晶格的能带自始至终是共同的或相对均匀的从而实现期望的优点。对于Si/O在图1和2中显示的4/1重复结构已被建模以表明在X方向上电子和空穴的增强迁移率。例如，对于电子(对于大块硅各向同性)而言计算的传导率有效质量为0.26并且对于4/1SiO超晶格而言在X方向上其为0.12，从而产生比率为0.46。类似地，对于空穴的计算产生对于大块硅而言值为0.36和对于4/1SiO超晶格而言值为0.16，从而产生比率为0.44。
虽然可在某些半导体器件中期望这样的方向优选特征，但是其它器件可受益于在平行于层组的任何方向上迁移率更均匀的提高。如本领域技术人员将理解的那样，还可有益的是对于电子和空穴两者或这些类型的载流子中仅一种而言具有提高的迁移率。
对于超晶格25的4/1SiO实施方案而言较低的传导率有效质量可比将以其它方式出现的传导率有效质量小三分之二，并且这适用于电子和空穴两者。当然，超晶格25还可在其中包含至少一种类型的传导率掺杂剂，如本领域技术人员还将理解的那样。
实际上，现在另外参考图3，现在描述按照本发明具有不同性质的超晶格25’的另一实施方案。在这个实施方案中，说明3/1/5/1的重复模式。更特别地，最低的基础半导体部分46a’具有三个单层且第二低的基础半导体部分46b’具有五个单层。这种模式在整个超晶格25’中重复。能带改性层50’可每个包括单个单层。对于这样的包括Si/O的超晶格25’，载流子迁移率的增强独立于在层平面中的取向。图3没有具体提到的那些其它要素类似于以上参考图1讨论的那些并且不需要在此进一步讨论。
在一些器件实施方案中，超晶格的全部基础半导体部分可为相同数量的单层厚。在其它实施方案中，基础半导体部分的至少一些可为不同数量的单层厚。在仍然其它实施方案中，所有基础半导体部分可为不同数量的单层厚。
在图4A-4C中，呈现使用密度泛函理论(DFT)计算的能带结构。在本领域公知的是DFT低估了带隙的绝对值。因此可通过适当的“剪刀校正(scissors correction)”使大于带隙的所有能带偏移。然而，已知带的形状可靠得多。应在这个方面解释竖直能量轴。
图4A显示由图1中显示的4/1Si/O超晶格25(由点线表示)和大块硅(由连续线表示)的γ点(G)计算的带结构。方向涉及4/1Si/O结构的晶胞并且不涉及Si的常规晶胞，但是图中的(001)方向确实对应于Si的常规晶胞的(001)方向，并因此显示Si导带最小值的预期位置。图中的(100)和(010)方向对应于常规Si晶胞的(110)和(-110)方向。本领域技术人员将理解图中的Si带被折叠以表示它们在用于4/1Si/O结构的适当的倒易晶格方向上。
可看出4/1Si/O结构的导带最小值与大块硅(Si)相反位于γ点，然而价带最小值出现在(001)方向上布里渊区的边缘处，我们称之为Z点。由于由额外的氧层引入的扰动所致的带分裂，技术人员还可注意与Si的导带最小值的曲率相比4/1Si/O结构的导带最小值的曲率更大。
图4B显示由大块硅(连续线)和4/1Si/O超晶格25(点线)的Z点计算的带结构。这个图说明在(100)方向上价带的曲率提高。
图4C显示由图3的超晶格25’的5/1/3/1Si/O结构(点线)和大块硅(连续线)的γ和Z点两者计算的带结构。由于5/1/3/1Si/O结构的对称性，在(100)和(010)方向上计算的带结构是等同的。因此，预期在平行于层即与(001)堆叠方向垂直的平面内传导率有效质量和迁移率是各向同性的。注意到在5/1/3/1Si/O示例中导带最小值和价带最大值都在Z点处或接近Z点。
虽然提高的曲率是减小的有效质量的表示，但是可通过传导率倒易有效质量张量计算进行适当的比较和鉴别。这导致申请人进一步从理论上说明5/1/3/1超晶格25’应基本上是直接带隙。如本领域技术人员将理解的，用于光学转变的适当矩阵元素是直接和间接带隙行为之间区别的另一指示符。
现在参考图5-8和图9的流程图90，现在描述了包括利用MST膜25来将接触掺杂剂约束在接触区域中的沟槽接触结构的半导体器件30和相关的制造方法。在图块91处开始，在初始步骤中，在图块92处在半导体衬底31(例如硅)中形成接触沟槽32，其中在衬底上的浅沟槽隔离(STI)(即氧化物)区域35在沟槽的相对侧上。在图块93处沟槽32衬有MST膜25，例如以上描述的Si/O超晶格(虽然可在不同的实施方案中使用其它半导体/非半导体材料)。在图块94处在MST膜25上形成半导体(这里为硅)盖层33，然后使用相对低的能量注入包括硼、砷、磷等中一种或多种的掺杂剂34。按照一种示例实施方式，对于BF2使用10keV的能量。然而，例如还可使用其它注入能量例如2-20keV和物质B、BF2、As和P。掺杂剂34进入MST层25上方的盖层33中，并且在随后的热步骤过程中MST层将掺杂剂保持或约束在固定位置。
接下来，在沟槽32中形成传导体(图块95)。更特别地，沟槽32可首先用Ti/TiN层36衬里，之后是钨(W)填料37(即钨塞)。提供钛用于硅化物40形成(参见图7a-7c)并且还充当阻挡层以减小或防止钨扩散和产生的尖端穿过下面的接合部。应注意还可使用其它金属来形成硅化物40，例如钴和镍。在图块96处说明性地总结了图9的方法。
更特别地，可将器件30退火以形成硅化物40。钛扩散至盖层33的硅中并且取决于硅盖厚度和沉积的Ti/TiN量(即使用的金属层的厚度)可以或可以不消耗MST层。即，在硅化物形成过程中MST膜可部分或完全牺牲。在图8中显示部分消耗了MST膜25’的示例，图8中其它要素用撇号表示，并且不需要进一步讨论。如果需要，也可使用在注入步骤之后的清洁(即蚀刻)步骤来减小硅盖33厚度。
现在将更详细地描述关于钛的示例硅化物工艺(如本领域技术人员将理解的那样，该工艺对于其它金属将不同)。富含金属的结晶相硅化物层(例如Ti5Si4或Ti5Si3)在500和550℃之间形成，之后C49-TiSi2在575和600℃之间形成。C49-TiSi2在大约800℃下转变为低阻C54-TiSi2相之前完全消耗富含金属的硅化物。钛扩散至硅中并可使用进入间隙的氧进入氧化硅层(通过还原氧化物)。
MST层25具有用于MST硅化工艺的间隙氧，或具有薄的原生氧化物的硅将是等效的。薄的原生氧化物将被钛还原并间隙进入钛硅化物晶体中。这将也是MST膜25的情况，其以在它内部的氧开始。通常来讲，如果盖层33较厚，硅化物40将在到达它之前停止。在这种情况下，这将是硅化物40、重度掺杂的硅(来自注入)、掺杂的MST层25(阻隔掺杂剂)、MST层和衬底31。
另外参考图7a-7c，可采用平面构造产生类似的接触结构30”、30”’和30””，与图6中显示的竖直沟槽构造相反。通过示例的方式，这些构造可用于平面器件(例如MOSFETS)中的源/漏接触。示例显示三种不同的构造，即来自阻挡层36”的硅化物40”完全消耗MST膜(图7a)、部分消耗MST膜(图7b)和在达到MST膜之前停止(图7c)。这三种构造还提供硅化物将如何出现在以上描述的竖直实施方案中的沟槽32的侧壁和底部部分上的详细视图(close upview)，这取决于在给定的实施方式中消耗MST层25的程度，如本领域技术人员将理解的那样。
还应注意MST层25”、25”’、25””可维持较高的B(或其它接触掺杂剂)剂量并减小在退火过程中(即掺杂剂的驱动下)扩散限制的深度或宽度(对于平面或3D接触而言)。此外，可有利地选择硅化物40、40”’、40””深度以留下不受影响的MST层25”、25”’、25””，部分去除，或完全去除MST层25”、25”’、25””(经受注入条件和硅厚度大于MST层)从而有利地留下高的B(或其它接触掺杂剂)和与基线(非MST)情况相比具有减小的扩散深度/宽度。
受益于本文所呈现的教导的本领域技术人员将想到许多修改和其它实施方案。因此，应理解本公开内容不限于本文公开的特定示例性实施方案。

Claims (21)

1.半导体器件,包含：
其中具有沟槽的半导体衬底；
至少部分覆盖该沟槽的底部和侧壁部分的超晶格衬层，该超晶格衬层包含多个堆叠的层组，每个层组包含限定了基础半导体部分的多个堆叠的基础半导体单层，和被约束在相邻的基础半导体部分的晶体晶格内的至少一个非半导体单层；
在该超晶格衬层上并且包含被该超晶格衬层约束在其中的掺杂剂的半导体盖层；和
在该沟槽内的传导体。
2.根据权利要求1所述的半导体器件，其中该传导体包含与该半导体盖层相邻并包含第一金属的金属衬层，和与该金属衬层相邻、填充该沟槽并包含第二金属的金属体。
3.根据权利要求2所述的半导体器件，其中该传导体还包含硅化物。
4.根据权利要求2所述的半导体器件，其中该半导体盖层包含硅；和第一金属包含钛、钴和镍中至少一种。
5.根据权利要求4所述的半导体器件，其中第二金属包含钨。
6.根据权利要求1所述的半导体器件，其中该传导体限定源/漏接触。
7.根据权利要求1所述的半导体器件，其中该基础半导体单层包含硅。
8.根据权利要求1所述的半导体器件，其中该至少一个非半导体单层包含氧。
9.根据权利要求1所述的半导体器件，其中该掺杂剂包含硼、砷和磷中至少一种。
10.用于制造半导体器件的方法，包括：
在半导体衬底中形成沟槽；
形成覆盖该沟槽的底部和侧壁部分的超晶格衬层，该超晶格衬层包含多个堆叠的层组，每个层组包含限定了基础半导体部分的多个堆叠的基础半导体单层，和被约束在相邻的基础半导体部分的晶体晶格内的至少一个非半导体单层；
形成在该超晶格衬层上并且包含被该超晶格衬层约束在其中的掺杂剂的半导体盖层；和
在该沟槽内形成传导体。
11.根据权利要求10所述的方法，其中形成该传导体包括形成与该半导体盖层相邻并包含第一金属的金属衬层，和形成与该金属衬层相邻、填充该沟槽并包含第二金属的金属体。
12.根据权利要求11所述的方法，其中形成该传导体还包括将该金属衬层退火。
13.根据权利要求12所述的方法，其中将该金属衬层退火至少部分消耗了超晶格衬层。
14.根据权利要求12所述的方法，其中该半导体盖层包含硅；和第一金属包含钛、钴和镍中至少一种。
15.根据权利要求14所述的方法，其中第二金属包含钨。
16.根据权利要求10所述的方法，还包括在凹槽内形成该传导体前清洁该半导体盖层。
17.根据权利要求10所述的方法，其中该传导体限定源/漏接触。
18.根据权利要求10所述的方法，其中该基础半导体单层包含硅。
19.根据权利要求10所述的方法，其中该至少一个非半导体单层包含氧。
20.根据权利要求10所述的方法，还包括使用在2-20keV范围内的注入能量在该半导体盖层中注入该掺杂剂。
21.根据权利要求10所述的方法，其中该掺杂剂包含硼、砷和磷中至少一种。
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