TW201939750A - 包含具有超晶格之改良接觸結構之半導體元件及相關方法 - Google Patents

包含具有超晶格之改良接觸結構之半導體元件及相關方法 Download PDF

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TW201939750A
TW201939750A TW108107836A TW108107836A TW201939750A TW 201939750 A TW201939750 A TW 201939750A TW 108107836 A TW108107836 A TW 108107836A TW 108107836 A TW108107836 A TW 108107836A TW 201939750 A TW201939750 A TW 201939750A
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semiconductor
superlattice
layer
metal
trench
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羅勃約翰 史蒂芬生
理查 柏頓
丹尼爾 康奈立
奈爾斯溫 柯迪
羅勃 Ｊ 米爾斯
迪米崔 霍烏托夫
厄爾文 特勞特曼
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美商安托梅拉公司
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Abstract

一種半導體元件，其可包含一半導體底材，當中設有一溝槽，及一超晶格襯裡，其至少局部覆蓋該溝槽之底部及側壁部分。該超晶格襯裡可包含堆疊之層群組，其中每一層群組包含堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包含該超晶格襯裡上且內部具有被該超晶格襯裡拘束之一摻雜物之一半導體頂蓋層，以及該溝槽內之一導體。

Description

包含具有超晶格之改良接觸結構之半導體元件及相關方法
本發明一般而言與半導體元件有關，詳細而言，本發明與具有改良接觸結構之半導體元件及其相關方法有關。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件效能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致效能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與／或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其N型通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部分(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個阻障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一阻障區各係由厚度範圍大致在二至六個交疊之SiO2／Si單層所構成。阻障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing) pp. 391 – 402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice, SAS)。此矽／氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species) 及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1 nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol. 89, No. 7 (2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
已公開的Wang、Tsu及Lofgren之國際專利申請案WO 02/103,767 A1揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一阻障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層／阻障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公開之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙 (aperiodic photonic band-gap, APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
除此之外，授予Wang等人的美國專利第6,376,337號揭示一種用於製作半導體元件絕緣或阻障層之方法，其包括在矽底材上沉積一層矽及至少一另外元素，使該沉積層實質上沒有缺陷，如此實質上無缺陷的磊晶矽便能沉積於該沉積層上。作為替代方案，一或多個元素構成之一單層，較佳者為包括氧元素，在矽底材上被吸收。夾在磊晶矽之間的複數絕緣層，形成阻障複合體。
儘管已有上述方法存在，但在某些應用中使用先進的半導體處理技術可能需要進一步的增強。
一種半導體元件，其可包含一半導體底材，當中設有一溝槽，及一超晶格襯裡，其至少局部覆蓋該溝槽之底部及側壁部分。該超晶格襯裡可包含複數個堆疊之層群組，其中每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包含一半導體頂蓋層，其在該超晶格襯裡上面且內部具有被該超晶格襯裡拘束之一摻雜物，及該溝槽內之一導體。
該導體可包含鄰接該半導體頂蓋層且含有一第一金屬之一金屬襯裡，以及鄰接該金屬襯裡、填充該溝槽且含有一第二金屬之一金屬體。此外，該導體可更包含矽化物。作為示例，該半導體頂蓋層可包含矽，該第一金屬可包含鈦、鈷、鎳當中至少一者，而該第二金屬可包含鎢。
根據一示例性實施例，該導體界定出一源極/汲極接點。作為示例，所述該些基底半導體單層可包含矽，而該至少一非半導體單層可包含氧。同樣作為示例，該摻雜物可包含硼、砷、磷當中至少一者。
本發明另一面向涉及一種用於製作一半導體元件之方法，其可包含在一半導體底材中形成一溝槽，以及形成覆蓋該溝槽之底部及側壁部分之一超晶格襯裡。該超晶格襯裡可包含複數個堆疊之層群組，其中每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該方法可更包含在該超晶格襯裡上形成一半導體頂蓋層，其內部包含被該超晶格襯裡拘束之一摻雜物，及形成該溝槽內之一導體。
在一示例性實施例中，形成該導體可包括形成鄰接該半導體頂蓋層且含有一第一金屬之一金屬襯裡；以及形成鄰接該金屬襯裡、填充該溝槽且含有一第二金屬之一金屬體。形成該導體可更包括對該金屬襯裡進行回火。在又另一示例性實施例中，對該金屬襯裡進行回火可至少部分地消耗掉該超晶格襯裡。作為示例，該半導體頂蓋層可包含矽，且該第一金屬可包含鈦、鈷、鎳當中至少一者。此外，該第二金屬可包含例如鎢。
該方法可更包括在該溝槽中形成該導體之前清潔該半導體頂蓋層。在一示例性實施例中，該導體可界定出一源極/汲極接點。作為示例，該基底半導體單層可包含矽，而該至少一非半導體單層可包含氧。同樣作為示例，該方法可更包含使用範圍在2到20keV之植入能量將該摻雜物植入該半導體頂蓋層中，而該摻雜物可包含硼、砷、磷當中至少一者。
茲參考說明書所附圖式詳細說明示例性實施例，圖式中所示者為示例性實施例。不過，實施例可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之特定示例。相反的，這些實施例之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)則用以標示不同實施方式中之類似元件。
一般而言，本發明係關於透過使用改良半導體超晶格，在平面式及垂直式半導體元件中形成改良的接觸結構，以有利地將接點摻雜物(contact dopant)拘束在所欲之區間。在本說明書中，經改良的半導體超晶格亦被稱為「MST」層或「MST技術」。
詳言之，MST技術涉及進階的半導體材料，例如下文將進一步說明之超晶格25。申請人之理論認為(但申請人並不欲受此理論所束縛)，本說明書所述之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)及：為電子之定義，且：為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量 (tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所束縛)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量(conductivity effective mass)。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子／電洞之導電性有效質量，便可用於分辨出較佳之材料。
申請人已辨識出可用於半導體元件之改進材料或結構。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及／或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。這些結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及／或鐵電特性，下文將進一步討論之。
參考圖1及圖2，所述材料或結構是超晶格25的形式，其結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。超晶格25包含複數個堆疊排列之層群組45a～45n，如圖1之概要剖視圖所示。
如圖所示，超晶格25之每一層群組45a～45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a～46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖1中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格內」一語，係指來自相對之基底半導體部分46a～46n之至少一些半導體原子，透過該些相對基底半導體部分間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部分46a～46n上面之非半導體材料之量而成為可能，這樣，可用之半導體鍵結位置便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論之。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時，新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位置。
在其他實施方式中，使用超過一個此種非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，能帶修改層50與相鄰之基底半導體部份46a～46n，可使超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為超晶格25垂直上下方多個層之間之摻雜物及／或材料擴散之阻擋。因此，這些特性可有利地允許超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進裝置行動性，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，超晶格25可進一步具有對諸如光電元件等尤其有利之實質上之直接能帶間隙。
超晶格25亦可在一上部層群組45n上面包含一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部分46a～46n可包含由 IV 族半導體、 III-V 族半導體及 II-VI 族半導體所組成之群組中選定之一基底半導體。當然， IV 族半導體亦包含 IV-IV 族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據之單層(亦即非完全或低於100%之涵蓋範圍)。舉例來說，參照圖15之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4／1重複結構。氧原子之可能位置僅有一半被佔據。
在其他實施方式及／或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，就一超晶格而言，例如矽／氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。圖1及圖2所示之矽／氧 4／1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4／1 矽／氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4／1 矽／氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
超晶格25之4／1 矽／氧實施方式之較低導電性有效質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3／1／5／1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽／氧之此種超晶格25’ 而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖4A-4C呈現使用密度功能理論(Density Functional Theory, DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖4A呈現主體矽 (以實線表示)及圖1之4／1 矽／氧超晶格25 (以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4／1 矽／氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然圖中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4／1 矽／氧結構之適當反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4／1 矽／氧結構之導帶最小值係位於G點，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4／1 矽／氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖4B呈現主體矽(實線)及該4／1 矽／氧超晶格25 (虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖4C呈現主體矽(實線)及圖3之5／1／3／1 矽／氧超晶格25’ (虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5／1／3／1 矽／氧結構之對稱性，在 方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5／1／3／1 矽／氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5／1／3／1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
茲參考圖5至圖8及圖9之流程圖90，說明包含溝槽接觸結構之一半導體元件30及其相關製作方法，該半導體元件利用MST薄膜25將接點摻雜物拘束在接觸區中。從方框91處開始，在初始步驟中，將接觸溝槽32形成於半導體底材31中(例如矽)，在方框92處，將淺溝槽隔離(STI)(例如氧化物)區35形成於溝槽兩側的底材上。在方框93處，使溝槽32襯上MST薄膜25，例如上述之矽／氧超晶格(然而在不同的實施例中亦可使用其他的半導體／非半導體材料)。在方框94處，將一半導體(此處為矽)頂蓋層33形成於該MST薄膜25上，其接著被以相對較低的能量被植入摻雜物34，其包括硼、砷、磷等等當中一者或多者。根據一示例性實施方式，物種BF2 使用的能量為10keV。然而，亦可使用其他植入能量，例如2到20keV，及其他物種，例如硼、BF2、砷及磷。摻雜物34進入MST層25上方之頂蓋層33，而該MST層在後續的加熱步驟中將困住或拘束摻雜物。
接著，將一導體形成於溝槽32中(方框95處)。更詳細而言，該溝槽32可先襯有鈦/氮化鈦層36，接著被鎢(W)填充物37(即鎢插塞)填充。所提供之鈦用於形成矽化物40(見圖7a至圖7c)，以及作為阻障層使用，以減少或防止鎢擴散及由此產生的突波(spikes)穿透下方接面。應注意的是，其他金屬亦可使用來形成矽化物40，例如鈷和鎳。如圖所示，圖9的方法結束於方框96。
更詳細而言，元件30可被回火以形成矽化物40。鈦擴散至頂蓋層33的矽後，是否可能會消耗MST層，取決於矽頂蓋厚度及鈦/氮化鈦之沉積量(即所用金屬層之厚度)。換言之，在形成矽化物的過程中，該MST薄膜可被部分或完全犧牲。MST薄膜25’被部分消耗之一例係繪示於圖8，該圖的其他元件以撇號(’)表示且無需進一步討論。如有需要，植入步驟後的清潔(即蝕刻)步驟亦可用於減少矽頂蓋33之厚度。
茲詳細說明使用鈦之一示例性矽化物製程(此製程會因使用不同的金屬而相異，熟習本發明所屬技術領域者當可理解)。首先在500°C及550°C間的溫度下形成富含金屬之晶相矽化物層(例如Ti5 Si4 或Ti5 Si3 )，接著在575°C及600°C間的溫度下形成C49 -TiSi2 。C49 -TiSi2 在約800°C溫度中轉變成低電阻的C54 -TiSi2 相之前，會完全消耗該富含金屬之矽化物。鈦將擴散至矽中，且可隨著氧進入間隙而突破氧化矽層(藉由減少氧化物)。
MST層25具有間隙氧以進行MST的矽化過程，或者具有薄原生氧化物的矽亦具有相當的效果。薄原生氧化物將被鈦減少，並進入矽化鈦晶體的間隙。MST薄膜25亦是同樣情況，其係從它裡面的氧開始。一般而言，若頂蓋層33較厚，矽化物40將在抵達頂蓋層33之前即停止。在此情況下，將獲得矽化物40、重摻雜矽(來自植入物)、被摻雜的MST層25(阻擋摻雜物)、MST層及底材31。
茲額外參考圖7a至圖7c，與圖6所示之垂直溝槽組構相反，相似的接觸結構30”、30’”及30””亦可製作於平面式組構中。作為示例，該些組構可用於平面式元件(例如MOSFETS)中的源極/汲極接點。該些示例顯示三種相異組構，即來自阻障層36” 之矽化物40”完全消耗MST薄膜 (圖7a)、部分消耗MST薄膜 (圖7b)，以及在到達MST薄膜前停止 (圖7c)。所述三種組構亦提供在上述垂直實施例中，矽化物將如何出現在溝槽32側壁和底部的詳細觀察，其取決於MST層25在給定實施方式中被消耗的程度，熟習本發明所屬技術領域者當可理解。
亦應注意的是，該些MST層25”、25’”、25””可保留較高的硼(或其他接點摻雜物)劑量，以及減少回火過程 (即摻雜物驅入) 中，擴散限制的深度或寬度(平面式或3D接點皆然)。此外，矽化物40、40’”、40””之深度可有利地被選定以留下完整無缺、部分移除或全部移除之MST層25”、25’”、25””(受植入條件與MST層上的矽的厚度影響)，從而有利地留下高劑量硼(或其他接點摻雜物)且具有相較於基線情況(非MST)更小的深度／寬度。
熟習本發明所屬技術領域者將受益於本說明書之教示而構思出各種修改及其他實施方式。因此，應了解的是，本發明不限於此處所述之示例性實施方式。
21、21’‧‧‧底材
25、25’‧‧‧超晶格
25”、25’’’、25’’’’‧‧‧MST層
30、30’、30’’、30’’’、30’’’’‧‧‧半導體元件
31、31’、31’’、31’’’‧‧‧底材
32‧‧‧接觸溝槽
33、33’、33’’’’、52、52’‧‧‧頂蓋層
34、34’‧‧‧摻雜物
35、35’‧‧‧STI區
36、36’、36’’、36’’’、36’’’’‧‧‧阻障層
37、37’‧‧‧填充物
40’’、40’’’、40’’’’‧‧‧矽化物
45a～45n、45a’～45n’‧‧‧層群組
46、46’‧‧‧基底半導體單層
46a～46n、46a’～46n’‧‧‧基底半導體部份
50、50’‧‧‧能帶修改層
圖1為依照一示例實施方式用於半導體元件之超晶格之放大概要剖視圖。
圖2為圖1所示超晶格之一部分之透視示意原子圖。
圖3為依照一示例實施方式之超晶格另一實施例之放大概要剖視圖。
圖4A為習知技術之主體矽及圖1-2所示之4／1 矽／氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖4B為習知技術之主體矽及圖1-2所示之4／1 矽／氧超晶格兩者從Z點計算所得能帶結構之圖。
圖4C為習知技術之主體矽及圖3所示之5／1／3／1 矽／氧超晶格兩者從G點與Z點計算所得能帶結構之圖。
圖5及圖6分別繪示在形成鎢插塞之前和之後，於包含超晶格溝槽襯裡之半導體元件中形成溝槽接點之剖視圖。
圖7a至圖7c繪示包含超晶格襯裡之平面式源極/汲極閘極接點組構之示意剖視圖。
圖8為圖6之溝槽接點之剖視圖，其中該超晶格溝槽襯裡在矽化過程中被部分消耗。
圖9繪示根據一示例性實施例製作半導體元件之流程圖。

Claims (21)

  1. 一種半導體元件，其包括： 一半導體底材，當中設有一溝槽； 一超晶格襯裡，其至少局部覆蓋該溝槽之底部及側壁部分，該超晶格襯裡包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層； 一半導體頂蓋層，其在該超晶格襯裡上面且內部包含被該超晶格襯裡拘束之一摻雜物；及 該溝槽內之一導體。
  2. 如申請專利範圍第1項之半導體元件，其中該導體包含鄰接該半導體頂蓋層且含有一第一金屬之一金屬襯裡，以及鄰接該金屬襯裡、填充該溝槽且含有一第二金屬之一金屬體。
  3. 如申請專利範圍第2項之半導體元件，其中該導體更包含矽化物。
  4. 如申請專利範圍第2項之半導體元件，其中該半導體頂蓋層包含矽；且該第一金屬包含鈦、鈷、鎳當中至少一者。
  5. 如申請專利範圍第4項之半導體元件，其中該第二金屬包含鎢。
  6. 如申請專利範圍第1項之半導體元件，其中該導體界定出一源極/汲極接點。
  7. 如申請專利範圍第1項之半導體元件，其中該些基底半導體單層包含矽。
  8. 如申請專利範圍第1項之半導體元件，其中該至少一非半導體單層包含氧。
  9. 如申請專利範圍第1項之半導體元件，其中該摻雜物包含硼、砷、磷當中至少一者。
  10. 一種用於製作一半導體元件之方法，其包括： 在一半導體底材中形成一溝槽； 形成覆蓋該溝槽底部及側壁部分之一超晶格襯裡，該超晶格襯裡包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層； 在該超晶格襯裡上形成一半導體頂蓋層，其內部包含被該超晶格襯裡拘束之一摻雜物；及 在該溝槽內形成一導體。
  11. 如申請專利範圍第10項之方法，其中形成該導體包括形成鄰接該半導體頂蓋層且含有一第一金屬之一金屬襯裡；以及形成鄰接該金屬襯裡、填充該溝槽且含有一第二金屬之一金屬體。
  12. 如申請專利範圍第11項之方法，其中形成該導體更包括對該金屬襯裡進行回火。
  13. 如申請專利範圍第12項之方法，其中對該金屬襯裡進行回火至少部分地消耗掉該超晶格襯裡。
  14. 如申請專利範圍第12項之方法，其中該半導體頂蓋層包含矽；且該第一金屬包含鈦、鈷、鎳當中至少一者。
  15. 如申請專利範圍第14項之方法，其中該第二金屬包含鎢。
  16. 如申請專利範圍第10項之方法，其更包括在該溝槽中形成該導體之前清潔該半導體頂蓋層。
  17. 如申請專利範圍第10項之方法，其中該導體界定出一源極/汲極接點。
  18. 如申請專利範圍第10項之方法，其中該些基底半導體單層包含矽。
  19. 如申請專利範圍第10項之方法，其中該至少一非半導體單層包含氧。
  20. 如申請專利範圍第10項之方法，其更包括使用範圍在2到20keV之植入能量，將該摻雜物植入該半導體頂蓋層中。
  21. 如申請專利範圍第10項之方法，其中該摻雜物包含硼、砷、磷當中至少一者。
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US20190279897A1 (en) 2019-09-12
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US10777451B2 (en) 2020-09-15
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US20190280090A1 (en) 2019-09-12
US10879356B2 (en) 2020-12-29
US20210074814A1 (en) 2021-03-11
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US20220285498A1 (en) 2022-09-08

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