WO2007131117A1 - Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods - Google Patents
Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods Download PDFInfo
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- WO2007131117A1 WO2007131117A1 PCT/US2007/068155 US2007068155W WO2007131117A1 WO 2007131117 A1 WO2007131117 A1 WO 2007131117A1 US 2007068155 W US2007068155 W US 2007068155W WO 2007131117 A1 WO2007131117 A1 WO 2007131117A1
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- semiconductor device
- superlattice
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Definitions
- SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL AND ASSOCIATED METHODS
- the present invention relates to the field of semiconductors, and, more particularly, to semiconductors having enhanced properties based upon energy band engineering and associated methods.
- U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
- U.S. Patent No. 4,937,204 to lshibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superiattice.
- U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superiattice with higher mobility achieved by reducing alloy scattering in the superiattice.
- U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionaily present in the silicon lattice at a percentage that places the channel layer under tensile stress.
- U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxiaily grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO 2 /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
- SAS semiconductor- atomic superiattice
- the Si/O superiattice is disclosed as useful in a silicon quantum and light-emitting devices.
- a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicuiar to the layers of the SAS.
- the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
- the insulating layer/barrier iayer allows for low defect epitaxial silicon to be deposited next to the insulating layer.
- APBG Aperiodic Photonic Band-Gap
- material parameters for example, the location of band minima, effective mass, etc, can be tailored to yield new aperiodic materials with desirable band-structure characteristics.
- Other parameters such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.
- a semiconductor device including one or more non-voiatile memory cells having relatively high charge carrier mobility.
- a semiconductor device including at least one non-volatiie memory cell comprising a superlattice channel. More particularly, the device may include a semiconductor substrate, the at least non-volatile memory cell may include spaced apart source and drain regions, and the superlattice channel may be between the source and drain regions.
- the superlattice channel may include a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions.
- each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon.
- the energy band- modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
- the at least one non-volatiie memory cell may further include floating gate adjacent the superlattice channel, and a control gate adjacent the floating gate.
- the at least one non-voiatile memory cell may also include a first insulating iayer (e.g., an oxide layer) between the floating gate and the control gate.
- a second insulating layer may also be between the superlattice channel and the floating gate,
- a superlattice insulating layer may be between the floating gate and the control gate to advantageously provide vertical insulation between the floating and control gates.
- the superiattice channel may have a common energy band structure therein, and it may also have a higher charge carrier mobility than wouid otherwise be present without the energy band-modifying layer.
- each base semiconductor portion may comprise at least one of silicon and germanium, and each energy band-modifying layer may comprise oxygen.
- each energy band-modifying layer may be a single monolayer thick, and each base semiconductor portion may be iess than eight monolayers thick.
- the superlattice may further have a substantially direct energy bandgap, and it may also include a base semiconductor cap layer on an uppermost group of layers.
- all of the base semiconductor portions may be a same number of monolayers thick.
- at least some of the base semiconductor portions may be a different number of monolayers thick.
- each energy band- modifying layer may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example.
- a contact layer may also be included on at least one of the source and drain regions.
- Another aspect of the invention is directed to a method for making a semiconductor device including at least one non-volat ⁇ e memory cell comprising a superlattice channel. More particularly, the method may include forming the at least non-volatile memory cell by forming spaced apart source and drain regions, and forming the superlattice channel between the source and drain regions.
- the superlattice channel may include a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions.
- each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon.
- the energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
- Forming the at least one non-volatile memory cell may further include forming a floating gate adjacent the superlattice channel, and forming a control gate adjacent the floating gate.
- a first insulating layer e.g., an oxide layer
- a second insulating layer may also be formed between the superlattice channel and the floating gate.
- a superlattice insulating layer may be formed between the floating gate and the control gate to advantageously provide vertical insulation between the gates.
- FIG. 1 is schematic cross-sectional view of a semiconductor device including a non-volatile memory cell with a superlattice channel in accordance with the present invention.
- FIG. 2 is a schematic cross-sectionai view of an alternate embodiment of the semiconductor device of FlG. 1.
- FIG. 3 is a greatly enlarged schematic cross-sectional view of the superlattice as shown in FIG. 1.
- FIG. 4 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1.
- FIG. 6A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-3.
- FIG. 6B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superiattice as shown in FIGS. 1-3.
- FIG. 6C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 4.
- FIGS. 7A-7D are a series of schematic cross-sectional diagrams illustrating a method for making the semiconductor device of FiG. 1.
- FIGS. 7A-7D are a series of schematic cross-sectional diagrams illustrating a method for making the semiconductor device of FiG. 1.
- FIGS. 7A-7D are a series of schematic cross-sectional diagrams illustrating a method for making the semiconductor device of FiG. 1.
- FIGS. 7A-7D are a series of schematic cross-sectional diagrams illustrating a method for making the semiconductor device of FiG. 1.
- the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices.
- Applicants theorize, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a "conductivity reciprocal effective mass tensor", M; 1 and M ⁇ 1 for electrons and holes respectively, defined as:
- a second superlattice insulating layer 55" may be formed between the floating and control gates 37", 39" to provide vertical insulation therebetween.
- the superlattice insulating layer 55" may be of a same configuration as the superlattice 25", or they may be of different configurations, examples of which will be discussed further below.
- an oxide or other insulating layer may also be used instead of the superlattice insulating layer 55" in this configuration, as will be appreciated by those skilled in the art.
- the band-modifying layers 50 may also cause the superlattice 25 to have a common energy band structure.
- the semiconductor device such as the ⁇ lustrated memory device 20, enjoys a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
- the superiattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for optoelectronic devices, for example, as described in further detail below,
- the source/drain regions 22, 23, 26, 27 and gate structure 35 of the memory device 20 may be considered as regions for causing the transport of charge carriers through the superiattice in a parallel direction relative to the layers of the stacked groups 45a-45n. Other such regions are also contemplated by the present invention.
- the superiattice 25 also illustratively includes a cap iayer 52 on an upper layer group 45n.
- the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
- the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
- the floating gate 37" may be formed by forming the cap layer 52" to a desired thickness and doping the cap layer to the desired dopant concentration.
- the control gate layer may also be formed by appropriately sizing and doping the cap layer 52" of the superiattice insulating iayer 55".
- Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group IM-V semiconductors, and Group H-Vl semiconductors.
- Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
- the base semiconductor may comprise at least one of silicon and germanium, for example.
- this one half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-haif of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0048] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used.
- St is theorized without Appiicants wishing to be bound thereto, that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages.
- the 4/1 repeating structure shown in FIGS. 3 and 4, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction.
- the calculated conductivity effective mass for electrons is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46.
- the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.
- the lower conductivity effective mass for the 4/1 Si/O embodiment of the superiattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
- the superiattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
- all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In stil! other embodiments, all of the base semiconductor portions may be a different number of monolayers thick. [0054] in FIGS. 6A-6C, band structures calculated using Density
- DFT Functional Theory
- FIG. 6A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice 25 shown in FIG. 1 (represented by dotted lines).
- the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001 ) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
- the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
- the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.
- Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
- Si bulk silicon
- the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
- the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
- FiG. 6B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the
- FIG. 6C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superiattice 25' of FIG. 5 (dotted iines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
- the substrate may be an eight-inch wafer 21 of lightly doped P ⁇ type or N-type single crystal siiicon with ⁇ 100> orientation, although other suitable substrates may aiso be used.
- a layer of the superiattice 25 material is then formed across the upper surface of the substrate 21.
- the superiattice 25 material is deposited across the surface of the substrate 21 using atomic layer deposition and the epitaxial silicon cap layer 52 is formed, as discussed previously above, and the surface is planarized to arrive at the structure of FIG. 7A.
- the superiattice 25 material may be selectively deposited in those regions where channels are to be formed, rather than across the entire substrate 21, as will be appreciated by those skilled in the art. Moreover, planarization may not be required in ail embodiments.
- the epitaxial silicon cap layer 52 may have a preferred thickness to prevent superlattice consumption during gate oxide growth, or any other subsequent oxidations, while at the same time reducing or minimizing the thickness of the silicon cap layer to reduce any parallel path of conduction with the superlattice.
- the silicon cap layer 52 may be greater than 45% of the grown gate oxide thickness pius a small incremental amount to account for manufacturing tolerances known to those skilled in the art. For the present example, and assuming growth of a 25 angstrom gate, one may use approximately 13-15 angstroms of silicon cap thickness.
- FiG. 7B depicts the memory device 20 after the first insulating layer gate oxide 37, the floating gate 37, the second insulating layer 38, and the gate electrode 36 are formed. More particularly, two gate oxide and polysiiicon deposition steps are performed, followed by patterning and/or etching to form the gate stack.
- Polysiiicon deposition refers to low-pressure chemicai vapor deposition (LPCVD) of silicon onto an oxide (hence it forms a poiycrystalline material). The step includes doping with P+ or As- to make it conducting, and the layer may be around 250 nm thick, for example.
- Sidewail spacers 40, 41 may then be formed after LDD formation and over the superlattice 25, as will be appreciated by those skilled in the art.
- the first gate insulating later 36 may be omitted, and the superiattice insulating layer 55" may be formed in the same manner discussed above on the floating gate layer 37 instead of the second gate insulating layer 38. This provides the alternate gate structure illustrated in FIG. 2, as will be appreciated by those skilled in the art.
- Portions of the superlattice 25 material and the substrate 21 may be removed in the source/drain regions, as wil ⁇ be appreciated by those skilled in the art. As may be seen, this step also forms an underlying portion 24 of the substrate 21 underlying the superlattice 25.
- the superlattice 25 material may be etched in a similar fashion to that described above for the gate structure 35. However, it should be noted that with the non-semiconductor present in the superlattice 25, e.g., oxygen, the superlattice may still be etched with an etchant formulated for silicon or polysiiicon unless the oxygen level is high enough to form SiO 2 and then it may be more easily etched using an etchant formulated for oxides rather than silicon.
- the appropriate etch for a given implementation wiii vary based upon the structure and materials used for the superiattice 25 and substrate 21 , as will be appreciated by those of skiil in the art.
- the patterning step may include performing a spinning photoresist, baking, exposure to light (i.e., a photolithography step), and developing the resist.
- the pattern is then transferred to another layer (oxide or nitride) which acts as an etch mask during the etch step.
- the etch step typically is a plasma etch (anisotropic, dry etch) that is materia! selective (e.g., etches silicon ten times faster than oxide) and transfers the lithography pattern into the material of interest.
- lightly doped source and drain extensions 22, 23 are formed using n-type or p-type LDD implantation, annealing, and cleaning.
- An anneal step may be used before or after the LDD implantation, but depending on the specific process, it may be omitted.
- the clean step is a chemical etch to remove metals and organics prior to depositing an oxide layer.
- FIG. 7D Implantation of the source and drain regions 26, 27 is illustrated in FIG. 7D.
- An S1O 2 layer is deposited and etched back.
- the appropriate N- type or p-type ion implantation is used to form the source and drain regions 26, 27.
- the structure is then annealed and cleaned.
- Seif-aligned suicide formation may then be performed to form the suicide layers 30, 31, and 34, and the source/drain contacts 32, 33, are formed to provide the final semiconductor device 20 illustrated in FIG. 1.
- the silicide formation is also known as salicidation.
- the salicidation process includes metal deposition (e.g. Ti), nitrogen annealing, metal etching, and a second annealing.
- the foregoing is, of course, but one example of a process and device in which the present invention may be used, and those of skill in the art will understand its application and use in many other processes and devices.
- the structures of the present invention may be formed on a portion of a wafer or across substantiaily all of a wafer.
- the use of an atomic iayer deposition tool may also not be needed for forming the superlattice 25 in some embodiments.
- the monolayers may be formed using a CVD tool with process conditions compatible with control of monolayers, as will be appreciated by those skilled in the art.
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2009510077A JP2009536463A (en) | 2006-05-05 | 2007-05-03 | Semiconductor device including floating gate memory cell having superlattice channel and related method |
EP07761833A EP2016624A1 (en) | 2006-05-05 | 2007-05-03 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
CA002650809A CA2650809A1 (en) | 2006-05-05 | 2007-05-03 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
AU2007247953A AU2007247953A1 (en) | 2006-05-05 | 2007-05-03 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
CN2007800162875A CN101438415B (en) | 2006-05-05 | 2007-05-03 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
Applications Claiming Priority (4)
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US11/381,794 US20060263980A1 (en) | 2003-06-26 | 2006-05-05 | Method for making a semiconductor device including a floating gate memory cell with a superlattice channel |
US11/381,794 | 2006-05-05 | ||
US11/381,787 | 2006-05-05 | ||
US11/381,787 US7659539B2 (en) | 2003-06-26 | 2006-05-05 | Semiconductor device including a floating gate memory cell with a superlattice channel |
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WO2007131117A1 true WO2007131117A1 (en) | 2007-11-15 |
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PCT/US2007/068155 WO2007131117A1 (en) | 2006-05-05 | 2007-05-03 | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods |
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EP (1) | EP2016624A1 (en) |
JP (1) | JP2009536463A (en) |
AU (1) | AU2007247953A1 (en) |
CA (1) | CA2650809A1 (en) |
TW (1) | TWI335664B (en) |
WO (1) | WO2007131117A1 (en) |
Cited By (2)
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WO2019173668A1 (en) * | 2018-03-08 | 2019-09-12 | Atomera Incorporated | Semiconductor device including enhanced contact structures having a superlattice and related methods |
CN113838911A (en) * | 2021-08-31 | 2021-12-24 | 电子科技大学 | FinFET integrated circuit basic unit |
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JPH09219459A (en) * | 1996-02-13 | 1997-08-19 | Toshiba Corp | Non-volatile semiconductor memory device and manufacture thereof |
JP2007521648A (en) * | 2003-06-26 | 2007-08-02 | アール.ジェイ. メアーズ エルエルシー | Semiconductor device having MOSFET with band design superlattice |
-
2007
- 2007-05-03 EP EP07761833A patent/EP2016624A1/en not_active Withdrawn
- 2007-05-03 AU AU2007247953A patent/AU2007247953A1/en not_active Abandoned
- 2007-05-03 WO PCT/US2007/068155 patent/WO2007131117A1/en active Application Filing
- 2007-05-03 JP JP2009510077A patent/JP2009536463A/en active Pending
- 2007-05-03 CA CA002650809A patent/CA2650809A1/en not_active Abandoned
- 2007-05-04 TW TW96115983A patent/TWI335664B/en active
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US20020139973A1 (en) * | 1997-07-18 | 2002-10-03 | Hitachi, Ltd. | Controllable conduction device |
WO2003049195A1 (en) * | 2001-11-27 | 2003-06-12 | Infineon Technologies Ag | Layer assembly and method for operating a layer assembly as a data memory |
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WO2019173668A1 (en) * | 2018-03-08 | 2019-09-12 | Atomera Incorporated | Semiconductor device including enhanced contact structures having a superlattice and related methods |
US10777451B2 (en) | 2018-03-08 | 2020-09-15 | Atomera Incorporated | Semiconductor device including enhanced contact structures having a superlattice |
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CN113838911A (en) * | 2021-08-31 | 2021-12-24 | 电子科技大学 | FinFET integrated circuit basic unit |
CN113838911B (en) * | 2021-08-31 | 2023-03-21 | 电子科技大学 | FinFET integrated circuit basic unit |
Also Published As
Publication number | Publication date |
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AU2007247953A1 (en) | 2007-11-15 |
CA2650809A1 (en) | 2007-11-15 |
JP2009536463A (en) | 2009-10-08 |
TW200807699A (en) | 2008-02-01 |
EP2016624A1 (en) | 2009-01-21 |
TWI335664B (en) | 2011-01-01 |
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