TWI335664B - Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods - Google Patents

Description

1335664 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of semiconductors, and more particularly to semiconductors having enhanced characteristics in accordance with energy band engineering and related methods. [Prior Art] Various structures and techniques for enhancing the performance of a semiconductor device, such as enhancing the mobility of a charge carrier, have been proposed. For example, U.S. Patent Application Serial No. 2003/0057416 to Currie et al. discloses the disclosure of silicon-germanium, and relaxed silicon, and includes those that would otherwise cause performance degradation. Strained material layers such as imperative-free zones. The biaxial deformation (nine) such as stfain formed in the upper layer changes the mobility of the carrier and enables the fabrication of higher speed and/or lower power components. A CMOS inverter based on a similar strained silicon technology is also disclosed in U.S. Patent Application Publication No. 2003/0034529 to Fitzgerald et al.

U.S. Patent No. 6,472,685, issued to U.S. Pat. (vaience band) withstand tensile deformation (tensile

StFain). An electron having a smaller effective mass and induced by an electric field applied to the gate electrode is confined in its second layer, so that an n-channel MOSFET can be assumed to have a higher Motivation.

U.S. Patent No. 4,937,204 to the disclosure of U.S. Patent No. 4,937,,,,,,,,,,,,,,,,,,,,,,,, 〇n〇layer)) The structure 'sends alternately with the growth of the insect crystal (4) growth). The (4) main electric movement direction is perpendicular to the plane of each layer of the superlattice. A short period superlattice of si Ge is disclosed in U.S. Patent No. 5,357,119 to the disclosure of U.S. Patent No. 5,357,119, which is incorporated herein by reference. Motivation. In accordance with a similar principle, a MOSFET with enhanced mobility is disclosed in U.S. Patent No. 5,683,943, the entire disclosure of which is incorporated herein by reference. The channel layer is in the form of a percentage of tensile stress in the month b and instead appears alternately in the germanium lattice.

A quantum well structure is disclosed in U.S. Patent No. 5,216,262, the entire disclosure of which is incorporated herein by reference. Each of the shielded regions is composed of a single layer having a thickness ranging from approximately two to six overlapping SiCVSi. A section of the material that is too thick is also placed between the shielded areas. Applied Physics and Materials Science and Processes (Applied), published online September 6, 2000

Physics and Materials Science & Processing) pp. 391 _ 402, Tsu in a "Phenomena in silicon nanostructure devices" article reveals helium and oxygen A semiconductor-atomic superlattice (SAS). This Si/O superlattice structure is revealed to be a useful Shixi quantum and luminescent element. In particular, it is disclosed how to fabricate and test the structure of a green electroluminescence diode. The direction of current flow in the diode structure is vertical, i.e., perpendicular to the level of the SAS. The SAS disclosed herein may comprise a semiconductor layer separated by adsorbed species such as oxygen atoms and C0 molecules. The dream that grows outside of this absorbed single layer of oxygen is described as an epitaxial layer and has a relatively low defect density. One of the SAS structures comprises a stone-like portion of a thickness of ι·ι nm, which is about eight atomic layers, and the thickness of the enamel portion of the other structure has two thicknesses. Times. Physics Review Letters, Vol. 89, No, 7 (August 12, 2002), published by Luo et al., entitled "Chemical Design of Direct Gap Light Fragmentation" ("Chemical Design of The article "Direct-Gap Light-Emitting Silicon") further discusses the luminescent SAS structure of Tsu.

Wang, Tsu and Lofgren et al., International Application Bulletin No. WO 02/1〇3 767 A1, discloses a shielded construction block of thin and oxygen 'carbon' H, structure, recording, helium or hydrogen, which can The current flowing vertically through the crystal lattice is reduced by more than four ten orders of magnitude. The insulating/shielding layer allows for the formation of fewer defects in the epitaxial layer to be deposited adjacent to the insulating layer.

A non-periodic photonic band-gap (APBG) can be applied to the electronic bandgap engineering, as disclosed in U.S. Patent Application Serial No. 2,347,520, the disclosure of which is incorporated herein by reference. In particular, the application discloses that the material parameters (for example, the position of the band with the minimum value, the equivalent quality can be adjusted to obtain a new = period material having the desired band structure characteristics. Other parameters, such as (4) the conduct of the conductor, the conductance and the dielectric coefficient (dielectrfc pen) or magnetic permeability, are all claimed to be designed into the material. The field of Nano 1 has made considerable efforts to increase the demand for more improved charge-in components in semiconductor components. Higher charge carrier kinetics can be used to include the power consumption of the device. If there is a high degree of kinetics, the performance is maintained even though the ploughing continues to lie smaller components. SUMMARY OF THE INVENTION Based on the foregoing background, one of the objects of the present invention is to provide a type of 苴 which has a high-charged body with a phase of a high-strength, a static, a purpose, a feature, and an advantage. According to the present invention, a 4-conductor is provided. The components are more: fixed two 3, non-volatile memory cells 'memory cells contain - superlattice channels. - Τ > 4 people I Sx7 ° cattle can contain a semiconductor substrate 'the at least one non-volatile slow cell secret zone 4 superlattice channel can be mixed with no ambiguity;; = Γί at the bottom of the semiconductor On the material, the complex base between the impurity and the immersion zone "the plural of the body part? The two-way (3) guide can be moved to the door. The memory can also include one of the adjacent superlattice channels." Non-i-second: the gate electrode: the control gate. In the embodiment, the first-insulation layer (for example, °, '' may include between the floating gate and the control gate - -Second, im layer vaporized layer). There may also be a super-crystal layer between the superlattice channel and the floating gate. There is also a ff between the ° and the control electrode. The pole is _ vertical insulation. There is no ratio than the belt; therefore, there can be a common energy band structure in the channel, and it can have a higher charge carrier dynamics. As an example, every -_ 〃 °匕3 There are at least one of Shi Xi and Yu, and each of the modified layers may contain oxygen. Further, each of the modified layers may each have a thickness of a single single layer, and each of the base semiconductor portions Each of the superlattice channels may have a substantial direct band gap, and the basin may also include a base semiconductor cap layer over a topmost layer group. In the embodiment, all of the base semiconductor portions T are of the same number of single layers. According to another embodiment, at least some of the base portions of the substrate may be different thicknesses of a single layer. Each of the energy-receiving layers may include a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, and carbon and oxygen. A contact layer may also be included in the source and drain regions. At least one of the above - another point of the present invention is directed to a method of fabricating a semiconductor device comprising at least one non-volatile memory cell comprising a superlattice channel. More specifically, The method may comprise forming a separated source and a drain region, and forming a superlattice channel between the source and the drain region to form at least one non-volatile memory cell. The superlattice channel may be included in the semiconductor bottom Material, between the source and the bungee a plurality of stacked layer groups. Further, each of the superlattice channels may comprise a plurality of stacked semiconductor monolayers defining a base semiconductor portion, and one of the upper layers of the modified layer, and The energy band modifying layer may include at least one non-semiconductor monolayer defined in a crystal lattice of one of the adjacent base semiconductor portions. The at least one non-volatile memory cell may further comprise adjacent to the super One of the lattice channels is oceanic, pole, and formed adjacent to one of the floating gates. In one embodiment, a first insulating layer (eg, an oxide layer) can be formed in the floating Between the gate and the gate, a second insulating layer may also be formed between the superlattice channel and the floating gate. In another embodiment, there may be a between the floating gate and the control gate Superlattice insulation to advantageously provide vertical insulation between the gates. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail in the following description of the accompanying drawings in which: FIG. However, the present invention can still be practiced in a sturdy manner, and the invention is of course not limited to the embodiment shown in the drawings. Rather, these embodiments are provided so that this disclosure will be thorough of the scope of the invention. Throughout the description of the present invention, the same drawing reference numerals are used to designate the same or equivalent elements, and the same reference numerals are used to identify similar elements in the different embodiments. The present invention relates to controlling the characteristics of a semiconductor material at the level of an atom or molecule in order to achieve an increase in the performance of the semiconductor element. In addition, the present invention is also directed to the identification, creation, and use of the property enhancing materials for use in the conductive paths of semiconductor components. The theory proposed by the Applicant of the present invention shows that certain supercrystals and structures disclosed herein can reduce the equivalent mass of the charge carriers and can cause higher movement of the charge carriers due to such reduction. Sex, but the applicant also states that the scope of the invention should not be limited to this theory. Among the documents in the art to which the present invention pertains, there are various definitions for equivalent quality. As a measure of the improvement in equivalent quality, the applicants respectively used "conductivity reciprocal effective mass tensor" Μ/1 and Mh·1 for electrons and holes. Definition: Σ /(▽/(Μ)), (▽ thickness is smoke X; lf(E(k,n), EF,T)d\ E>Ejr bZ is the definition of electrons, and: • ' Σ f ( Vt£(k,»)),.(Vt£(k,n)), ^E{Kn\EF,T)^ -ifte:_d±_ \{\-f{E^,n),EF, T)) dlVi • E<Ef bZ is the definition of the hole, where is the Fermi-Dirac distribution 'EF is Fermi energy, Τ is temperature, E(kjn ) is the energy of the electron in the state corresponding to the wave vector k and the nth band, the subscripts i and j refer to the orthogonal coordinates X, y and z, and the integral is in the Brillouin zone (BZ·, Brillouinzone) The process is carried out in the energy band of the electron and hole energy bands higher and lower than the Fermi energy. Applicant's definition of the conductivity inverse equivalent mass tensor is such that the conductivity of the material is greater than the larger value of the corresponding component of the equivalent mass tensor of the material's tensorial component of its conductivity. It can also be larger. The applicant hereby again mentions the value of the conductivity inverse equivalent mass tensor set by the superlattice described in the following two paragraphs, which can improve the conductive properties of the material, such as the typical preferred direction of charge carrier transport. However, the 'same applicant' still states that the scope of the invention should not be limited to this theory = when the reciprocal of the number of tensor items is referred to herein as the conductive equivalent mass. In other words, if the characteristics of the structure of the semiconductor material are described, the conductivity equivalent of the aforementioned electron/hole, and the calculation result of the carrier pre-distribution can be used to separate the effects. Enhance the materials. The application mode can be selected to have an enhanced energy band structure for a specific purpose. Such a kind of dragon is a material of the superlattice used for the semiconductor component channel region. Sulphurization Figure 1 first contains a memory element 2G based on the superlattice of this side. However, it will be understood by those skilled in the art that the lion can be applied to many different semiconductor components, such as discrete components and/or integrated circuits. The memory cell 20 shown in the figure includes a bottom formed thereon. Non-volatile memory cells on material 21. The memory cell is depicted as comprising a source region with a lightly doped source/dipole extension 22, 23, a source of impurities 26, 27' and a channel region provided by the superlattice 25: a supercrystal Some parts of the grid 25, when forming a lightly doped source/pole extension 22, 23 ❿ for the sake of clarity, the '® cap reading line lion, while the undoped part is ^ solid line / The secret gold is turned into 3. , 31 and the impurity contacts 32, 33 overlap the source/drain regions 26, 27, as will be understood by those skilled in the art. The -= pole structure 35, as shown, includes a pass-and-two-insulator layer 36' provided by the superlattice 25 and a floating gate above the first insulating layer. ^ includes a second insulating layer 38 over the floating gate 37, and a control gate 39 above the second. As an example, the floating and control gates 37, 39 can be first and second. The insulating layer %% may be an oxide layer (ie, a stone oxide layer). For the sake of clarity, the first and second insulating layers 36, 38 are in the form of a dotted line of memory cells 2 The crucible is also shown to be provided with sidewall insulating layers 40, 4b and a gold layer 34 on the control gate 39, as would be understood by those skilled in the art. Flute is described with reference to Figure 2 to illustrate another in accordance with the present invention. - Embodiment Memory Element 2", the aforementioned - and second insulating layer 36' 38 may be omitted from the gate structure 35, and may instead use 10 the vertical insulating property of the superlattice 25". In the illustrated example, the floating gate 37" is formed directly over the superlattice 25" without insulation (ie, ', oxide) layer Intervention. As will be discussed further below, the superlattice 25" material described herein provides enhanced motion not only in the lateral direction (ie, between the 'source/drain regions 26', 27'). This also makes it possible to exert an insulator effect on the current in the vertical direction, so this configuration is possible. Similarly, a second superlattice insulating layer 55" can be formed between the floating and control gates 37''" to provide vertical insulation therebetween. The superlattice insulating layer 55, may be the same structure as the superlattice 25", or it may be a different organization, examples of which will be discussed further below. Of course, an oxide or other insulating layer, here The fabric may also be used in place of the superlattice insulating layer 55"' as understood by those skilled in the art. The applicant has extracted the improved material or structure available for the channel region of the memory element 20. More specifically, the Applicant has delineated some materials or structures in which the appropriate conductivity equivalent mass of electrons and/or holes is relatively low compared to the corresponding value of Shi Xi. many. Referring now to Figures 3 and 4' simultaneously, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular scale and which utilizes conventional atomic or molecular layer deposition techniques ( Techniques of atomic or molecular layer deposition) The superlattice 25 includes a plurality of layer stacks 45a-45n arranged in a stacked form, the stacking relationship of which can be understood from the schematic cross-sectional view in FIG. Each of the layers 45a-45n of the superlattice 25, as shown, includes a plurality of stacked base semiconductor layers 46 defining a plurality of base semiconductor portions 46a - 46n, and An energy-band modifying layer 50 is provided. For clarity of explanation, the band modification layer 50 is indicated by a dotted line in FIG. The band modification layer 50 in the figure includes a non-semiconductor monolayer (non-semiconduct〇r m〇n〇iayer) confined within the crystal lattice of the adjacent base semiconductor portion. Among other embodiments, more than one such single layer is also possible. It should be noted that what is referred to herein as a non-semiconductor or semiconductor monolayer refers to a single layer of material that, if formed in a holistic manner, is a non-semiconductor or semiconductor. That is, a single monolayer of a material such as a semiconductor does not necessarily exhibit the same properties as it would be formed in a relatively sturdy manner in a relatively thick material, as would be understood by those skilled in the art. 133.5664 The Applicant again mentions the following theory, but likewise the Applicant has stated that the scope of the invention should not be limited to the theory that the band-modified layer 5 and its adjacent base semiconductor portions 46a-46n' will The charge carriers of the superlattice 25 in a direction parallel to the layer have a lower proper conductivity equivalent quality than none of them. Consider another way where this parallel direction is orthogonal to the direction of the stack. The band modification layer 5 can also enable the superlattice 25 to have a generally common band structure. The theory of the present invention shows that a semiconductor element such as the illustrated memory element 20 is based on a lower conductivity. The equivalent mass can also enjoy the charge carrier of I胄. In some embodiments, also due to the energy band engineering achievements achieved by the present invention, the ultra-cell 25 may also have a substantial direct energy band gap, which is particularly suitable for the photovoltaic element, as behind The situation will be explained in detail.

As will be appreciated by those skilled in the art, the source/no-polar regions 22, 23, ^ '27 and _ structures 35 of the memory element 20 can be considered to result in the charge Newcomer in the stacking group. Layer class = the area through which the direction passes. The invention also contemplates that the superlattice 25 is also shown to include a cover yer 52 above the top layer set 45n. The cap layer 52 can also include a plurality of base semiconductor monolayers 46. The cap layer 52 ^ = to 1GG single-layered base semiconductors ' and preferably should have (1) to % single layers. in front

The 'float _37 can be formed by forming the cap layer 52 to dope to the desired doping gradient. Similarly, the control appropriately controls the superlattice insulating layer 55', the size of the cap layer 52, and the "Shi Xi and 锗 at least its _. w dry derivation Τ contains, for example, per-layer lining modification The layer 50 may comprise a non-semiconductor (n〇n_semicondu coffee) selected from the group consisting of oxygen, nitrogen, gas, etc. The non-semiconducting ITO is deposited by successive layers to facilitate the process, and also = Stability (them·stable). As can be understood by other implementers, the non-semiconductor can also be compatible with a specific semiconductor system 12 1335664 another species or a lining or compound. For example, 矽 and 锗 at least one of them. w; the word 'single layer should also include the monoatomic layer (4) le gamma layer) and the early smgle m〇lecular layer. It should be noted that the band modification layer 5〇 should also include a layer that does not completely fill all possible original layers. For example, 'refer to FIG. 4, which shows sand as a base semiconductor material. And using oxygen as the energy band to modify the material, a 4/1 number of possible positions of oxygen is Full. ,, then the "abundance of the specific case in other embodiments and / or materials under different circumstances, as Solution 'wherein the wire does not have to fill half of this. That is, as shown in the figure, in the special layer, the individual atoms of oxygen are not arranged in the surface, as in the case of the artisan who can understand the example of the atomic deposition. It is possible that the position of the oxygen is divided by the occupant's _ _ _ _ _ _ while other specific values may be applied in some specific embodiments. Since Shixi and Oxygen are currently widely used in general semiconductor process manufacturers, it is possible to use the technique described in the present invention to solve the problem. Therefore, as soon as the application is ready, the invention can be applied to the invention. The age of the invention should not be limited to seven or less, so that the energy band of the superlattice is all over the whole range or more = To: advantage. The 4/1 repeating structure shown in Figs. 3 and 4, the (i) (is) isotropic of the second i), the calculated H 0 superlattice of conductivity, etc. is 0.12', and the ratio of the two is 0.46. . The same 'holes' calculation of the county, 4/1, superlattice is 0.16, the ratio of the two is 〇.44. The value of 7 is (iv) may be advantageous in some (10) certain semiconductor components on the ϊ, but the increase in the average sentence may be more advantageous, as the skilled person would add == sex while increasing 'or only An increase in the dynamic charge of a charge carrier may also have its 13 133.5664 benefits. The lower conductivity of the 4/1 Si/O embodiment of the superlattice 25 is less than two-thirds of the quality of the conductivity of the superlattice of the superlattice, the money case = both the sub-hole and the hole All right. Of course, the superlattice 25 may further comprise a conductive doping (conductivitydop), as is well known to those skilled in the art. Ying 25, and then describe a supercrystal having different properties according to the present invention. Another embodiment of the cell. In this embodiment, the repeat mode is 3/1/5/1 and the underlying base semiconductor portion 46a has three single layers and the second lowest layer. The base semi-conductor is 4613's five-layer solution. This mode of rejoicing is repeated throughout the superlattice 25. Each layer of modified band 5 can contain a single-single layer. In the case of such a superlattice 25 containing Si/O, the enhancement of the charge timbre is independent of the sounds of the sounds, and the other structural parts not specifically mentioned in FIG. Similar to those discussed above in Figure 2, and therefore will not be discussed again. In some of the component embodiments, all of the base semiconductor portions of the superlattice may be of the same number of monolithic thicknesses. In other embodiments, the superlattice is less than some of the base semiconductor portions, and the thickness may be a different number The thickness of the overlap. In other embodiments, all of the base semiconductor portions of the superlattice have a thickness of $1 for a different number of monolithic laminates. 'Figures 6A-6C show the theory of applied density function ( Densily Functi〇nal is the calculated structure of the belt. This technique is widely known as FF, and DF is between the energy bands _ absolute value. All the above bands can be used; ^^^ "Lsclssors correction") Offset. However, the shape of the band is recognized as more reliable. The band scale of the vertical axis should be considered under such cognition. Figure 6 is the overall block of the prior art (4), solid line Indicates the 4/1 Si/O superlattice (dashed line) of the figure, and the scale of the energy band structure calculated by the point of the code point (6). It suppresses the 4/1 Si/Q structure. The crystal cell (4) t-ratio rather than the Si-like unit cell, although the direction of the (〇〇1) in the figure is consistent with the (001) direction of the general unit crystal of & and thus shows the Si conduction band. The expected position of the minimum value. The (1〇〇) and (〇1〇) directions of the figure ^ are in the (10)) and ( ιι〇) direction of the general unit cell of Si: It will be understood by those skilled in the art that the energy band of Si in the figure is displayed in a folded direction so that the appropriate anti-lattice direction of the 4/1 Si/O structure (recipr〇cal touch (2) this fine coffee) is shown in the figure. It can be seen that the command line is located in the block of the code point, the minimum of the 4/1 Si/0 structure conduction band, the edge of the Brilon zone, and the bond band The minimum value is the minimum point of the propagation of the Wei-band in the _) direction. ^Material, 4/1 Si/O, the larger curvature rate' is compared with the minimum curvature of the conduction band of Si For the sake of it. , due to the extra oxygen layer introduced by the disruption caused by the energy band separation line) in the overall block of the stone (solid line) and 4/1 'superlattice 25 (virtual_) direction bonding band structure butterfly. _ shows that the overall block 矽 (solid line) and the increase in the conduction band minimum and the dirty 兮 显示 shown in Figure 5 are an indicator of the equivalent mass reduction, but via conductivity The calculation of ί Ϊ 4 can still be compared with _. This makes the superlattice 25' of the present application should be a direct hybrid gap. The skill of the artist can (4) solve the problem of optical transfer (_altransition): matrix early matrior dement) 7^ directly close the band to _ line lying another indicator. Now, referring to FIGS. 7A-7E at the same time, a method of fabricating the memory element 2A will be described below. This method begins with the provision of a stone substrate 21 . As an example, the substrate may be a <1〇〇> pointing, a lightly doped P-type or an N-type single crystal 2 other suitable neonates may also be used. According to this example, a layer of superlattice 25 material is then formed over the entire upper surface of the substrate 21. More specifically, the 'superlattice 25 material is deposited on the entire surface of the substrate 21 by atomic layer deposition, and the telecrystalline capping layer 52 is also formed. As previously discussed, the surface is subsequently Planarization to achieve the structure of Figure 7A. It should be noted that in some implementations, the 'superlattice 25 material can be selectively deposited in the regions where the channels will be formed, while 15 U3, 5664 is the entire substrate 21, as is f. In addition, it is not necessary to perform flattening in all of the embodiments. The y-deposited cap layer 52 may have a preferred thickness to avoid the growth of the gate oxide, or the consumption of the superlattice during any subsequent oxygen training, and the thickness of the cap layer may be reduced or decreased at the time of closing, the lowest Reduce any conductive paths parallel to the superlattice. For a given oxide growth, in order to follow the well-known following about 45% of the fines, the axillary layer 52 can be greater than 45% of the thickness of the grown oxide plus a small increment to cover Process tolerances as known to those skilled in the art. For the purposes of the present invention, and assuming an angstrom gate, a thickness of the crucible layer of about 13-15 angstroms can be selected. Shown in Fig. 7B is a first insulating layer gate oxide 37, a floating gate 38, and a memory element 2G after formation. More specifically, it performs two steps of gate oxygen, material and eve 4 deposition, followed by imaging and domain side to form a free stack. Xijing 矽 Shenyi refers to low-pressure chemical vapor deposition (LpcvD, 'which will be deposited on the oxide (which is therefore the county of polycrystalline stone: 'II, s. 3) mixed with P+ or As· Miscellaneous to make it conductive, after which the layer is approximately ^ thick. The sidewall insulating layer 4, 41 can then be formed on the superlattice 25 after the LDD is formed, as in (4) in the Lai It is understandable. In the case of the real ft, the 'th" 'gate insulating layer 36 can be omitted' and the superlattice is absolutely formed. This can provide the cap of Figure 2 (four) - the inter-species configuration w, As can be understood by those skilled in the art, it is understandable that some parts of the falling material 21 can be removed in the source/polar region. As seen, this turn will also be formed using the disk ', f卩 卩 ° ° male \ , which can provide the underlying pad for the superlattice 25 . Superlattice 25 material can be ΐ = 'oxygen, present in the superlattice 25, the superlattice can still use the ί si agent to carry out the side Unless the degree of oxygen is high enough to form a side agent that is not cut, it may be easier to use the second method of the second method, which will depend on the superlattice 25 and the bottom. It will be understood by those skilled in the art. The sub-microman step) and the Dou Yang 〇^ include performing a photoresist spin coating, baking, and exposure (ie, a micro-step) from a fine age. Usually, it is tilted. _ another layer (oxidation 16 1335664 or nitride), which is used as an etch mask during the etching step. The etching step is typically material-specific (for example, etching 矽 is faster than oxide) Plasma etching (non-isotropic, dry etching) and transfer of the lithographic image into the desired material. Referring to Figure 7C, the lightly doped source and drain ("LDD," lightly_d〇ped S〇urce fine drain) extends 22 ' 23, using n-type or p-type LDD implantation, tempering, and cleaning. It may be possible to use a tempering step before or after LDD implantation, but Depending on the specific process, it may also be omitted. The cleaning step is a chemical etching, which is used to remove metals and organics before depositing an oxide layer. Source and immersion areas 26, 27. The implant system is shown in Figure 7D. A different layer of 2 is first = product. Appropriate N-type or P-type The structure of the wire and the bungee region g2, the structure is then tempered and cleaned. Then, the automatic alignment of the metal halide can be performed to form the metallization layer 3, 31 and 34, and the source / The female contact %, 33^ is formed into the final semiconductor element 2() shown in Fig. 3. The shape of the metal impurity is the metal crystallization (4) secret (4). The metal crystallization process includes metal reading ( For example, T!), nitrogen tempering, metal money engraving, and a second tempering. Of course, the foregoing description is only one of the processes and components that may be used in the present invention, and a f φ & The structure of the present invention can be formed on the wafer-to-wafer wafer in other processes and in the sinus and components. In addition, in some real cases, the use of atomic layer deposition tools may not be necessary. For example, under the control of the process conditions, 'use the -cv〇 tool', as can be understood by those skilled in the art. The artist-in-law understands the invention described in the above-mentioned words and deeds. In the circumstances, it can be inferred that there are many changes to the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Still referred to as a simple description of the drawings. Fig. 1 is a schematic diagram of a cross section of a db-te 2Sr IJ. conductor element in accordance with the present invention. Figure 1 is a schematic view of a thief surface of another embodiment of the semiconductor device. 17 1335664 Figure 3 is a large scale enlarged cross-sectional view of the superlattice shown in Figure 1. Figure 4 is a partial view of the superlattice of Figure 1. The atomic structure is applied to the superlattice of the element of the ®1. The larger than the embodiment, Fig. 6 is the overall block in the prior art, and the 4/1 ga code point shown in Fig. 1-3. The calculated curve of the energy band structure. 4/1 Figure 6C is the ha: s^/〇zf 7 -7D is a series of schematic cross-sectional views illustrating the fabrication of a round germanium semiconductor component

[Main component symbol description]

20 Non-volatile memory element/memory cell 20” Memory element 21 Substrate/layer 22 Source 23 Tungsten extension 24 Under pad part 25, 25, 25,: Superlattice 26, 26” Source 27' 27,5 No-pole region 30 Source 31 Deuterium metal telluride layer 32 Source 33 Deuterium contact 34 Metal telluride layer 35 ' 35" Gate structure 36 First insulating layer 37, 37" Floating gate 38 Second Insulation layer 39, 39" control gate 40'41 sidewall isolation layer 45n top layer group 45a-45n stack group 46 semiconductor single layer 18 133-5664 46a', 46b' 50, 50, 52, 52, 55" , 46a-46n base semiconductor part with modified layer cover superlattice insulation

Claims (1)

1335664 X. Patent Application Range: 1. A semiconductor component comprising: a semiconductor substrate; and at least one non-volatile memory cell comprising a separated source and drain region, a superlattice channel, included a plurality of stacked layer groups between the source and the drain region on the semiconductor substrate, each of the superlattice channels each comprising a plurality of stacked semiconductor monolayers defining a base semiconductor portion and One of the upper layers can be provided with a modified layer comprising at least one non-semiconductor monolayer defined in the crystal lattice of the adjacent base semiconductor portion, adjacent to the superlattice channel One of the floating gates, and one of the control gates adjacent to the floating gate electrode. 2. The semiconductor component of claim 1 wherein the non-volatile content is between the float and the (four) gate. Miscellaneous, and more package 3. The semiconductor component of claim 2, wherein the at least one non-volatile cell further contains a _------------------------------------ The semiconductor device of claim 1, wherein the superlattice channel has a semiconductor element of the superlattice channel having a ratio of 1 to 8 and a semiconductor component of each of the base semiconductor portions. The semiconductor component of claim 1 wherein each of the base semiconductor portions (1) is a semiconductor component of claim 1 wherein each of the band modification layers 20 133.5664 contains oxygen. a single %, the semiconductor component of claim 1, wherein each of the band-modifying layers is a semiconductor element each of which is a semiconductor element of each of the base semiconductor portions, wherein the super-lattice The channel further has a top group of layers, a cap super-channel, and a body part 1i: a thickness semiconductor element, wherein all of the substrates are semi-conductive, and the one-half layer is guided by the substrate. Semiconductor portion 18. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; and forming at least one non-volatile memory cell, wherein the source and the non-polar region are formed by separation, each of the superlattice channels Each of the layers comprises a single layer of defined conductors and one of the upper layers of the conductor layer, and the body = a semi-conductive layer forming a floating gate adjacent to one of the superlattice channels, and adjacent to the formation One of the floating gates controls the gate. Stealing 3: if' forming the at least one non-volatile memory, the packet 3 has a first insulating layer formed between the gate and the control gate. The method of claim 19, wherein the forming the at least one non-volatile memory 21 1335664 further comprises forming a second insulating layer between the superlattice channel and the floating closed end. The memory of the buddy contains at least one of the layers. The method further comprises the method of forming an energy band structure in the _ and the non-polar region, the method of claim 18, wherein the superlattice channel has a common modifying layer in the presence of 4! S S . Among them, the superlattice channel has a method of not having the method of claim 18 of the patent application, and the per-base semiconductor portion contains each error. The method of claim 18, wherein each of the base semiconductor portions comprises the method of claim 18, wherein each of the band modification layers comprises aerobic. The method of the single-layer H-month patent suffices 18, wherein each of the energy-band modification layers is a single-single-eight-single method, wherein each of the base semiconductor portions is less directly capable of benefiting祀 项 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 其中 超 其中 其中 其中 其中 其中 其中 其中 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超 超Patent range item 1 〇j is the thickness of the same number of single layers. <万法' of all of the base semiconductor parts 33· Patent application item 18·7, at least some of which are different numbers of single layers 'of which 22 of these base semiconductor parts are 1 1335664 34. Patent application The method of claim 18, wherein each of the band modification layers comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen. twenty three