TWI645562B - 在單一晶圓處理室中製作具有所需均勻度控制之加強型半導體結構之方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
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- H01L21/0245—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
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Abstract
一種在單一晶圓處理室之處理半導體晶圓的方法可包括，將該單一晶圓處理室加熱到650至700℃範圍內之溫度，以及在經加熱之該單一晶圓處理室內，經由沉積矽及氧在該半導體晶圓上形成至少一超晶格，以形成複數個堆疊之層群組。每一層群組包含複數個堆疊之基底矽單層，其界定出一基底矽部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層。沉積氧可包括使用一N2O氣體流。
Description
本申請案主張2015年6月2日提出之美國臨時專利申請案第62/169,885號之優先權，茲將該臨時申請案之完整內容納入本說明書。
本發明一般而言與半導體元件有關，詳細而言，本發明與製作加強型半導體結構之方法有關。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件性能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致性能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與/或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘電極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其n通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部分(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個能障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一能障區各係由厚度範圍大致在二至六個交疊之SiO2/Si單層所構成。能障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing)pp.391-402中，
Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice,SAS)。此矽/氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species)及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol.89,No.7(2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
已公告之Wang,Tsu及Lofgren等人的國際申請案WO 02/103,767 A1號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一能障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層/能障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公告之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙(aperiodic photonic band-gap,APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期
性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
雖有此等結構所提供之優點，但對於將進階半導體材料與各種半導體元件結合，以及不同的半導體處理設定而言，進一步的開發仍是有必要的。
一種在單一晶圓處理室中處理半導體晶圓的方法可包括，將該單一晶圓處理室加熱到650至700℃範圍內之溫度，以及在經加熱之該單一晶圓處理室內，經由沉積矽及氧在該半導體晶圓上形成至少一超晶格，以形成複數個堆疊之層群組。每一層群組可包含複數個堆疊之基底矽單層，其界定出一基底矽部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層。沉積氧可包括使用一N2O氣體流而沉積氧。
詳細而言，所述N2O氣體流可包括，在含有諸如氦及氬至少其中一者之氣體中包括0.1%至10%的N2O。作為示例，沉積氧可包括以1至100秒範圍內的曝露時間沉積氧。在一實施例中，N2O氣體流量可在每分鐘10至5000標準立方公分(standard cubic centimeters per minute，SCCM)範圍內。此外，氧的沉積可在諸如10至100Torr範圍內之壓力下進行。作為示例，在氧單層形成期間，N2O的總劑量可在1x1014至7x1014原子/平方公分(atoms/cm2)範圍內。
依照本發明一示例性實施方式，半導體晶圓可包括複數個分隔之淺溝槽隔絕(STI)區，且形成至少一超晶格可包括在相鄰的成
對淺溝槽隔絕區之間選擇性形成各個超晶格。依照本發明另一示例，形成至少一超晶格可包括在半導體晶圓上地毯式(blanket)形成超晶格。此外，來自相對基底矽部分之至少一些矽原子，可透過該些相對基底矽部分間之至少一氧單層以化學方式鍵結在一起。\
25‧‧‧超晶格
25’‧‧‧超晶格
45a~45n‧‧‧層群組
45a’~45n’‧‧‧層群組
46‧‧‧基底半導體單層
46’‧‧‧基底半導體單層
46a~46n‧‧‧基底半導體部份
46a’~46n’‧‧‧基底半導體部份
50‧‧‧能帶修改層
50’‧‧‧能帶修改層
52‧‧‧頂蓋層
52’‧‧‧頂蓋層
60‧‧‧半導體晶圓
61‧‧‧單一晶圓處理室
62‧‧‧加熱器
63‧‧‧控制器
70‧‧‧晶圓
71‧‧‧批次反應器
72‧‧‧加熱器
73‧‧‧控制器
74‧‧‧淺溝槽隔絕區
80‧‧‧圖表
81‧‧‧N2O氣體流
82‧‧‧O2氣體流
83‧‧‧點
85‧‧‧圖表
86‧‧‧繪製線
87‧‧‧參考線
90‧‧‧圖表
91‧‧‧繪製線
100‧‧‧圖表
101‧‧‧氧
102‧‧‧氮化矽
103‧‧‧碳-12
110‧‧‧圖表
111‧‧‧氧
112‧‧‧氮化矽
113‧‧‧碳-12
圖1為依照本發明之一半導體元件所用一超晶格之放大示意剖視圖。
圖2為圖1所示超晶格之一部分之透視示意原子圖。
圖3為依照本發明之一超晶格之另一實施方式之放大示意剖視圖。
圖4A為習知技術之主體矽及圖1~2所示之4/1矽/氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖4B為習知技術之主體矽及圖1~2所示之4/1矽/氧超晶格兩者從Z點計算所得能帶結構之圖。
圖4C為習知技術之主體矽及圖3所示之5/1/3/1矽/氧超晶格兩者從G點與Z點計算所得能帶結構之圖。
圖5為一方塊圖，其概要描繪依照本發明一示例實施方式，使用一N2O氣體流在一單一晶圓處理室形成超晶格。
圖6為一概要方塊圖，其描繪依照本發明另一示例實施方式，使用一N2O氣體流在一批次晶圓處理室形成超晶格。
圖7為依照本發明一示例實施方式，在一單一晶圓處理
室中O2氧沉積方式(deposition approach)及N2O氧沉積方式兩者之總劑量相對於流量之圖表。
圖8為依照本發明一示例實施方式，在一單一晶圓處理室中N2O氧沉積方式之總劑量相對於時間之圖表。
圖9為依照本發明一示例實施方式，在一單一晶圓處理室中N2O氧沉積方式之總劑量相對於溫度之圖表。
圖10及11為依照本發明示例實施方式，在一單一晶圓處理室中，以不同的淺溝槽隔絕區間距進行選擇性超晶格沉積之濃度相對於深度之圖表。
茲參考本發明說明書所附圖式詳細說明本發明，圖式中所示者為本發明之較佳實施方式。不過，本發明可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之實施方式。相反的，這些實施方式之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡，並向熟習本發明所屬技術領域者完整傳達本發明之範圍。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)則用以標示不同實施方式中之類似元件。
一般而言，本發明與加強型半導體元件有關，詳細而言，本發明與結合有進階半導體材料(例如下文所述之超晶格25)的加強型半導體元件及其相關製造技術有關。透過原子量級模擬及實驗驗證(SIMS)，申請人確立了，在超晶格25中，諸如硼及砷等等的電性摻雜物
具有一能量最小值(energetic minimum)，該能量最小值位在氧或CO或氮等原子層附近(其典型為一矽鏈從其中被移除)，且這些摻雜物在熱擴散下會優先在此位置聚積。在下文說明了示例性的超晶格結構後，本說明書接著提供用於超晶格25之強化確定性摻雜(enhanced deterministic doping)方法。但應注意的是，熟習本發明所屬技術領域者當可理解，本說明書所述方法除超晶格外亦可用於其他半導體層及半導體結構。
申請人之理論認為(但申請人並不欲受此理論所束縛)，本說明書所述之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)及：
為電子之定義，且：
為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k
及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量(tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所束縛)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子/電洞之導電性有效質量，便可用於分辨出較佳之材料。
申請人已辨識出可用於半導體元件之改進材料或結構。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及/或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。這些結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及/或鐵電特性，下文將進一步討論之。
參考圖1及圖2，該些材料或結構之形式為一超晶格25，該超晶格25之結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。該超晶格25包含複數個堆疊排列之層群組45a~45n，如圖1之示意剖視圖所示。
如圖所示，超晶格25之每一層群組45a~45n包含複
數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a~46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖1中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格內」一語，係指來自相對之基底半導體部分46a~46n之至少一些半導體原子，透過該些相對基底半導體部分間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部分46a~46n上面之非半導體材料之量而成為可能，這樣，可用之半導體鍵結位置便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論之。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時，新沉積之半導體原子使可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位置。
在其他實施方式中，使用超過一個非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，能帶修改層50與相鄰之基底半導體部份46a~46n，可使該超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換
一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使該超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為該超晶格25垂直上下方多個層之間之摻雜物及/或材料擴散之阻擋。因此，這些特性可有利地允許該超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進裝置行動性，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含該超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，該超晶格25可進一步具有對諸如光電元件等尤其有利之實質上之直接能帶間隙。
如圖所示，該超晶格25亦包含一上部層群組45n上面之一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部分46a~46n可包含由IV族半導體、III-V族半導體及II-VI族半導體所組成之群組中選定之一基底半導體。當然，IV族半導體亦包含IV-IV族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈
積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據(亦即非完全或低於100%之涵蓋範圍)之單層。舉例來說，參照圖2之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4/1重複結構。在圖示之實施例中，氧原子之可能位置僅有一半被佔據。
在其他實施方式及/或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，就一超晶格而言，例如矽/氧超晶格，矽單層之數目最好為七層或更
少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。。圖1及圖2所示之矽/氧4/1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4/1矽/氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4/1矽/氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
該超晶格25之4/1矽/氧實施方式之較低導電性有效質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，該超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3/1/5/1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽/氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提
及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖4A~4C呈現應用密度功能理論(Density Functional Theory,DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖4A呈現主體矽(以實線表示)及圖1之4/1矽/氧超晶格25(以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4/1矽/氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然圖中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4/1矽/氧結構之適當反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4/1矽/氧結構之導帶最小值係位於G點，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4/1矽/氧結構之導帶最小值之曲率較大，此係因額外氧層引
入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖4B呈現主體矽(實線)及該4/1矽/氧超晶格25(虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖4C呈現主體矽(實線)及圖3之5/1/3/1矽/氧超晶格25’(虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5/1/3/1矽/氧結構之對稱性，在方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5/1/3/1矽/氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5/1/3/1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
參考圖5~圖11，以下說明在單一晶圓(圖5)及批次晶圓(圖6)處理室中，使用N2O氧輸送系統製作如前文所述之能帶經過設計之結構或薄膜以增加產率之示例方法。在單一晶圓方式中，一半導體(例如矽)晶圓60可被插入一單一晶圓處理室61，該單一晶圓處理室概要地包括一加熱器或加熱元件62。此外，一控制器63可控制該加熱器62、氣體流，以及該處理室61在處理期間的其他操作，以在該晶圓60上進行
一地毯式超晶格25沉積。亦即，超晶格25是形成在該晶圓60的整個上部表面上。但在某些實施例中，則可使用選擇性沉積方式，在該方式中，超晶格25層或薄膜係在淺溝槽隔絕區形成後，選擇性地形成在該晶圓60的主動區域上，如下文參考圖6所進一步討論。不論地毯式還是選擇性的超晶格沉積，都可利用本說明書所述方法在該單一晶圓處理室61中實施。
一示例性單一晶圓處理室61為單一晶圓進階半導體材料(ASM)處理室，在該處理室中，減壓(reduced pressure，RP)操作可在諸如10T至100T之壓力範圍內，詳言之為大約19T至40T之壓力範圍內達成。作為比較，在製作矽/氧超晶格25的典型方法中，該ASM處理室可使用含有1% O2氣體流之一氦氣來源。在本發明一實施例中，所使用的是N2O氧源，而非O2氧源。詳言之，控制器63可在一氦或氬氣體源中提供0.1%至10%範圍內之N2O氣體流，更明確而言為大約1%之N2O氣體流，以取代前述的O2氣體流。一般而言，N2O的反應活性比O2低，因此在某些應用中N2O有利於協助控制製造程序，如下文所進一步討論。
以下說明在單一晶圓處理室61中使用前述N2O氣體流的示例性處理參數。該處理室可加熱至，舉例而言，650至700℃範圍內之溫度。申請人已確定，溫度低於650℃時，完全或幾乎沒有氧會隨著N2O氣體流與矽/氧超晶格薄膜25結合。此外，溫度高於700℃時，氧雖然會結合，但氧沉積後的矽生長可能會減少，這大概是不同的結合狀態開始支配的緣故。舉例而言，在選擇性沉積方法中，二氧化矽可能形成在表面上，因而導致矽的生長率較低。
此外，該N2O氣體流量可從10至5000SCCM，詳言
之為大約80至195SCCM，且其劑量時間可從10秒至100秒，詳言之為大約12至24秒。這可對應於大約1x1014至7x1014原子/平方公分之總劑量，如圖7中圖表80的繪製線81所示，該繪製線代表680℃的單一晶圓處理。作為比較，繪製線82對應於一O2氣體流，其只需3秒的曝露時間，因其反應活性大於N2O。從圖中可看出，N2O的12秒曝露時間是4倍長，且其調諧曲線(tuning curve)比較平坦。在此一比較中，整體製程壓力(overall process pressure)經過了調整，以針對N2O獲得一點83(但溫度、時間及流量保持與該點83下方之點相同)，該點使製程總劑量集中在大約1x1015原子/平方公分。申請人的理論為(但申請人並不欲受此理論所束縛)，利用N2O氣體流沉積氧單層的超晶格薄膜，其劑量保持(dose retention)及堆積(pile up)結果，可相似於利用O2氣體流沉積氧層的超晶格薄膜。
在圖6之示例中，複數個晶圓70在設有一加熱器72之一批次反應器71中進行處理。同樣地，一控制器73在批次處理期間控制該加熱器72、氣體流等等，以在該些晶圓70上形成超晶格25。圖中所繪示例為一選擇性沉積製程，在該製程中，如上文所述，各個的超晶格被形成在該些晶圓70中相鄰的淺溝槽隔絕區74之間，但在不同實施例中，亦可採用地毯式的薄膜沉積。
作為示例，此種包含上述結構的半導體元件或晶圓的批次處理，可利用日本東京Hitachi Kokusai Electric,Inc.公司的批次磊晶系統(Batch Epitaxial System，BES)實施。該批次磊晶系統可在mTorr狀態下操作，且其設計為一大型加熱爐。作為示例，一個批次可包含50至125個半導體晶圓，但在不同實施例中亦可使用其他數目的晶圓。此外，除本
說明書所述之示例性處理室外，亦可使用其他不同的處理室。
在N2O的反應活性有利地低於O2，從而有助於控制批次製造程序以獲得較佳均勻度的同時，亦可選定不同的處理參數讓N2O充分反應，以允許前述的超晶格薄膜形成。舉例而言，可將溫度升高至足以獲得一氧源而進行反應，但同時不使溫度過高而導致氧在下一個矽層降下前就脫附(desorb)，或導致氧以不同組態鍵合(SiO2)而使得矽的磊晶生長完全無法重新開始。一般而言，在較低壓力下的批次處理會使氣體更有反應性，因此，前文針對單一晶圓處理所提供的參數亦可用於批次處理，但溫度應下調為550至600℃，以在mTorr狀態中提供同等的反應活性。單一與批次晶圓處理皆可使用諸如二氯矽烷(DCS)而為選擇性或非選擇性。二氯矽烷可在較高溫度中使用，且對HCl的添加有選擇性。但在不同組構中亦可使用其他溫度範圍。
在圖8的圖表85中，繪製線86代表在一ASM單一晶圓處理室中，一1% N2O氣體流在650℃及83SCCM下進行沉積時總劑量相對於時間的曲線。從參考繪製線87可看出，該總劑量實質上為直線形。作為比較，在相同規模下，氧的總劑量會是1x1015原子/平方公分，曝露時間則會減至3秒。
在圖9的圖表90中，繪製線91描繪在單一晶圓處理室中，一1% N2O氣體流的總劑量相對於溫度的曲線。如前所述，在ASM單一晶圓平台中，氧結合在接近及低於650℃時無法重複(亦即沒有N2O分解)，且在高於700℃時會不安定(亦即鍵合至矽的氧有所改變)。
另參考圖10，圖表100描繪在單一晶圓ASM處理室
中，以相對寬的間距--使用30Å間隙壁(spacer)--並使用N2O進行一選擇性超晶格沉積(亦即沉積在相鄰的淺溝槽隔絕區之間)時，濃度相對於深度的曲線。在所繪示例中，氧濃度以繪製線101表示，氮化矽濃度以繪製線102表示，碳-12則以繪製線103表示。此示例係使用680℃的溫度及170SCCM的N2O流量並曝露12秒。
圖11之圖表110為另一相似示例。圖11的示例除了使用較小間隙壁(即16Å)外，其他每個條件都與圖10示例相同。在圖11所繪示例中，氧濃度以繪製線111表示，氮化矽濃度以繪製線112表示，碳-12則以繪製線113表示。
在得益於本說明書之教示下，熟習本發明所屬技術領域者將可想到許多變化及其他實施方式。因此，應理解的是，本發明並不限於本說明書所揭露之特定示例性實施方式。
Claims (18)
- 一種在一單一晶圓處理室中處理一半導體晶圓之方法，該方法包括：將該單一晶圓處理室加熱到650至700℃範圍內之溫度；以及在經加熱之該單一晶圓處理室內，經由沉積矽及氧在該半導體晶圓上形成至少一超晶格，以形成複數個堆疊之層群組，每一層群組包含複數個堆疊之基底矽單層，其界定出一基底矽部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層；其中沉積氧包括使用一N2O氣體流以沉積氧，所述N2O氣體流包括在含有氦及氬至少其中一者之氣體中包括0.1%至10%的N2O。
- 如申請專利範圍第1項之方法，其中沉積氧包括以1至100秒範圍內的曝露時間沉積氧。
- 如申請專利範圍第1項之方法，其中所述N2O氣體流量在每分鐘10至5000標準立方公分(SCCM)範圍內。
- 如申請專利範圍第1項之方法，其中沉積氧包括在10至100Torr範圍內之壓力下沉積氧。
- 如申請專利範圍第1項之方法，其中在所述氧單層形成期間，N2O的總劑量在1x1014至7x1014原子/平方公分範圍內。
- 如申請專利範圍第1項之方法，其中所述半導體晶圓包括複數個分隔之淺溝槽隔絕(STI)區，且其中形成所述至少一超晶格包括在相鄰的成對淺溝槽隔絕區之間選擇性形成各個超晶格。
- 如申請專利範圍第1項之方法，其中形成所述至少一超晶格包括在所述半導體晶圓上以地毯式形成超晶格。
- 如申請專利範圍第1項之方法，其中來自相對基底矽部分之至少一些矽原子，係透過該些相對基底矽部分間之至少一氧單層以化學方式鍵結在一起。
- 一種在一單一晶圓處理室中處理一半導體晶圓之方法，該半導體晶圓包括複數個分隔之淺溝槽隔絕(STI)區，該方法包括：將該單一晶圓處理室加熱到650至700℃範圍內之溫度；以及在經加熱之該單一晶圓處理室內，經由沉積矽及氧在該半導體晶圓上相鄰的成對淺溝槽隔絕區之間選擇性地形成各個超晶格，以形成複數個堆疊之層群組，每一層群組包含複數個堆疊之基底矽單層，其界定出一基底矽部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層；其中沉積氧包括使用在含有氦及氬至少其中一者之氣體中包括0.1%至10%N2O之一N2O氣體流並在10至100Torr範圍內之壓力下沉積氧。
- 如申請專利範圍第9項之方法，其中沉積氧包括以1至100秒範圍內的曝露時間沉積氧。
- 如申請專利範圍第9項之方法，其中所述N2O氣體流量在每分鐘10至5000標準立方公分(SCCM)範圍內。
- 如申請專利範圍第9項之方法，其中在所述氧單層形成期間，N2O的總劑量在1x1014至7x1014原子/平方公分範圍內。
- 如申請專利範圍第9項之方法，其中來自相對基底矽部分之至少一些矽原子，係透過該些相對基底矽部分間之至少一氧單層以化學方式鍵結在一起。
- 一種在一單一晶圓處理室中處理一半導體晶圓之方法，該方法包括：將該單一晶圓處理室加熱到650至700℃範圍內之溫度；以及在經加熱之該單一晶圓處理室內，經由沉積矽及氧在該半導體晶圓上形成一地毯式超晶格，以形成複數個堆疊之層群組，每一層群組包含複數個堆疊之基底矽單層，其界定出一基底矽部份，以及被拘束在相鄰基底矽部份之一晶格內之至少一氧單層；其中沉積氧包括使用在含有氦及氬至少其中一者之氣體中包括0.1%至10%N2O之一N2O氣體流並在10至100Torr範圍內之壓力下沉積氧。
- 如申請專利範圍第14項之方法，其中沉積氧包括以1至100秒範圍內的曝露時間沉積氧。
- 如申請專利範圍第14項之方法，其中所述N2O氣體流量在每分鐘10至5000標準立方公分(SCCM)範圍內。
- 如申請專利範圍第14項之方法，其中在所述氧單層形成期間，N2O的總劑量在1x1014至7x1014原子/平方公分範圍內。
- 如申請專利範圍第14項之方法，其中來自相對基底矽部分之至少一些矽原子，係透過該些相對基底矽部分間之至少一氧單層以化學方式鍵結在一起。
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- 2016-06-01 US US15/169,983 patent/US9721790B2/en active Active
- 2016-06-02 TW TW105117443A patent/TWI645562B/zh active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050163692A1 (en) * | 2000-08-08 | 2005-07-28 | Atanackovic Petar B. | Rare earth-oxides, rare earth -nitrides, rare earth -phosphides and ternary alloys with silicon |
| US20150144877A1 (en) * | 2013-11-22 | 2015-05-28 | Mears Technologies, Inc. | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016196600A1 (en) | 2016-12-08 |
| US20160358773A1 (en) | 2016-12-08 |
| TW201644049A (zh) | 2016-12-16 |
| US9721790B2 (en) | 2017-08-01 |
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