JP2017126747A - 酸素源としてのn2oを使用する原子層構造を包含する半導体デバイスの製造方法 - Google Patents
酸素源としてのn2oを使用する原子層構造を包含する半導体デバイスの製造方法 Download PDFInfo
- Publication number
- JP2017126747A JP2017126747A JP2017003204A JP2017003204A JP2017126747A JP 2017126747 A JP2017126747 A JP 2017126747A JP 2017003204 A JP2017003204 A JP 2017003204A JP 2017003204 A JP2017003204 A JP 2017003204A JP 2017126747 A JP2017126747 A JP 2017126747A
- Authority
- JP
- Japan
- Prior art keywords
- oxygen
- semiconductor
- monolayer
- forming
- range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 239000001301 oxygen Substances 0.000 title claims abstract description 66
- 229910052760 oxygen Inorganic materials 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 47
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 title 1
- 229960001730 nitrous oxide Drugs 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 71
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 65
- 239000010703 silicon Substances 0.000 claims abstract description 64
- 239000002356 single layer Substances 0.000 claims abstract description 42
- 238000012545 processing Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 239000002800 charge carrier Substances 0.000 abstract description 13
- 230000006872 improvement Effects 0.000 abstract description 5
- 238000007734 materials engineering Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 26
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000003775 Density Functional Theory Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002052 molecular layer Substances 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013626 chemical specie Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229940124447 delivery agent Drugs 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B17/00—Surgical instruments, devices or methods, e.g. tourniquets
- A61B17/54—Chiropodists' instruments, e.g. pedicure
-
- A—HUMAN NECESSITIES
- A43—FOOTWEAR
- A43B—CHARACTERISTIC FEATURES OF FOOTWEAR; PARTS OF FOOTWEAR
- A43B17/00—Insoles for insertion, e.g. footbeds or inlays, for attachment to the shoe after the upper has been joined
- A43B17/003—Insoles for insertion, e.g. footbeds or inlays, for attachment to the shoe after the upper has been joined characterised by the material
- A43B17/006—Insoles for insertion, e.g. footbeds or inlays, for attachment to the shoe after the upper has been joined characterised by the material multilayered
-
- A—HUMAN NECESSITIES
- A43—FOOTWEAR
- A43B—CHARACTERISTIC FEATURES OF FOOTWEAR; PARTS OF FOOTWEAR
- A43B7/00—Footwear with health or hygienic arrangements
- A43B7/14—Footwear with health or hygienic arrangements with foot-supporting parts
- A43B7/1405—Footwear with health or hygienic arrangements with foot-supporting parts with pads or holes on one or more locations, or having an anatomical or curved form
- A43B7/1455—Footwear with health or hygienic arrangements with foot-supporting parts with pads or holes on one or more locations, or having an anatomical or curved form with special properties
- A43B7/146—Footwear with health or hygienic arrangements with foot-supporting parts with pads or holes on one or more locations, or having an anatomical or curved form with special properties provided with acupressure points or means for foot massage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Surgery (AREA)
- Public Health (AREA)
- General Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Medical Informatics (AREA)
- Heart & Thoracic Surgery (AREA)
- Materials Engineering (AREA)
- Veterinary Medicine (AREA)
- Animal Behavior & Ethology (AREA)
- Molecular Biology (AREA)
- Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
- Wood Science & Technology (AREA)
- Epidemiology (AREA)
- Biomedical Technology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
fはフェルミ・ディラック分布であり、
EFはフェルミエネルギーであり、
Tは温度であり、
E(k、n)は波数ベクトルkとn番目のエネルギーバンドに対応する状態の電子のエネルギーであり、
添え字iとjはデカルト座標x、y、zを意味し、
積分はブリュアンゾーン(B.Z.)上で取られ、且つ、
総和は、電子と正孔それぞれのフェルミエネルギーの上下のエネルギーを持つバンド上で取られる。
21 基板
22 浅いトレンチ分離(STI)領域
25 超格子
Claims (25)
- 半導体デバイスの製造方法であって、
半導体処理チャンバ内の半導体基板上に複数の離間した構造を形成するステップであって、各構造は複数の積層された層のグループを含み、且つ、層の各グループは、ベース半導体部分を定義する複数の積層されたベースシリコン単分子層と、隣接ベースシリコン部分の結晶格子内に拘束された少なくとも1つの酸素単分子層とを含む、ステップ、
を含み、
前記酸素単分子層は、酸素源としてN2Oを使用して形成される、
方法。 - 形成するステップが、エピタキシャル化学蒸着(CVD)を使用して離間した構造の前記複数のグループを形成するステップを含む、請求項1に記載の方法。
- 前記ベースシリコン単分子層が、600℃〜800℃の範囲の温度で形成される、請求項1に記載の方法。
- 前記ベースシリコン単分子層が、665℃〜685℃の範囲の温度で形成される、請求項3に記載の方法。
- 前記酸素単分子層が、500℃〜750℃の範囲の温度で形成される、請求項1に記載の方法。
- 前記酸素源の曝露時間が1〜240秒である、請求項1に記載の方法。
- 前記酸素源が、2%未満のN2Oを有するヘリウム源ガスを含む、請求項1に記載の方法。
- 前記離間した構造の間に浅いトレンチ分離(STI)領域を形成するステップをさらに含む、請求項1に記載の方法。
- 前記STI領域は、前記離間した構造を形成する前に形成される、請求項8に記載の方法。
- 前記離間した構造の各々の上にそれぞれのキャップ半導体層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記キャップ半導体層を形成するステップは、580℃〜900℃の範囲の温度で前記キャップ半導体層を形成するステップを含む、請求項10に記載の方法。
- 半導体デバイスの製造方法であって、
エピタキシャル化学蒸着(CVD)を使用して半導体処理チャンバ内の隣接する構造間に浅いトレンチ分離(STI)領域を有する半導体基板上に複数の離間した構造を形成するステップであって、各構造は複数の積層された層のグループを含み、且つ、層の各グループは、ベース半導体部分を定義する複数の積層されたベースシリコン単分子層と、隣接ベースシリコン部分の結晶格子内に拘束された少なくとも1つの酸素単分子層とを含む、ステップ、
を含み、
前記酸素単分子層は、酸素源としてN2Oを使用して形成される、
方法。 - 前記ベースシリコン単分子層が、600℃〜800℃の範囲の温度で形成される、請求項12に記載の方法。
- 前記ベースシリコン単分子層が、665℃〜685℃の範囲の温度で形成される、請求項13に記載の方法。
- 前記酸素単分子層が、500℃〜750℃の範囲の温度で形成される、請求項12に記載の方法。
- 前記酸素源の曝露時間が1〜240秒である、請求項12に記載の方法。
- 前記酸素源が、2%未満のN2Oを有するヘリウム源ガスを含む、請求項12に記載の方法。
- 前記STI領域は、前記離間した構造を形成する前に形成される、請求項12に記載の方法。
- 前記離間した構造の各々の上にそれぞれのキャップ半導体層を形成するステップをさらに含む、請求項12に記載の方法。
- キャップ半導体層を形成するステップは、580℃〜900℃の範囲の温度でキャップ半導体層を形成するステップを含む、請求項12に記載の方法。
- 半導体デバイスの製造方法であって、
半導体処理チャンバ内の半導体基板上に複数の離間した構造を形成するステップであって、各構造は複数の積層された層のグループを含み、且つ、層の各グループは、ベース半導体部分を定義する複数の積層されたベースシリコン単分子層と、隣接ベースシリコン部分の結晶格子内に拘束された少なくとも1つの酸素単分子層とを含む、ステップ、
を含み、
前記酸素単分子層は、酸素源としてN2Oを使用して、500℃〜750℃の範囲の温度で形成され、且つ、
前記ベースシリコン単分子層が、600℃〜800℃の範囲の温度で形成される、
方法。 - 形成するステップが、エピタキシャル化学蒸着(CVD)を使用して離間した構造の前記複数のグループを形成するステップを含む、請求項21に記載の方法。
- 前記ベースシリコン単分子層が、665℃〜685℃の範囲の温度で形成される、請求項21に記載の方法。
- 前記酸素源の曝露時間が1〜240秒である、請求項21に記載の方法。
- 前記酸素源が、2%未満のN2Oを有するヘリウム源ガスを含む、請求項21に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/996,312 US9558939B1 (en) | 2016-01-15 | 2016-01-15 | Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source |
US14/996,312 | 2016-01-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017126747A true JP2017126747A (ja) | 2017-07-20 |
JP6342527B2 JP6342527B2 (ja) | 2018-06-13 |
Family
ID=57708383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017003204A Active JP6342527B2 (ja) | 2016-01-15 | 2017-01-12 | 酸素源としてのn2oを使用する原子層構造を包含する半導体デバイスの製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9558939B1 (ja) |
EP (1) | EP3193353A1 (ja) |
JP (1) | JP6342527B2 (ja) |
KR (1) | KR101905299B1 (ja) |
TW (1) | TWI616937B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024034433A1 (ja) * | 2022-08-08 | 2024-02-15 | 信越半導体株式会社 | 量子コンピュータ用シリコン基板の製造方法、量子コンピュータ用シリコン基板及び半導体装置 |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017197108A1 (en) | 2016-05-11 | 2017-11-16 | Atomera Incorporated | Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods |
US10170604B2 (en) | 2016-08-08 | 2019-01-01 | Atomera Incorporated | Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers |
US10191105B2 (en) | 2016-08-17 | 2019-01-29 | Atomera Incorporated | Method for making a semiconductor device including threshold voltage measurement circuitry |
TWI723262B (zh) | 2017-05-16 | 2021-04-01 | 美商安托梅拉公司 | 包含超晶格作為吸除層之半導體元件及方法 |
EP3639299A1 (en) | 2017-06-13 | 2020-04-22 | Atomera Incorporated | Semiconductor device with recessed channel array transistor (rcat) including a superlattice and associated methods |
US10109479B1 (en) | 2017-07-31 | 2018-10-23 | Atomera Incorporated | Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice |
US10741436B2 (en) | 2017-08-18 | 2020-08-11 | Atomera Incorporated | Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface |
US10608027B2 (en) | 2017-12-15 | 2020-03-31 | Atomera Incorporated | Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice |
US10529757B2 (en) | 2017-12-15 | 2020-01-07 | Atomera Incorporated | CMOS image sensor including pixels with read circuitry having a superlattice |
US10529768B2 (en) | 2017-12-15 | 2020-01-07 | Atomera Incorporated | Method for making CMOS image sensor including pixels with read circuitry having a superlattice |
US10615209B2 (en) | 2017-12-15 | 2020-04-07 | Atomera Incorporated | CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice |
US10461118B2 (en) | 2017-12-15 | 2019-10-29 | Atomera Incorporated | Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk |
US10276625B1 (en) | 2017-12-15 | 2019-04-30 | Atomera Incorporated | CMOS image sensor including superlattice to enhance infrared light absorption |
US10355151B2 (en) | 2017-12-15 | 2019-07-16 | Atomera Incorporated | CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk |
US10367028B2 (en) | 2017-12-15 | 2019-07-30 | Atomera Incorporated | CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice |
US10396223B2 (en) | 2017-12-15 | 2019-08-27 | Atomera Incorporated | Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk |
US10608043B2 (en) | 2017-12-15 | 2020-03-31 | Atomera Incorporation | Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice |
US10361243B2 (en) | 2017-12-15 | 2019-07-23 | Atomera Incorporated | Method for making CMOS image sensor including superlattice to enhance infrared light absorption |
US10304881B1 (en) | 2017-12-15 | 2019-05-28 | Atomera Incorporated | CMOS image sensor with buried superlattice layer to reduce crosstalk |
WO2019173668A1 (en) | 2018-03-08 | 2019-09-12 | Atomera Incorporated | Semiconductor device including enhanced contact structures having a superlattice and related methods |
US10468245B2 (en) | 2018-03-09 | 2019-11-05 | Atomera Incorporated | Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice |
US10727049B2 (en) | 2018-03-09 | 2020-07-28 | Atomera Incorporated | Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice |
US10763370B2 (en) | 2018-04-12 | 2020-09-01 | Atomera Incorporated | Inverted T channel field effect transistor (ITFET) including a superlattice |
US11355667B2 (en) | 2018-04-12 | 2022-06-07 | Atomera Incorporated | Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice |
US10593798B2 (en) | 2018-08-05 | 2020-03-17 | International Business Machines Corporation | Vertical transistor with one atomic layer gate length |
US10586864B2 (en) * | 2018-08-05 | 2020-03-10 | International Business Machines Corporation | Vertical transistor with one-dimensional edge contacts |
US10566191B1 (en) | 2018-08-30 | 2020-02-18 | Atomera Incorporated | Semiconductor device including superlattice structures with reduced defect densities |
US10811498B2 (en) | 2018-08-30 | 2020-10-20 | Atomera Incorporated | Method for making superlattice structures with reduced defect densities |
TWI720587B (zh) * | 2018-08-30 | 2021-03-01 | 美商安托梅拉公司 | 用於製作具較低缺陷密度超晶格結構之方法及元件 |
US20200135489A1 (en) * | 2018-10-31 | 2020-04-30 | Atomera Incorporated | Method for making a semiconductor device including a superlattice having nitrogen diffused therein |
US10818755B2 (en) | 2018-11-16 | 2020-10-27 | Atomera Incorporated | Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance |
US10593761B1 (en) | 2018-11-16 | 2020-03-17 | Atomera Incorporated | Method for making a semiconductor device having reduced contact resistance |
US10854717B2 (en) | 2018-11-16 | 2020-12-01 | Atomera Incorporated | Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance |
US10840337B2 (en) | 2018-11-16 | 2020-11-17 | Atomera Incorporated | Method for making a FINFET having reduced contact resistance |
US10580867B1 (en) | 2018-11-16 | 2020-03-03 | Atomera Incorporated | FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance |
US10580866B1 (en) | 2018-11-16 | 2020-03-03 | Atomera Incorporated | Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance |
US10840335B2 (en) | 2018-11-16 | 2020-11-17 | Atomera Incorporated | Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance |
US10847618B2 (en) | 2018-11-16 | 2020-11-24 | Atomera Incorporated | Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance |
US10840336B2 (en) | 2018-11-16 | 2020-11-17 | Atomera Incorporated | Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods |
US11329154B2 (en) | 2019-04-23 | 2022-05-10 | Atomera Incorporated | Semiconductor device including a superlattice and an asymmetric channel and related methods |
US10937888B2 (en) | 2019-07-17 | 2021-03-02 | Atomera Incorporated | Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices |
US10879357B1 (en) | 2019-07-17 | 2020-12-29 | Atomera Incorporated | Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice |
US10937868B2 (en) | 2019-07-17 | 2021-03-02 | Atomera Incorporated | Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices |
US10825901B1 (en) | 2019-07-17 | 2020-11-03 | Atomera Incorporated | Semiconductor devices including hyper-abrupt junction region including a superlattice |
US11183565B2 (en) | 2019-07-17 | 2021-11-23 | Atomera Incorporated | Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods |
US10868120B1 (en) | 2019-07-17 | 2020-12-15 | Atomera Incorporated | Method for making a varactor with hyper-abrupt junction region including a superlattice |
US10825902B1 (en) | 2019-07-17 | 2020-11-03 | Atomera Incorporated | Varactor with hyper-abrupt junction region including spaced-apart superlattices |
US10840388B1 (en) | 2019-07-17 | 2020-11-17 | Atomera Incorporated | Varactor with hyper-abrupt junction region including a superlattice |
US11437487B2 (en) | 2020-01-14 | 2022-09-06 | Atomera Incorporated | Bipolar junction transistors including emitter-base and base-collector superlattices |
US11177351B2 (en) | 2020-02-26 | 2021-11-16 | Atomera Incorporated | Semiconductor device including a superlattice with different non-semiconductor material monolayers |
US11302823B2 (en) | 2020-02-26 | 2022-04-12 | Atomera Incorporated | Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers |
US11075078B1 (en) | 2020-03-06 | 2021-07-27 | Atomera Incorporated | Method for making a semiconductor device including a superlattice within a recessed etch |
US11469302B2 (en) | 2020-06-11 | 2022-10-11 | Atomera Incorporated | Semiconductor device including a superlattice and providing reduced gate leakage |
US11569368B2 (en) | 2020-06-11 | 2023-01-31 | Atomera Incorporated | Method for making semiconductor device including a superlattice and providing reduced gate leakage |
US11837634B2 (en) | 2020-07-02 | 2023-12-05 | Atomera Incorporated | Semiconductor device including superlattice with oxygen and carbon monolayers |
EP4154320A1 (en) * | 2020-07-02 | 2023-03-29 | Atomera Incorporated | Method for making a semiconductor device using superlattices with different non-semiconductor thermal stabilities |
US12020926B2 (en) | 2021-03-03 | 2024-06-25 | Atomera Incorporated | Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice |
US11923418B2 (en) | 2021-04-21 | 2024-03-05 | Atomera Incorporated | Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer |
US11810784B2 (en) | 2021-04-21 | 2023-11-07 | Atomera Incorporated | Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer |
US11682712B2 (en) | 2021-05-26 | 2023-06-20 | Atomera Incorporated | Method for making semiconductor device including superlattice with O18 enriched monolayers |
US11728385B2 (en) | 2021-05-26 | 2023-08-15 | Atomera Incorporated | Semiconductor device including superlattice with O18 enriched monolayers |
US11721546B2 (en) | 2021-10-28 | 2023-08-08 | Atomera Incorporated | Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms |
US11631584B1 (en) | 2021-10-28 | 2023-04-18 | Atomera Incorporated | Method for making semiconductor device with selective etching of superlattice to define etch stop layer |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07153685A (ja) * | 1993-11-29 | 1995-06-16 | Oki Electric Ind Co Ltd | 歪ヘテロ超格子構造の薄膜形成方法 |
JPH07193059A (ja) * | 1993-12-27 | 1995-07-28 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002231717A (ja) * | 2000-11-03 | 2002-08-16 | Texas Instruments Inc | 酸化剤としてN2Oを用いた超薄膜SiO2 |
US20040262595A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears Llc | Semiconductor device including band-engineered superlattice |
JP2007043147A (ja) * | 2005-07-29 | 2007-02-15 | Samsung Electronics Co Ltd | 原子層蒸着工程を用いたシリコンリッチナノクリスタル構造物の形成方法及びこれを用いた不揮発性半導体装置の製造方法 |
US20070194298A1 (en) * | 2006-02-21 | 2007-08-23 | Rj Mears, Llc | Semiconductor device comprising a lattice matching layer |
Family Cites Families (125)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6127681Y2 (ja) | 1980-07-08 | 1986-08-18 | ||
US4485128A (en) | 1981-11-20 | 1984-11-27 | Chronar Corporation | Bandgap control in amorphous semiconductors |
JPH0656887B2 (ja) | 1982-02-03 | 1994-07-27 | 株式会社日立製作所 | 半導体装置およびその製法 |
US4594603A (en) | 1982-04-22 | 1986-06-10 | Board Of Trustees Of The University Of Illinois | Semiconductor device with disordered active region |
US4590399A (en) | 1984-02-28 | 1986-05-20 | Exxon Research And Engineering Co. | Superlattice piezoelectric devices |
US4882609A (en) | 1984-11-19 | 1989-11-21 | Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. | Semiconductor devices with at least one monoatomic layer of doping atoms |
JPS61145820U (ja) | 1985-03-04 | 1986-09-09 | ||
JPS61210679A (ja) | 1985-03-15 | 1986-09-18 | Sony Corp | 半導体装置 |
JPS61220339A (ja) | 1985-03-26 | 1986-09-30 | Nippon Telegr & Teleph Corp <Ntt> | 半導体材料特性の制御方法 |
JPS62219665A (ja) | 1986-03-20 | 1987-09-26 | Fujitsu Ltd | 超格子薄膜トランジスタ |
US4908678A (en) | 1986-10-08 | 1990-03-13 | Semiconductor Energy Laboratory Co., Ltd. | FET with a super lattice channel |
US5081513A (en) | 1991-02-28 | 1992-01-14 | Xerox Corporation | Electronic device with recovery layer proximate to active layer |
US5216262A (en) | 1992-03-02 | 1993-06-01 | Raphael Tsu | Quantum well structures useful for semiconductor devices |
JPH0643482A (ja) | 1992-07-24 | 1994-02-18 | Matsushita Electric Ind Co Ltd | 空間光変調素子およびその製造方法 |
US5955754A (en) | 1992-10-23 | 1999-09-21 | Symetrix Corporation | Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same |
US5357119A (en) | 1993-02-19 | 1994-10-18 | Board Of Regents Of The University Of California | Field effect devices having short period superlattice structures using Si and Ge |
US5606177A (en) | 1993-10-29 | 1997-02-25 | Texas Instruments Incorporated | Silicon oxide resonant tunneling diode structure |
US5466949A (en) | 1994-08-04 | 1995-11-14 | Texas Instruments Incorporated | Silicon oxide germanium resonant tunneling |
US5627386A (en) | 1994-08-11 | 1997-05-06 | The United States Of America As Represented By The Secretary Of The Army | Silicon nanostructure light-emitting diode |
US5561302A (en) | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5577061A (en) | 1994-12-16 | 1996-11-19 | Hughes Aircraft Company | Superlattice cladding layers for mid-infrared lasers |
FR2734097B1 (fr) | 1995-05-12 | 1997-06-06 | Thomson Csf | Laser a semiconducteurs |
US6326650B1 (en) | 1995-08-03 | 2001-12-04 | Jeremy Allam | Method of forming a semiconductor structure |
US6344271B1 (en) | 1998-11-06 | 2002-02-05 | Nanoenergy Corporation | Materials and products using nanostructured non-stoichiometric substances |
EP0843361A1 (en) | 1996-11-15 | 1998-05-20 | Hitachi Europe Limited | Memory device |
WO1998026316A1 (en) | 1996-12-13 | 1998-06-18 | Massachusetts Institute Of Technology | Tunable microcavity using nonlinear materials in a photonic crystal |
US5994164A (en) | 1997-03-18 | 1999-11-30 | The Penn State Research Foundation | Nanostructure tailoring of material properties using controlled crystallization |
US6255150B1 (en) | 1997-10-23 | 2001-07-03 | Texas Instruments Incorporated | Use of crystalline SiOx barriers for Si-based resonant tunneling diodes |
US6376337B1 (en) | 1997-11-10 | 2002-04-23 | Nanodynamics, Inc. | Epitaxial SiOx barrier/insulation layer |
JP3443343B2 (ja) | 1997-12-03 | 2003-09-02 | 松下電器産業株式会社 | 半導体装置 |
JP3547037B2 (ja) | 1997-12-04 | 2004-07-28 | 株式会社リコー | 半導体積層構造及び半導体発光素子 |
US6608327B1 (en) | 1998-02-27 | 2003-08-19 | North Carolina State University | Gallium nitride semiconductor structure including laterally offset patterned layers |
JP3854731B2 (ja) | 1998-03-30 | 2006-12-06 | シャープ株式会社 | 微細構造の製造方法 |
US6888175B1 (en) | 1998-05-29 | 2005-05-03 | Massachusetts Institute Of Technology | Compound semiconductor structure with lattice and polarity matched heteroepitaxial layers |
RU2142665C1 (ru) | 1998-08-10 | 1999-12-10 | Швейкин Василий Иванович | Инжекционный лазер |
US6586835B1 (en) | 1998-08-31 | 2003-07-01 | Micron Technology, Inc. | Compact system module with built-in thermoelectric cooling |
DE60042666D1 (de) | 1999-01-14 | 2009-09-17 | Panasonic Corp | Halbleiterbauelement und Verfahren zu dessen Herstellung |
EP1168539B1 (en) | 1999-03-04 | 2009-12-16 | Nichia Corporation | Nitride semiconductor laser device |
GB9905196D0 (en) | 1999-03-05 | 1999-04-28 | Fujitsu Telecommunications Eur | Aperiodic gratings |
US6993222B2 (en) | 1999-03-05 | 2006-01-31 | Rj Mears, Llc | Optical filter device with aperiodically arranged grating elements |
GB2385981B (en) | 1999-03-05 | 2003-11-05 | Nanovis Llc | Laser with aperiodic grating |
US6350993B1 (en) | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
US6281532B1 (en) | 1999-06-28 | 2001-08-28 | Intel Corporation | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering |
US6570898B2 (en) | 1999-09-29 | 2003-05-27 | Xerox Corporation | Structure and method for index-guided buried heterostructure AlGalnN laser diodes |
US6501092B1 (en) | 1999-10-25 | 2002-12-31 | Intel Corporation | Integrated semiconductor superlattice optical modulator |
RU2173003C2 (ru) | 1999-11-25 | 2001-08-27 | Септре Электроникс Лимитед | Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств |
DE10025264A1 (de) | 2000-05-22 | 2001-11-29 | Max Planck Gesellschaft | Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung |
US7902546B2 (en) | 2000-08-08 | 2011-03-08 | Translucent, Inc. | Rare earth-oxides, rare earth -nitrides, rare earth -phosphides and ternary alloys with silicon |
US7301199B2 (en) | 2000-08-22 | 2007-11-27 | President And Fellows Of Harvard College | Nanoscale wires and related devices |
US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
US6521549B1 (en) | 2000-11-28 | 2003-02-18 | Lsi Logic Corporation | Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit |
US20020100942A1 (en) | 2000-12-04 | 2002-08-01 | Fitzgerald Eugene A. | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
US6690699B2 (en) | 2001-03-02 | 2004-02-10 | Lucent Technologies Inc | Quantum cascade laser with relaxation-stabilized injection |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
EP1428262A2 (en) | 2001-09-21 | 2004-06-16 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
WO2003079415A2 (en) | 2002-03-14 | 2003-09-25 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
US6816530B2 (en) | 2002-09-30 | 2004-11-09 | Lucent Technologies Inc. | Nonlinear semiconductor light sources |
US7023010B2 (en) | 2003-04-21 | 2006-04-04 | Nanodynamics, Inc. | Si/C superlattice useful for semiconductor devices |
US20060267130A1 (en) | 2003-06-26 | 2006-11-30 | Rj Mears, Llc | Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween |
US20050282330A1 (en) | 2003-06-26 | 2005-12-22 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers |
US20060263980A1 (en) | 2003-06-26 | 2006-11-23 | Rj Mears, Llc, State Of Incorporation: Delaware | Method for making a semiconductor device including a floating gate memory cell with a superlattice channel |
US20060011905A1 (en) | 2003-06-26 | 2006-01-19 | Rj Mears, Llc | Semiconductor device comprising a superlattice dielectric interface layer |
US7033437B2 (en) | 2003-06-26 | 2006-04-25 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
US7586116B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
US7229902B2 (en) | 2003-06-26 | 2007-06-12 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
US20070063185A1 (en) | 2003-06-26 | 2007-03-22 | Rj Mears, Llc | Semiconductor device including a front side strained superlattice layer and a back side stress layer |
US7598515B2 (en) | 2003-06-26 | 2009-10-06 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
US7045813B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Semiconductor device including a superlattice with regions defining a semiconductor junction |
US7531828B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions |
US7514328B2 (en) | 2003-06-26 | 2009-04-07 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
US20060223215A1 (en) | 2003-06-26 | 2006-10-05 | Rj Mears, Llc | Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice |
US7446002B2 (en) | 2003-06-26 | 2008-11-04 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a superlattice dielectric interface layer |
US20070020860A1 (en) | 2003-06-26 | 2007-01-25 | Rj Mears, Llc | Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods |
US20070010040A1 (en) | 2003-06-26 | 2007-01-11 | Rj Mears, Llc | Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer |
EP1644983B1 (en) | 2003-06-26 | 2008-10-29 | Mears Technologies, Inc. | Semiconductor device including mosfet having bandgap-engineered superlattice |
US20060243964A1 (en) | 2003-06-26 | 2006-11-02 | Rj Mears, Llc | Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
US20070012910A1 (en) | 2003-06-26 | 2007-01-18 | Rj Mears, Llc | Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer |
US7586165B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Microelectromechanical systems (MEMS) device including a superlattice |
US20060292765A1 (en) | 2003-06-26 | 2006-12-28 | Rj Mears, Llc | Method for Making a FINFET Including a Superlattice |
US7227174B2 (en) | 2003-06-26 | 2007-06-05 | Rj Mears, Llc | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
US20040266116A1 (en) | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Methods of fabricating semiconductor structures having improved conductivity effective mass |
US7531829B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
US20060273299A1 (en) | 2003-06-26 | 2006-12-07 | Rj Mears, Llc | Method for making a semiconductor device including a dopant blocking superlattice |
US7535041B2 (en) | 2003-06-26 | 2009-05-19 | Mears Technologies, Inc. | Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
US20050279991A1 (en) | 2003-06-26 | 2005-12-22 | Rj Mears, Llc | Semiconductor device including a superlattice having at least one group of substantially undoped layers |
US7531850B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a memory cell with a negative differential resistance (NDR) device |
US7153763B2 (en) | 2003-06-26 | 2006-12-26 | Rj Mears, Llc | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing |
US7612366B2 (en) | 2003-06-26 | 2009-11-03 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice layer above a stress layer |
US20060231857A1 (en) | 2003-06-26 | 2006-10-19 | Rj Mears, Llc | Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device |
US20070020833A1 (en) | 2003-06-26 | 2007-01-25 | Rj Mears, Llc | Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer |
US20040262594A1 (en) | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Semiconductor structures having improved conductivity effective mass and methods for fabricating same |
US20070063186A1 (en) | 2003-06-26 | 2007-03-22 | Rj Mears, Llc | Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer |
US7045377B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
US7491587B2 (en) | 2003-06-26 | 2009-02-17 | Mears Technologies, Inc. | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer |
US7202494B2 (en) | 2003-06-26 | 2007-04-10 | Rj Mears, Llc | FINFET including a superlattice |
US20060220118A1 (en) | 2003-06-26 | 2006-10-05 | Rj Mears, Llc | Semiconductor device including a dopant blocking superlattice |
US7659539B2 (en) | 2003-06-26 | 2010-02-09 | Mears Technologies, Inc. | Semiconductor device including a floating gate memory cell with a superlattice channel |
US20070015344A1 (en) | 2003-06-26 | 2007-01-18 | Rj Mears, Llc | Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions |
US20060289049A1 (en) | 2003-06-26 | 2006-12-28 | Rj Mears, Llc | Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer |
KR100549008B1 (ko) | 2004-03-17 | 2006-02-02 | 삼성전자주식회사 | 등방성식각 기술을 사용하여 핀 전계효과 트랜지스터를제조하는 방법 |
TW200746421A (en) | 2005-07-15 | 2007-12-16 | Mears R J Llc | Semiconductor device including a channel with a non-semiconductor monolayer and associated methods |
US7517702B2 (en) | 2005-12-22 | 2009-04-14 | Mears Technologies, Inc. | Method for making an electronic device including a poled superlattice having a net electrical dipole moment |
TWI316294B (en) | 2005-12-22 | 2009-10-21 | Mears Technologies Inc | Method for making an electronic device including a selectively polable superlattice |
US20080012004A1 (en) | 2006-03-17 | 2008-01-17 | Mears Technologies, Inc. | Spintronic devices with constrained spintronic dopant |
US7625767B2 (en) | 2006-03-17 | 2009-12-01 | Mears Technologies, Inc. | Methods of making spintronic devices with constrained spintronic dopant |
US7985995B2 (en) * | 2006-08-03 | 2011-07-26 | Micron Technology, Inc. | Zr-substituted BaTiO3 films |
US7781827B2 (en) | 2007-01-24 | 2010-08-24 | Mears Technologies, Inc. | Semiconductor device with a vertical MOSFET including a superlattice and related methods |
US7928425B2 (en) | 2007-01-25 | 2011-04-19 | Mears Technologies, Inc. | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods |
US7880161B2 (en) | 2007-02-16 | 2011-02-01 | Mears Technologies, Inc. | Multiple-wavelength opto-electronic device including a superlattice |
US7863066B2 (en) | 2007-02-16 | 2011-01-04 | Mears Technologies, Inc. | Method for making a multiple-wavelength opto-electronic device including a superlattice |
US7812339B2 (en) | 2007-04-23 | 2010-10-12 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures |
CN100590803C (zh) * | 2007-06-22 | 2010-02-17 | 中芯国际集成电路制造(上海)有限公司 | 原子层沉积方法以及形成的半导体器件 |
JP2009054705A (ja) | 2007-08-24 | 2009-03-12 | Toshiba Corp | 半導体基板、半導体装置およびその製造方法 |
JP5159413B2 (ja) | 2008-04-24 | 2013-03-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20110215299A1 (en) | 2010-03-08 | 2011-09-08 | Mears Technologies, Inc. | Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods |
CN102870195A (zh) | 2010-04-28 | 2013-01-09 | 日本碍子株式会社 | 外延基板以及外延基板的制造方法 |
JP5708187B2 (ja) | 2011-04-15 | 2015-04-30 | サンケン電気株式会社 | 半導体装置 |
US8994002B2 (en) | 2012-03-16 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET having superlattice stressor |
US8497171B1 (en) | 2012-07-05 | 2013-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET method and structure with embedded underlying anti-punch through layer |
CN105900241B (zh) | 2013-11-22 | 2020-07-24 | 阿托梅拉公司 | 包括超晶格耗尽层堆叠的半导体装置和相关方法 |
CN106104805B (zh) * | 2013-11-22 | 2020-06-16 | 阿托梅拉公司 | 包括超晶格穿通停止层堆叠的垂直半导体装置和相关方法 |
US9745658B2 (en) * | 2013-11-25 | 2017-08-29 | Lam Research Corporation | Chamber undercoat preparation method for low temperature ALD films |
US9716147B2 (en) | 2014-06-09 | 2017-07-25 | Atomera Incorporated | Semiconductor devices with enhanced deterministic doping and related methods |
US9721790B2 (en) * | 2015-06-02 | 2017-08-01 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
-
2016
- 2016-01-15 US US14/996,312 patent/US9558939B1/en active Active
- 2016-12-13 TW TW105141224A patent/TWI616937B/zh active
- 2016-12-21 EP EP16205912.5A patent/EP3193353A1/en not_active Withdrawn
-
2017
- 2017-01-12 JP JP2017003204A patent/JP6342527B2/ja active Active
- 2017-01-13 KR KR1020170006171A patent/KR101905299B1/ko active IP Right Grant
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07153685A (ja) * | 1993-11-29 | 1995-06-16 | Oki Electric Ind Co Ltd | 歪ヘテロ超格子構造の薄膜形成方法 |
JPH07193059A (ja) * | 1993-12-27 | 1995-07-28 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002231717A (ja) * | 2000-11-03 | 2002-08-16 | Texas Instruments Inc | 酸化剤としてN2Oを用いた超薄膜SiO2 |
US20040262595A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears Llc | Semiconductor device including band-engineered superlattice |
JP2007521646A (ja) * | 2003-06-26 | 2007-08-02 | アール.ジェイ. メアーズ エルエルシー | バンド設計超格子を有する半導体装置 |
JP2007043147A (ja) * | 2005-07-29 | 2007-02-15 | Samsung Electronics Co Ltd | 原子層蒸着工程を用いたシリコンリッチナノクリスタル構造物の形成方法及びこれを用いた不揮発性半導体装置の製造方法 |
US20070194298A1 (en) * | 2006-02-21 | 2007-08-23 | Rj Mears, Llc | Semiconductor device comprising a lattice matching layer |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024034433A1 (ja) * | 2022-08-08 | 2024-02-15 | 信越半導体株式会社 | 量子コンピュータ用シリコン基板の製造方法、量子コンピュータ用シリコン基板及び半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR20170085983A (ko) | 2017-07-25 |
TWI616937B (zh) | 2018-03-01 |
US9558939B1 (en) | 2017-01-31 |
JP6342527B2 (ja) | 2018-06-13 |
TW201725609A (zh) | 2017-07-16 |
EP3193353A1 (en) | 2017-07-19 |
KR101905299B1 (ko) | 2018-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6342527B2 (ja) | 酸素源としてのn2oを使用する原子層構造を包含する半導体デバイスの製造方法 | |
TWI645562B (zh) | 在單一晶圓處理室中製作具有所需均勻度控制之加強型半導體結構之方法 | |
TWI679708B (zh) | 製作具有以回火超晶格方式形成埋置絕緣層之半導體元件之方法 | |
CN107112354B (zh) | 包括超晶格和替换金属栅极结构的半导体装置和相关方法 | |
AU2006344095B2 (en) | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing | |
US11978771B2 (en) | Gate-all-around (GAA) device including a superlattice | |
TW202036727A (zh) | 用於製作包含其中擴散有氮的超晶格之半導體元件之方法 | |
JP2009510727A (ja) | 表側の歪んでいる超格子層、裏側の応力層を有する半導体装置及び関連する方法 | |
EP3844819B1 (en) | Method for making superlattice structures with reduced defect densities | |
TWI852012B (zh) | 包含具有不同非半導體材料單層的超晶格之半導體元件及其相關方法 | |
TWI760113B (zh) | 包含具有不同非半導體材料單層的超晶格之半導體元件及其相關方法 | |
CN107864684B (zh) | 以期望的均匀性控制在单个晶片加工室中制造增强的半导体结构的方法 | |
TW202105726A (zh) | 設有含超晶格之突陡接面區之可變電容器及相關方法 | |
TW202105727A (zh) | 設有含分隔超晶格之突陡接面區之半導體元件及相關方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20171124 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180109 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180402 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180417 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180516 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6342527 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |