TWI574366B - 引線框及其製造方法以及半導體裝置及其製造方法 - Google Patents

引線框及其製造方法以及半導體裝置及其製造方法 Download PDF

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Publication number
TWI574366B
TWI574366B TW102103092A TW102103092A TWI574366B TW I574366 B TWI574366 B TW I574366B TW 102103092 A TW102103092 A TW 102103092A TW 102103092 A TW102103092 A TW 102103092A TW I574366 B TWI574366 B TW I574366B
Authority
TW
Taiwan
Prior art keywords
small
side surfaces
lead frame
pit
die holder
Prior art date
Application number
TW102103092A
Other languages
English (en)
Chinese (zh)
Other versions
TW201347123A (zh
Inventor
宮尾仁
Original Assignee
新光電氣工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新光電氣工業股份有限公司 filed Critical 新光電氣工業股份有限公司
Publication of TW201347123A publication Critical patent/TW201347123A/zh
Application granted granted Critical
Publication of TWI574366B publication Critical patent/TWI574366B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/048—Mechanical treatments, e.g. punching, cutting, deforming or cold welding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW102103092A 2012-01-31 2013-01-28 引線框及其製造方法以及半導體裝置及其製造方法 TWI574366B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012018461A JP5833459B2 (ja) 2012-01-31 2012-01-31 リードフレーム及びその製造方法と半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
TW201347123A TW201347123A (zh) 2013-11-16
TWI574366B true TWI574366B (zh) 2017-03-11

Family

ID=48837510

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102103092A TWI574366B (zh) 2012-01-31 2013-01-28 引線框及其製造方法以及半導體裝置及其製造方法

Country Status (5)

Country Link
US (1) US8778739B2 (https=)
JP (1) JP5833459B2 (https=)
KR (1) KR101957257B1 (https=)
CN (1) CN103227115B (https=)
TW (1) TWI574366B (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112014006397B4 (de) * 2014-02-24 2022-11-17 Mitsubishi Electric Corporation Leistungshalbleitermodul und Leistungseinheit
JP6408431B2 (ja) * 2015-06-11 2018-10-17 Ｓｈプレシジョン株式会社 リードフレーム、リードフレームの製造方法、および半導体装置
JP2017208486A (ja) * 2016-05-19 2017-11-24 株式会社ミスズ工業 表面に凹凸を有する金属部材、ヒートスプレッダ、半導体パッケージ及びそれらの製造方法
TWI623076B (zh) * 2016-11-02 2018-05-01 Fusheng Electronics Corporation 導線架製作方法
US10998255B2 (en) 2018-07-12 2021-05-04 Nxp Usa, Inc. Overmolded microelectronic packages containing knurled flanges and methods for the production thereof
TWI690045B (zh) * 2018-08-03 2020-04-01 欣興電子股份有限公司 構裝結構、其接合方法及用於其的線路板
WO2020053728A2 (en) * 2018-09-11 2020-03-19 Rjr Technologies, Inc. Air cavity package with improved connections between components
JP2021034705A (ja) * 2019-08-29 2021-03-01 Ｊｘ金属株式会社 金属板、金属樹脂複合体、半導体デバイス及び、金属板の製造方法
WO2024090029A1 (ja) * 2022-10-25 2024-05-02 富士電機株式会社 半導体モジュール、半導体装置、及び車両

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294409B1 (en) * 2000-01-27 2001-09-25 Siliconware Precisionware Industries Co., Ltd. Method of forming a constricted-mouth dimple structure on a leadframe die pad
US20050051876A1 (en) * 2003-09-08 2005-03-10 United Test And Assembly Test Center, Ltd. Integrated circuit package with leadframe enhancement and method of manufacturing the same
US20090256247A1 (en) * 2008-04-14 2009-10-15 Infineon Technologies Ag Semiconductor device and method including first and second carriers

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Publication number Priority date Publication date Assignee Title
JPS6378558A (ja) * 1986-09-22 1988-04-08 Hitachi Ltd 電子装置
JPS6442847A (en) * 1987-08-10 1989-02-15 Toshiba Corp Lead frame
JP2552887Y2 (ja) * 1991-03-29 1997-10-29 サンケン電気株式会社 絶縁物被覆電子部品
JPH077122A (ja) * 1993-06-17 1995-01-10 Fujitsu Ltd Ｉｃパッケージ
JPH07161896A (ja) 1993-12-02 1995-06-23 Hitachi Cable Ltd リードフレームとその製造方法
JP3339173B2 (ja) 1994-04-01 2002-10-28 松下電器産業株式会社 リードフレーム及びその製造方法及びそれを用いた半導体装置
JPH0864739A (ja) * 1994-08-24 1996-03-08 Hitachi Cable Ltd ディンプル加工を施したリードフレームの製造方法及びそのディンプル加工金型
JPH0864749A (ja) * 1994-08-25 1996-03-08 Hitachi Cable Ltd リードフレーム
US7091602B2 (en) 2002-12-13 2006-08-15 Freescale Semiconductor, Inc. Miniature moldlocks for heatsink or flag for an overmolded plastic package
US7476602B2 (en) * 2005-01-31 2009-01-13 Texas Instruments Incorporated N2 based plasma treatment for enhanced sidewall smoothing and pore sealing porous low-k dielectric films
JP2009260282A (ja) 2008-03-18 2009-11-05 Panasonic Corp パッケージ用リードフレーム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294409B1 (en) * 2000-01-27 2001-09-25 Siliconware Precisionware Industries Co., Ltd. Method of forming a constricted-mouth dimple structure on a leadframe die pad
US20050051876A1 (en) * 2003-09-08 2005-03-10 United Test And Assembly Test Center, Ltd. Integrated circuit package with leadframe enhancement and method of manufacturing the same
US20090256247A1 (en) * 2008-04-14 2009-10-15 Infineon Technologies Ag Semiconductor device and method including first and second carriers

Also Published As

Publication number Publication date
JP2013157536A (ja) 2013-08-15
US8778739B2 (en) 2014-07-15
TW201347123A (zh) 2013-11-16
KR101957257B1 (ko) 2019-03-13
KR20130088773A (ko) 2013-08-08
JP5833459B2 (ja) 2015-12-16
US20130193567A1 (en) 2013-08-01
CN103227115A (zh) 2013-07-31
CN103227115B (zh) 2017-04-12

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