TWI546907B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
TWI546907B
TWI546907B TW103123685A TW103123685A TWI546907B TW I546907 B TWI546907 B TW I546907B TW 103123685 A TW103123685 A TW 103123685A TW 103123685 A TW103123685 A TW 103123685A TW I546907 B TWI546907 B TW I546907B
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Taiwan
Prior art keywords
substrate
semiconductor device
semiconductor
sealing material
outer edge
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TW103123685A
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English (en)
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TW201523800A (zh
Inventor
Katsunori Shibuya
Soichi Homma
Yuusuke Takano
Shinpei Ishida
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Toshiba Kk
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Publication of TW201523800A publication Critical patent/TW201523800A/zh
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Publication of TWI546907B publication Critical patent/TWI546907B/zh

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Description

半導體裝置及其製造方法 [相關申請案]
本申請案享有將日本專利申請案2013-258655號(申請日：2013年12月13日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本實施形態係關於一種半導體裝置及其製造方法。
近年來，為了抑制自半導體裝置產生之EMI(Electro Magnetic Interference，電磁干擾)，存在於半導體封裝體之表面形成電磁遮罩之情況。於在半導體封裝體形成電磁遮罩時，半導體封裝體係將其背面(基板側之面)朝向搬送載具側而搭載於搬送載具上。於電磁遮罩之材料形成於半導體封裝體之表面時，電磁遮罩之材料亦形成於鄰接之複數個半導體封裝體間之搬送載具之表面。因此，電磁遮罩係於半導體封裝體之表面及搬送載具之表面作為連續膜而形成。於此種情形時，於形成電磁遮罩後，將半導體封裝體自搬送載具拉離時，於半導體封裝體之外緣產生電磁遮罩材料之毛邊。
本發明提供一種半導體裝置及其製造方法，該半導體裝置可抑制於在半導體封裝體之表面形成電磁遮罩時，於半導體封裝體之外緣產生遮罩材料之毛邊。
本實施形態之半導體裝置包括基板。半導體晶片配置於基板之 第1面上。密封材料被覆半導體晶片。導電膜被覆密封材料之正面及側面。於半導體裝置之基板側之外緣設置有階差、斜面或槽。
1‧‧‧搬送載具
10、11、12‧‧‧半導體裝置
20‧‧‧基板
21‧‧‧芯材
22、23‧‧‧阻焊劑
25‧‧‧端子
30‧‧‧密封材料
40‧‧‧電磁遮罩
50‧‧‧接地端子
60‧‧‧半導體晶片
70‧‧‧晶粒黏著材料
80‧‧‧金屬線
90‧‧‧槽
BL1‧‧‧第1刀片
BL2‧‧‧第2刀片
C、C10‧‧‧虛線框
D1‧‧‧深度
E20‧‧‧基板之外緣
E30‧‧‧密封材料之外緣
ST‧‧‧階差
TP‧‧‧正斜面
TPr‧‧‧倒斜面
TR‧‧‧槽
W1‧‧‧第1寬度
W2‧‧‧第2寬度
圖1(A)及(B)係表示於搬送載具1上搭載有第1實施形態之複數個半導體裝置10之狀態之圖。
圖2(A)及(B)係表示於半導體裝置10之表面形成有電磁遮罩40之狀態之剖面圖。
圖3係表示第1實施形態之半導體裝置10之製造方法之剖面圖。
圖4係表示繼圖3後之半導體裝置10之製造方法之剖面圖。
圖5係表示繼圖4後之半導體裝置10之製造方法之剖面圖。
圖6(A)及(B)係表示半導體封裝體之切割步驟之圖。
圖7係表示形成電磁遮罩40後之半導體裝置10之圖。
圖8係表示第1實施形態之變化例1之半導體裝置10及搬送載具1之構成之一例之剖面圖。
圖9係表示第1實施形態之變化例2之半導體裝置10及搬送載具1之構成之一例之剖面圖。
圖10(A)及(B)係表示於按照第2實施形態之半導體裝置11之表面形成有電磁遮罩40之狀態之圖。
圖11(A)及(B)係第2實施形態之半導體裝置11之剖面圖及後視圖。
圖12(A)及(B)係第3實施形態之半導體裝置12之剖面圖及後視圖。
以下，參照圖式說明本發明之實施形態。本實施形態並非限定本發明。於以下之實施形態中，基板之上下方向表示將設置有半導體晶片之面設為上之情形時之相對方向，存在與按照重力加速度之上下 方向不同之情況。
(第1實施形態)
圖1(A)及圖1(B)係表示於搬送載具1上搭載有第1實施形態之複數個半導體裝置10之狀態之圖。半導體裝置10(以下亦稱為半導體封裝體)係於搭載於搬送載具1之狀態下被搬入至濺鍍裝置。於濺鍍裝置中，電磁遮罩之材料形成於半導體裝置10之表面。半導體裝置10例如可為NAND(NOT AND，反及)型記憶體，但並無特別限定。電磁遮罩之形成方法除濺鍍法以外，亦可為鍍敷法、蒸鍍法、離子鍍著法等。
圖2(A)係表示於搭載於搬送載具1上之狀態下之半導體裝置10之表面形成有電磁遮罩40之狀態之剖面圖。圖2(B)係圖2(A)之虛線框C之部分之放大圖。
搭載於搬送載具1上之半導體裝置10包括基板20、密封材料30及電磁遮罩40。基板20例如可為PWB(Printed Wiring Board，印刷線路板)等基板。基板20包括芯材21、阻焊劑22、23、端子25及未圖示之配線。芯材21例如使用玻璃、樹脂、鐵氟龍(註冊商標)、陶瓷等材料而形成。阻焊劑22被覆芯材21之上表面(第1面)及配線，阻焊劑23被覆芯材21之背面(與第1面為相反側之第2面)。端子25設置於芯材21之背面。再者，阻焊劑23設置於芯材21之背面中端子25以外之區域。
密封材料30例如使用鑄模用樹脂等而形成。密封材料30被覆並保護配置於基板20之上表面(第1面)之單個或複數個半導體晶片(圖2中未圖示)。
作為導電膜之電磁遮罩40被覆密封材料30之正面及側面。電磁遮罩40係使用例如Cu、Ni、Ti、Au、Ag、Pd、Pt、Fe、Cr、SUS等金屬材料而形成。又，電磁遮罩40例如亦可為使用上述金屬材料之任意複數種材料之合金、或使用上述金屬材料之任意複數種材料之積層膜。
電磁遮罩40係與設置於半導體裝置10之封裝體側面(基板20之側面)之接地電極50電性連接。電磁遮罩40係為了抑制於半導體裝置10之封裝體內部產生之電磁波向封裝體外部漏出而設置。即，電磁遮罩40係為了抑制對半導體裝置10之周圍造成之EMI而設置。再者，接地電極50係經由任一端子25(接地端子)而與外部之接地電性連接。
本實施形態之半導體裝置10於具有基板20及密封材料30之半導體封裝體之基板20側之外緣設置有階差ST。更詳細而言，如圖2(B)所示，基板20之外緣E20較密封材料30之外緣E30位於更內側。藉此，藉由基板20之側面與密封材料30之側面而形成階差ST。
如此，藉由使階差ST設置於半導體封裝體之基板20側之外緣，於半導體裝置10搭載於搬送載具1時，如圖2(A)所示，半導體裝置10之階差ST與搬送載具1之表面形成於橫方向上開口之槽TR。藉此，可抑制於濺鍍電磁遮罩40之材料時電磁遮罩40之材料進入槽TR內。
當然，電磁遮罩40之材料由於以某種程度折入至背面側，故亦略微進入槽TR內。因此，槽TR無法完全防止電磁遮罩40之材料進入槽TR內。然而，形成於基板20與搬送載具1之間之電磁遮罩40之連續膜幾乎不存在、或非常薄。因此，於形成電磁遮罩40後，將半導體裝置10自搬送載具1提起時，不會產生電磁遮罩40之毛邊、或電磁遮罩40之毛邊非常小。
又，藉由使槽ST之深度變深，可抑制電磁遮罩40之材料進入槽ST內。槽ST之深度可藉由使基板20之尺寸變小、或使密封材料30之尺寸變大而實現。
如此，本實施形態之半導體裝置10可藉由於半導體封裝體之基板20側之外緣設置階差ST，而抑制形成電磁遮罩40時於基板20之側面形成電磁遮罩40之連續膜。藉此，可抑制於將半導體裝置10自搬送載具提起時於半導體裝置10之外緣產生毛邊。
又，即便因基板20之應變或搬送載具之應變，而於基板20之背面與搬送載具1之表面之間存在間隙，階差ST亦可抑制電磁遮罩40之材料進入基板20與搬送載具1之間。因此，根據本實施形態，可抑制端子25彼此因電磁遮罩40之材料而短路。
再者，亦考慮藉由於搬送載具設置支持半導體封裝體之中心部之突出部，而形成階差ST及槽TR。然而，於搬送載具設置突出部使成本變高。又，不易將高度與基板10相同或小於該基板10之突出部設置於搬送載具。進而，亦不易將半導體封裝體準確地置於突出部。因此，與藉由於搬送載具設置突出部而形成階差ST及槽TR相比，本實施形態之半導體裝置10之階差ST能以如下方式相對較容易地形成。
圖3~圖7係表示第1實施形態之半導體裝置10之製造方法之剖面圖。圖3~圖5表示至利用密封材料30進行之樹脂密封為止之步驟。圖6表示半導體封裝體之切割步驟。圖7表示形成電磁遮罩40後之半導體裝置10。再者，於圖3~圖5所示之步驟中，基板20或半導體封裝體尚未被單片化。因此，基板20或複數個半導體封裝體為連結之狀態。雖然未圖示，但例如複數個半導體封裝體以呈矩陣狀二維配置之方式形成於基板20上。
首先，如圖3所示，於基板20上搭載半導體晶片60。此時，半導體晶片60係藉由晶粒黏著材料70而接著於基板20上。晶粒黏著材料70為片狀或膏狀之任一者均可。於晶粒黏著材料70為附有切割保護膠帶之晶粒黏著膜之情形時，將切割保護膠帶貼附於半導體晶圓後進行半導體晶圓之切割。若將經單片化之半導體晶片60自切割保護膠帶卸除，則晶粒黏著膜殘留於半導體晶片60之背面。將具有晶粒黏著膜之半導體晶片60搭載於基板20上。於積層複數個半導體晶片60之情形時，於半導體晶片60上依序搭載其他半導體晶片60即可。
另一方面，於使用晶粒黏著膏作為晶粒黏著材料70之情形時， 於基板20上塗佈晶粒黏著膏，於該晶粒黏著膏上搭載半導體晶片60即可。於積層複數個半導體晶片60之情形時，於基板20上搭載半導體晶片60後，於該半導體晶片60上進而塗佈晶粒黏著膏，搭載另一半導體晶片60。藉此，獲得圖3所示之構造。
其次，為了確實地接著基板20與半導體晶片60、及接著半導體晶片60彼此，對基板20及半導體晶片60進行熱處理。其次，對半導體晶片60進行電漿清洗，清洗半導體晶片60之焊墊表面。電漿處理係使用Ar、O2、H2或Ar+H2等而執行。
其次，如圖4所示，利用金屬線80將半導體晶片60之焊墊與基板20之焊墊之間接合。金屬線80例如使用Au、Ag或Cu等而形成。進而，金屬線80亦可為塗佈有Pd之Cu。
其次，於執行電漿清洗後，如圖5所示，利用樹脂密封半導體晶片60及金屬線80。樹脂密封方法例如可為轉注成形法、壓縮成形法、全張成形法、射出成形法等。
其次，如圖6(A)及圖6(B)所示般進行封裝體切割。於封裝體切割中，使用刀片BL1及BL2將圖5所示之半導體封裝體10單片化。
於封裝體切割中，首先，如圖6(A)所示，使用具有第1寬度W1之第1刀片BL1自基板20之背面(與半導體晶片60之搭載面為相反側之面)切入切口(局部切割)。此時，切口之深度D1(參照圖6(B))可為與基板20大致相等之深度。即，第1刀片BL1亦可將切口切至基板20與樹脂材料30之界面為止，將基板20切斷。即便基板20被切斷，由於樹脂材料30相連結，故半導體封裝體彼此亦為連結之狀態。如此，使用第1刀片BL1於呈矩陣狀二維配置之複數個半導體封裝體間形成具有第1寬度W1及深度D1之槽。
再者，於可抑制電磁遮罩40之材料進入槽TR之範圍內，深度D1亦可小於基板20之厚度。反之，亦存在深度D1可大於基板20之厚度 之情況，但為了抑制電磁遮罩40之材料進入槽TR，深度D1過深欠佳。
其次，如圖6(B)所示，使用第2刀片BL2沿上述切口切斷密封材料30(全切)。即，第2刀片BL2係沿由第1刀片BL1形成之槽切斷半導體封裝體10間之樹脂材料30。藉此，複數個半導體封裝體10被單片化。此時，第2刀片BL2具有較第1寬度W1窄之第2寬度W2。第2刀片BL2切斷藉由第1刀片BL1形成之切口之大致中心部之樹脂材料30。藉此，於經單片化之半導體封裝體之基板20側之外緣形成階差ST。即，如圖6(A)及圖6(B)所示，藉由使用寬度不同之複數個刀片BL1、BL2切割半導體封裝體10，於基板20之背面之外緣形成階差ST。再者，雖然圖6(A)及圖6(B)中未圖示，但藉由切割，形成於基板20之切割線之接地端子50(參照圖2(A))露出。接地端子50係與接下來說明之電磁遮罩40電性連接。
其次，為了於半導體封裝體10之表面形成電磁遮罩40，如圖1所示，將半導體封裝體10搭載於搬送載具1。關於半導體封裝體10係將基板20側之面(基板20之背面)朝向搬送載具1搭載。
其次，如圖2所示，於半導體封裝體10之密封材料30之上表面及側面形成電磁遮罩40。此時，電磁遮罩40係使用濺鍍法、鍍敷法、蒸鍍法、離子鍍著法等而被覆半導體封裝體10之上表面及側面。
作為電磁遮罩40之一例，例如考慮Cu膜及SUS膜之積層膜。SUS膜係用以抑制Cu腐蝕之保護膜。Cu膜之厚度例如較佳為0.1μm~20μm。於Cu膜之厚度未達0.1μm之情形時，電磁遮罩之效果變弱。於Cu膜之厚度超過20μm之情形時，產生Cu膜剝離之問題。SUS層之膜厚例如較佳為0.01μm~5μm。於SUS層之膜厚未達0.01μm之情形時，作為保護層之效果變弱。於SUS層之膜厚大於等於5μm之情形時，亦產生SUS膜剝離之問題。又，由於需要大量SUS材料，故成本 變高。再者，保護層並不限於SUS等金屬膜，亦可為樹脂、陶瓷、金屬氧化膜、金屬氮化膜等。
自半導體封裝體之表面產生較多電磁雜訊。因此，設置於樹脂材料30之上表面之電磁遮罩40之厚度較佳為厚於設置於密封材料30之側面之電磁遮罩40之厚度。藉由使設置於樹脂材料30之上表面之電磁遮罩40變厚，可有效地抑制EMI。
其後，藉由將半導體封裝體10自搬送載具1取出，而完成圖7所示之半導體裝置10。
根據本實施形態，階差ST設置於半導體封裝體10之基板20側之外緣。藉此，於濺鍍電磁遮罩40之材料時，半導體裝置10之階差ST與搬送載具1之表面形成槽TR，槽TR抑制電磁遮罩40之材料朝向基板20之側面進入。其結果為，於形成電磁遮罩40後，將半導體封裝體10自搬送載具1提起時，不會產生電磁遮罩40之毛邊、或電磁遮罩40之毛邊非常小。
本實施形態之半導體封裝體10只要具有寬度不同之2個切割刀片即可形成，僅變更切割步驟即可實現。因此，本實施形態之半導體封裝體10無需製成呈特殊形狀之搬送載具或托盤，可容易且便宜地製造。
(變化例1)
圖8係表示第1實施形態之變化例1之半導體裝置10及搬送載具1之構成之一例的剖面圖。變化例1之基板20之側面係以基板20之晶片搭載面(第1面)之面積大於基板20之背面(第2面)之面積之方式具有斜面TP。如此，即便基板20之側面為正斜面TP之形狀，電磁遮罩40之材料亦不易形成於基板20之側面。因此，變化例1之半導體裝置10亦可獲得與第1實施形態相同之效果。
為了使基板20之側面為正斜面TP之形狀，只要使參照圖6(A)說 明之第1刀片BL1之刀尖為尖細形狀即可。藉此，於第1刀片BL1切割基板20後，基板20之側面如圖8所示般成為正斜面形狀。
變化例1之其他構成及製造方法可與第1實施形態之對應之構成及製造方法相同。藉此，變化例1可獲得與第1實施形態相同之效果。
(變化例2)
圖9係表示第1實施形態之變化例2之半導體裝置10及搬送載具1之構成之一例的剖面圖。變化例2之基板20之側面以基板20之背面(第2面)之面積大於晶片搭載面(第1面)之面積之方式具有斜面TPr。如此，即便基板20之側面為倒斜面TPr之形狀，電磁遮罩40之材料亦不易形成於基板20之側面。因此，變化例2之半導體裝置10亦可獲得與第1實施形態相同之效果。
為了使基板20之側面為倒斜面TPr之形狀，於參照圖6(A)說明之步驟時，使第1刀片BL1斜向地傾斜即可。或者，於參照圖6(B)說明之步驟後，使用另一刀片自橫方向切削基板20之側面即可。藉此，基板20之側面如圖9所示般成為正斜面形狀。
變化例2之其他構成及製造方法可與第1實施形態之對應之構成及製造方法相同。藉此，變化例2可獲得與第1實施形態相同之效果。
(第2實施形態)
圖10(A)係表示於按照第2實施形態之半導體裝置11之表面形成有電磁遮罩40之狀態之圖。圖10(B)係圖10(A)之虛線框C10之部分之放大圖。於第2實施形態之半導體裝置11中，於基板20之背面(第2面)之外緣去除阻焊劑23。藉此，藉由阻焊劑23與基板20形成階差ST。即，芯材21及阻焊劑22到達至密封材料30之外緣，阻焊劑21之外緣位於芯材21之外緣之內側。第2實施形態之其他構成可與第1實施形態之對應之構成相同。
圖11(A)及圖11(B)係第2實施形態之半導體裝置11之剖面圖及後 視圖。圖11(A)係沿圖11(B)之A-A線之剖面圖。再者，省略樹脂材料30內之半導體晶片之圖示。
如圖11(A)及圖11(B)所示，第2實施形態之半導體裝置11於半導體封裝體之基板20之背面之外周設置有階差ST。階差ST係設置於芯材21與阻焊劑23之間。因此，如圖10(B)所示，半導體裝置11中，半導體封裝體與搬送載具1之間之槽TR變得非常窄。由此，可進而抑制於形成電磁遮罩40時，電磁遮罩40之材料進入槽TR內，可進而抑制於阻焊劑23之側面形成電磁遮罩40之連續膜。其結果為，可更有效地抑制於將半導體裝置10自搬送載具提起時，於半導體裝置10之外緣產生毛邊。進而，第2實施形態之半導體裝置11可獲得與第1實施形態相同之效果。
關於半導體裝置11，只要加工基板20之背面之阻焊劑23即可。例如，於圖11(B)所示之端子25之區域，阻焊劑23係使用微影法去除。此時，亦同時去除半導體封裝體之外緣之阻焊劑23即可。又，於藉由印刷法形成阻焊劑23之情形時，只要不於半導體封裝體之外緣塗佈阻焊劑23即可。即，第2實施形態之階差ST可不使用複數個切割刀片，而使用形成阻焊劑23時之微影技術或印刷法而形成。由此，第2實施形態之半導體裝置11可進一步容易且便宜地製造。
再者，第2實施形態之階差ST亦可與第1實施形態同樣地藉由切割步驟而形成。例如，只要使圖6(A)所示之利用第1刀片BL1之局部切割之深度D1為與阻焊劑23之厚度大致相等之深度即可。藉此，於維持著芯材21及阻焊劑22之狀態下，第1刀片BL1可切割阻焊劑23。若以此方式使深度D1變淺，則可藉由切割步驟形成第2實施形態之階差ST。
(第3實施形態)
圖12(A)及圖12(B)係第3實施形態之半導體裝置12之剖面圖及後 視圖。再者，圖12(A)係沿圖12(B)之A-A線之剖面圖。如圖12(A)及圖12(B)所示，第3實施形態之半導體裝置12沿半導體封裝體之基板20之背面之外周具有環狀之槽90。槽90係藉由利用微影法對阻焊劑23進行加工而形成。
槽90較佳為設置於距基板20之端10μm~500μm之位置。例如，於槽90之位置距基板20之端未達10μm之情形時，不易使用微影法精度良好地形成槽90。另一方面，若槽90之位置距基板20之端超過500μm，則槽90與端子25重疊。
藉由於基板20之背面設置有槽90，可抑制於形成電磁遮罩40時，電磁遮罩40之材料折入至背面。例如，於基板20或搬送載具1產生應變之情形時，於基板20之背面與搬送載具1之表面之間形成間隙。進入該間隙之電磁遮罩40之材料滯留於槽90之空間。因此，電磁遮罩40之材料被捕捉至槽90之空間，幾乎未到達至端子25。藉此，可抑制相互鄰接之端子25電性短路。
另一方面，電磁遮罩40被覆樹脂材料30之上表面及側面，將基板20之背面被覆至槽90之近前。因此，電磁遮罩40可更有效地抑制EMI，且可使阻焊劑23與芯材21之密接性提高。
再者，半導體晶片60及密封材料30之形態無特別限定。雖未圖示，但例如半導體晶片60亦可為具有金屬凸塊之形態。於此情形時，於切割半導體晶圓後，將經單片化之半導體晶片60覆晶安裝於基板20上。其次，於半導體晶片60與基板20間塗佈樹脂。其次，以密封材料30被覆半導體晶片。其後之步驟可與上述實施形態相同。藉此，即便為具有金屬凸塊之半導體晶片60，亦可獲得上述實施形態之效果。
雖然說明了本發明之若干實施形態，但該等實施形態係作為示例而提示者，並非意圖限定發明之範圍。該等實施形態可藉由其他各種形態而實施，可於不脫離發明之主旨之範圍內進行各種省略、替 換、變更。該等實施形態或其變化係與包含於發明之範圍或主旨同樣地，包含於申請專利範圍中記載之發明及其均等之範圍者。
1‧‧‧搬送載具
10‧‧‧半導體裝置
20‧‧‧基板
21‧‧‧芯材
22、23‧‧‧阻焊劑
25‧‧‧端子
30‧‧‧密封材料
40‧‧‧電磁遮罩
50‧‧‧接地端子
C‧‧‧虛線框
E20‧‧‧基板之外緣
E30‧‧‧密封材料之外緣
ST‧‧‧階差
TR‧‧‧槽

Claims (7)

  1. 一種半導體裝置，其包括：基板；半導體晶片，其配置於上述基板之第1面上；密封材料，其被覆上述半導體晶片；及導電膜，其被覆上述密封材料之上表面及側面；且於上述基板之與上述第1面相反側之第2面之外緣設置有階差、斜面或槽。
  2. 如請求項1之半導體裝置，其中上述基板之外緣較上述密封材料之外緣位於更內側，上述階差係藉由上述基板與上述密封材料而形成。
  3. 如請求項1之半導體裝置，其中上述基板包含被覆上述第2面之絕緣膜；於上述第2面之外緣去除上述絕緣膜，上述階差係藉由上述絕緣膜與上述基板而形成。
  4. 如請求項1至3中任一項之半導體裝置，其中上述基板包含被覆上述第2面之絕緣膜；且上述絕緣膜沿上述基板之上述第2面之外緣具有環狀之槽。
  5. 如請求項1至3中任一項之半導體裝置，其中上述導電膜係自上述密封材料之上表面向側面連續設置，於上述階差、上述斜面或上述槽間斷。
  6. 一種半導體裝置之製造方法，其包括：藉由以密封材料被覆配置於基板之第1面上之半導體晶片，而於上述基板上形成複數個半導體封裝體；自上述基板之與上述第1面為相反側之第2面對上述基板切入 具有第1深度及最大值為第1寬度之切口；藉由以較上述第1寬度窄之第2寬度沿上述切口切斷上述密封材料，將上述半導體封裝體單片化；於上述半導體封裝體之單片化後，於將上述第2面朝向載具之狀態下將複數個上述半導體封裝體搭載於該載具；於上述半導體封裝體之上述密封材料之上表面及側面形成導電膜。
  7. 如請求項6之半導體裝置之製造方法，其中上述切口係使用具有尖細形狀之刀片而形成。
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