CN104716105A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN104716105A
CN104716105A CN201410453745.3A CN201410453745A CN104716105A CN 104716105 A CN104716105 A CN 104716105A CN 201410453745 A CN201410453745 A CN 201410453745A CN 104716105 A CN104716105 A CN 104716105A
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Prior art keywords
substrate
semiconductor device
semiconductor
package body
electromagnetic shielding
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CN104716105B (zh
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涩谷克则
本间庄一
高野勇佑
石田心平
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Kioxia Corp
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Toshiba Corp
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Abstract

本发明提供一种半导体装置及其制造方法，该半导体装置可以抑制在半导体封装体的表面形成电磁屏蔽时，在半导体封装体的外缘产生屏蔽材料的毛边，且抑制半导体封装体的背面的端子间的短路。本实施方式的半导体装置包括基板。半导体芯片配置于基板的第1面上。密封材料被覆半导体芯片。导电膜被覆密封材料的上表面及侧面。在基板的与第1面相反侧的第2面的外缘设置着阶差、斜面或槽。

Description

半导体装置及其制造方法
[相关申请案] 
本申请案享有将日本专利申请案2013-258655号(申请日：2013年12月13日)作为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。 
技术领域
本实施方式涉及一种半导体装置及其制造方法。 
背景技术
近年来，为了抑制从半导体装置产生的EMI(Electro Magnetic Interference，电磁干扰)，存在于半导体封装体的表面形成电磁屏蔽的情况。当在半导体封装体形成电磁屏蔽时，半导体封装体是将其背面(基板侧的面)朝向搬送载具侧而搭载于搬送载具上。当电磁屏蔽的材料形成于半导体封装体的表面时，电磁屏蔽的材料也形成于邻接的多个半导体封装体间的搬送载具的表面。因此，电磁屏蔽是在半导体封装体的表面及搬送载具的表面作为连续膜而形成。在此种情况下，当形成电磁屏蔽后，将半导体封装体从搬送载具拉离时，在半导体封装体的外缘产生电磁屏蔽材料的毛边。 
发明内容
本发明提供一种半导体装置及其制造方法，该半导体装置可以抑制于在半导体封装体的表面形成电磁屏蔽时，在半导体封装体的外缘产生屏蔽材料的毛边。 
本实施方式的半导体装置包括基板。半导体芯片配置于基板的第1面上。密封材料被覆半导体芯片。导电膜被覆密封材料的上表面及侧面。在基板的与第1面相反侧的第2面的外缘设置着阶差、斜面或槽。 
附图说明
图1(A)及(B)是表示在搬送载具1上搭载着第1实施方式的多个半导体装置10的状 态的图。 
图2(A)及(B)是表示在半导体装置10的表面形成着电磁屏蔽40的状态的剖视图。 
图3是表示第1实施方式的半导体装置10的制造方法的剖视图。 
图4是表示继图3后的半导体装置10的制造方法的剖视图。 
图5是表示继图4后的半导体装置10的制造方法的剖视图。 
图6(A)及(B)是表示半导体封装体的切割步骤的图。 
图7是表示形成电磁屏蔽40后的半导体装置10的图。 
图8是表示第1实施方式的变化例1的半导体装置10及搬送载具1的构成的一例的剖视图。 
图9是表示第1实施方式的变化例2的半导体装置10及搬送载具1的构成的一例的剖视图。 
图10(A)及(B)是表示在按照第2实施方式的半导体装置11的表面形成着电磁屏蔽40的状态的图。 
图11(A)及(B)是第2实施方式的半导体装置11的剖视图及后视图。 
图12(A)及(B)是第3实施方式的半导体装置12的剖视图及后视图。 
具体实施方式
以下，参照附图说明本发明的实施方式。本实施方式并非限定本发明。在以下的实施方式中，基板的上下方向表示将设置着半导体芯片的面设为上的情况下的相对方向，存在与按照重力加速度的上下方向不同的情况。 
(第1实施方式) 
图1(A)及图1(B)是表示在搬送载具1上搭载着第1实施方式的多个半导体装置10的状态的图。半导体装置10(以下也称为半导体封装体)是在搭载于搬送载具1的状态下被搬入至溅镀装置。在溅镀装置中，电磁屏蔽的材料形成于半导体装置10的表面。半导体装置10例如可以为NAND(NOT AND，与非)型存储器，但并无特别限定。电磁屏蔽的形成方法除溅镀法以外，也可以为镀敷法、蒸镀法、离子镀着法等。 
图2(A)是表示在搭载于搬送载具1上的状态下的半导体装置10的表面形成着电磁屏蔽40的状态的剖视图。图2(B)是图2(A)的虚线框C的部分的放大图。 
搭载于搬送载具1上的半导体装置10包括基板20、密封材料30及电磁屏蔽40。基板20例如可以为PWB(Printed Wiring Board，印刷线路板)等基板。基板20包括芯材 21、阻焊剂22、23、端子25及未图示的配线。芯材21例如使用玻璃、树脂、特富龙(注册商标)、陶瓷等材料而形成。阻焊剂22被覆芯材21的上表面(第1面)及配线，阻焊剂23被覆芯材21的背面(与第1面为相反侧的第2面)。端子25设置于芯材21的背面。此外，阻焊剂23设置于芯材21的背面中端子25以外的区域。 
密封材料30例如使用铸模用树脂等而形成。密封材料30被覆并保护配置于基板20的上表面(第1面)的单个或多个半导体芯片(图2中未图示)。 
作为导电膜的电磁屏蔽40被覆密封材料30的正面及侧面。电磁屏蔽40是使用例如Cu、Ni、Ti、Au、Ag、Pd、Pt、Fe、Cr、SUS等金属材料而形成。另外，电磁屏蔽40例如也可以为使用所述金属材料的任意复数种材料的合金、或使用所述金属材料的任意复数种材料的积层膜。 
电磁屏蔽40是与设置于半导体装置10的封装体侧面(基板20的侧面)的接地电极50电性连接。电磁屏蔽40是为了抑制于半导体装置10的封装体内部产生的电磁波向封装体外部漏出而设置。即，电磁屏蔽40是为了抑制对半导体装置10的周围造成的EMI而设置。此外，接地电极50是经由任一端子25(接地端子)而与外部的接地电性连接。 
本实施方式的半导体装置10在具有基板20及密封材料30的半导体封装体的基板20侧的外缘设置着阶差ST。更详细来说，如图2(B)所示，基板20的外缘E20相比密封材料30的外缘E30位于更内侧。由此，通过基板20的侧面与密封材料30的侧面而形成阶差ST。 
这样，通过阶差ST设置于半导体封装体的基板20侧的外缘，当半导体装置10搭载于搬送载具1时，如图2(A)所示，半导体装置10的阶差ST与搬送载具1的表面形成于横方向上开口的槽TR。由此，可以抑制溅镀电磁屏蔽40的材料时电磁屏蔽40的材料进入槽TR内。 
当然，电磁屏蔽40的材料由于以某种程度折入至背面侧，所以也略微进入槽TR内。因此，槽TR无法完全防止电磁屏蔽40的材料进入槽TR内。然而，形成于基板20与搬送载具1之间的电磁屏蔽40的连续膜几乎不存在、或非常薄。因此，当形成电磁屏蔽40后，将半导体装置10从搬送载具1提起时，不会产生电磁屏蔽40的毛边、或电磁屏蔽40的毛边非常小。 
另外，通过使槽ST的深度变深，可以抑制电磁屏蔽40的材料进入槽ST内。槽ST的深度可以通过使基板20的尺寸变小、或使密封材料30的尺寸变大而实现。 
这样，本实施方式的半导体装置10可以通过在半导体封装体的基板20侧的外缘设置阶差ST，而抑制形成电磁屏蔽40时在基板20的侧面形成电磁屏蔽40的连续膜。由 此，可以抑制将半导体装置10从搬送载具提起时在半导体装置10的外缘产生毛边。 
另外，即便因基板20的应变或搬送载具的应变，而在基板20的背面与搬送载具1的表面之间存在间隙，阶差ST也可以抑制电磁屏蔽40的材料进入基板20与搬送载具1之间。因此，根据本实施方式，可以抑制端子25彼此因电磁屏蔽40的材料而短路。 
此外，也考虑通过在搬送载具设置支持半导体封装体的中心部的突出部，而形成阶差ST及槽TR。然而，在搬送载具设置突出部使成本变高。另外，不易将高度与基板10相同或小于等于该基板10的突出部设置于搬送载具。进而，也不易将半导体封装体准确地置于突出部。因此，与通过在搬送载具设置突出部而形成阶差ST及槽TR相比，本实施方式的半导体装置10的阶差ST能以如下方式相对较容易地形成。 
图3～图7是表示第1实施方式的半导体装置10的制造方法的剖视图。图3～图5表示至利用密封材料30进行的树脂密封为止的步骤。图6表示半导体封装体的切割步骤。图7表示形成电磁屏蔽40后的半导体装置10。此外，于图3～图5所示的步骤中，基板20或半导体封装体还没有被单片化。因此，基板20或多个半导体封装体为连结的状态。虽然未图示，但例如多个半导体封装体以呈矩阵状二维配置的方式形成于基板20上。 
首先，如图3所示，在基板20上搭载半导体芯片60。此时，半导体芯片60是通过芯片黏着材料70而接着于基板20上。芯片黏着材料70为片状或膏状的任一个均可。在芯片黏着材料70为附有切割保护胶带的芯片黏着膜的情况下，将切割保护胶带贴附于半导体晶片后进行半导体晶片的切割。如果将单片化的半导体芯片60从切割保护胶带卸除，则芯片黏着膜残留于半导体芯片60的背面。将具有芯片黏着膜的半导体芯片60搭载于基板20上。在积层多个半导体芯片60的情况下，在半导体芯片60上依序搭载其他半导体芯片60即可。 
另一方面，在使用芯片黏着膏作为芯片黏着材料70的情况下，在基板20上涂布芯片黏着膏，于该芯片黏着膏上搭载半导体芯片60即可。在积层多个半导体芯片60的情况下，在基板20上搭载半导体芯片60后，在该半导体芯片60上进而涂布芯片黏着膏，搭载另一半导体芯片60。由此，获得图3所示的构造。 
接着，为了确实地接着基板20与半导体芯片60、及接着半导体芯片60彼此，对基板20及半导体芯片60进行热处理。接着，对半导体芯片60进行电浆清洗，清洗半导体芯片60的焊垫表面。电浆处理是使用Ar、O2、H2或Ar+H2等而执行。 
接着，如图4所示，利用金属线80将半导体芯片60的焊垫与基板20的焊垫之间接合。金属线80例如使用Au、Ag或Cu等而形成。进而，金属线80也可以为涂布着 Pd的Cu。 
接着，当执行电浆清洗后，如图5所示，利用树脂密封半导体芯片60及金属线80。树脂密封方法例如可为转注成形法、压缩成形法、全张成形法、射出成形法等。 
接着，如图6(A)及图6(B)所示般进行封装体切割。于封装体切割中，使用刀片BL1及BL2将图5所示的半导体封装体10单片化。 
在封装体切割中，首先，如图6(A)所示，使用具有第1宽度W1的第1刀片BL1从基板20的背面(与半导体芯片60的搭载面为相反侧的面)切入切口(局部切割)。此时，切口的深度D1(参照图6(B))可为与基板20大致相等的深度。即，第1刀片BL1也可以将切口切至基板20与树脂材料30的界面为止，将基板20切断。即便基板20被切断，由于树脂材料30相连结，所以半导体封装体彼此也为连结的状态。这样，使用第1刀片BL1在呈矩阵状二维配置的多个半导体封装体间形成具有第1宽度W1及深度D1的槽。 
此外，在能够抑制电磁屏蔽40的材料进入槽TR的范围内，深度D1也可以小于基板20的厚度。反之，也存在深度D1可以大于基板20的厚度的情况，但为了抑制电磁屏蔽40的材料进入槽TR，深度D1过深欠佳。 
接着，如图6(B)所示，使用第2刀片BL2沿所述切口切断密封材料30(全切)。即，第2刀片BL2是沿由第1刀片BL1形成的槽切断半导体封装体10间的树脂材料30。由此，多个半导体封装体10被单片化。此时，第2刀片BL2具有比第1宽度W1窄的第2宽度W2。第2刀片BL2切断通过第1刀片BL1形成的切口的大致中心部的树脂材料30。由此，在被单片化的半导体封装体的基板20侧的外缘形成阶差ST。即，如图6(A)及图6(B)所示，通过使用宽度不同的多个刀片BL1、BL2切割半导体封装体10，在基板20的背面的外缘形成阶差ST。此外，虽然图6(A)及图6(B)中未图示，但通过切割，形成于基板20的切割线的接地端子50(参照图2(A))露出。接地端子50是与接下来说明的电磁屏蔽40电性连接。 
接着，为了在半导体封装体10的表面形成电磁屏蔽40，如图1所示，将半导体封装体10搭载于搬送载具1。半导体封装体10是将基板20侧的面(基板20的背面)朝向搬送载具1搭载。 
接着，如图2所示，在半导体封装体10的密封材料30的上表面及侧面形成电磁屏蔽40。此时，电磁屏蔽40是使用溅镀法、镀敷法、蒸镀法、离子镀着法等而被覆半导体封装体10的上表面及侧面。 
作为电磁屏蔽40的一例，例如考虑Cu膜及SUS膜的积层膜。SUS膜是用来抑制 Cu腐蚀的保护膜。Cu膜的厚度例如优选0.1μm～20μm。在Cu膜的厚度小于0.1μm的情况下，电磁屏蔽的效果变弱。在Cu膜的厚度超过20μm的情况下，产生Cu膜剥离的问题。SUS层的膜厚例如优选0.01μm～5μm。在SUS层的膜厚小于0.01μm的情况下，作为保护层的效果变弱。在SUS层的膜厚大于等于5μm的情况下，也产生SUS膜剥离的问题。另外，由于需要大量SUS材料，所以成本变高。此外，保护层并不限于SUS等金属膜，也可以为树脂、陶瓷、金属氧化膜、金属氮化膜等。 
从半导体封装体的表面产生较多电磁噪音。因此，设置于树脂材料30的上表面的电磁屏蔽40的厚度优选厚于设置于密封材料30的侧面的电磁屏蔽40的厚度。通过使设置于树脂材料30的上表面的电磁屏蔽40变厚，可以有效地抑制EMI。 
然后，通过将半导体封装体10从搬送载具1取出，图7所示的半导体装置10完成。 
根据本实施方式，阶差ST设置于半导体封装体10的基板20侧的外缘。由此，当溅镀电磁屏蔽40的材料时，半导体装置10的阶差ST与搬送载具1的表面形成槽TR，槽TR抑制电磁屏蔽40的材料朝向基板20的侧面进入。结果，当形成电磁屏蔽40后，将半导体封装体10从搬送载具1提起时，不会产生电磁屏蔽40的毛边、或电磁屏蔽40的毛边非常小。 
本实施方式的半导体封装体10只要具有宽度不同的2个切割刀片则可形成，仅变更切割步骤即可实现。因此，本实施方式的半导体封装体10无需制成呈特殊形状的搬送载具或托盘，可以容易且便宜地制造。 
(变化例1) 
图8是表示第1实施方式的变化例1的半导体装置10及搬送载具1的构成的一例的剖视图。变化例1的基板20的侧面是以基板20的芯片搭载面(第1面)的面积大于基板20的背面(第2面)的面积的方式具有斜面TP。这样，即便基板20的侧面为正斜面TP的形状，电磁屏蔽40的材料也不易形成于基板20的侧面。因此，变化例1的半导体装置10也可以获得与第1实施方式相同的效果。 
为了使基板20的侧面为正斜面TP的形状，只要使参照图6(A)说明的第1刀片BL1的刀尖为尖细形状即可。由此，当第1刀片BL1切割基板20后，基板20的侧面像图8所示那样成为正斜面形状。 
变化例1的其他构成及制造方法可以与第1实施方式的对应的构成及制造方法相同。由此，变化例1可以获得与第1实施方式相同的效果。 
(变化例2) 
图9是表示第1实施方式的变化例2的半导体装置10及搬送载具1的构成的一例 的剖视图。变化例2的基板20的侧面以基板20的背面(第2面)的面积大于芯片搭载面(第1面)的面积的方式具有斜面TPr。这样，即便基板20的侧面为倒斜面TPr的形状，电磁屏蔽40的材料也不易形成于基板20的侧面。因此，变化例2的半导体装置10也可以获得与第1实施方式相同的效果。 
为了使基板20的侧面为倒斜面TPr的形状，参照图6(A)说明的步骤时，使第1刀片BL1斜向地倾斜即可。或者，在参照图6(B)说明的步骤后，使用另一刀片从横方向切削基板20的侧面即可。由此，基板20的侧面像图9所示那样成为正斜面形状。 
变化例2的其他构成及制造方法可以与第1实施方式的对应的构成及制造方法相同。由此，变化例2可以获得与第1实施方式相同的效果。 
(第2实施方式) 
图10(A)是表示在按照第2实施方式的半导体装置11的表面形成着电磁屏蔽40的状态的图。图10(B)是图10(A)的虚线框C10的部分的放大图。于第2实施方式的半导体装置11中，在基板20的背面(第2面)的外缘去除阻焊剂23。由此，通过阻焊剂23与基板20形成阶差ST。即，芯材21及阻焊剂22到达至密封材料30的外缘，阻焊剂21的外缘位于芯材21的外缘的内侧。第2实施方式的其他构成可以与第1实施方式的对应的构成相同。 
图11(A)及图11(B)是第2实施方式的半导体装置11的剖视图及后视图。图11(A)是沿图11(B)的A-A线的剖视图。此外，省略树脂材料30内的半导体芯片的图示。 
如图11(A)及图11(B)所示，第2实施方式的半导体装置11在半导体封装体的基板20的背面的外周设置着阶差ST。阶差ST是设置于芯材21与阻焊剂23之间。因此，如图10(B)所示，半导体装置11中，半导体封装体与搬送载具1之间的槽TR变得非常窄。由此，可以进而抑制形成电磁屏蔽40时，电磁屏蔽40的材料进入槽TR内，可以进而抑制阻焊剂23的侧面形成电磁屏蔽40的连续膜。结果，可以更有效地抑制将半导体装置10从搬送载具提起时，在半导体装置10的外缘产生毛边。进而，第2实施方式的半导体装置11可以获得与第1实施方式相同的效果。 
关于半导体装置11，只要加工基板20的背面的阻焊剂23即可。例如，在图11(B)所示的端子25的区域，阻焊剂23是使用光刻法去除。此时，也同时去除半导体封装体的外缘的阻焊剂23即可。另外，在通过印刷法形成阻焊剂23的情况下，只要不在半导体封装体的外缘涂布阻焊剂23即可。即，第2实施方式的阶差ST可不使用多个切割刀片，而使用形成阻焊剂23时的光刻技术或印刷法而形成。由此，第2实施方式的半导体装置11可以进一步容易且便宜地制造。 
此外，第2实施方式的阶差ST也可以与第1实施方式同样地通过切割步骤而形成。例如，只要使图6(A)所示的利用第1刀片BL1的局部切割的深度D1为与阻焊剂23的厚度大致相等的深度即可。由此，在维持着芯材21及阻焊剂22的状态下，第1刀片BL1可以切割阻焊剂23。如果以此方式使深度D1变浅，则可以通过切割步骤形成第2实施方式的阶差ST。 
(第3实施方式) 
图12(A)及图12(B)是第3实施方式的半导体装置12的剖视图及后视图。此外，图12(A)是沿图12(B)的A-A线的剖视图。如图12(A)及图12(B)所示，第3实施方式的半导体装置12沿半导体封装体的基板20的背面的外周具有环状的槽90。槽90是通过利用蚀刻法对阻焊剂23进行加工而形成。 
槽90优选设置于距基板20的端10μm～500μm的位置。例如，在槽90的位置距基板20的端小于10μm的情况下，不易使用蚀刻法精度良好地形成槽90。另一方面，如果槽90的位置距基板20的端超过500μm，则槽90与端子25重叠。 
通过在基板20的背面设置着槽90，可以抑制在形成电磁屏蔽40时，电磁屏蔽40的材料折入至背面。例如，在基板20或搬送载具1产生应变的情况下，在基板20的背面与搬送载具1的表面之间形成间隙。进入该间隙的电磁屏蔽40的材料滞留于槽90的空间。因此，电磁屏蔽40的材料被捕捉至槽90的空间，几乎未到达至端子25。由此，可以抑制相互邻接的端子25电短路。 
另一方面，电磁屏蔽40被覆树脂材料30的上表面及侧面，将基板20的背面被覆至槽90的近前。因此，电磁屏蔽40可以更有效地抑制EMI，且可以使阻焊剂23与芯材21的密接性提高。 
此外，半导体芯片60及密封材料30的形态无特别限定。虽未图示，但例如半导体芯片60也可以为具有金属凸块的形态。在此情况下，当切割半导体晶片后，将单片化的半导体芯片60倒装芯片安装于基板20上。接着，于半导体芯片60与基板20间涂布树脂。接着，以密封材料30被覆半导体芯片。之后的步骤可与所述实施方式相同。由此，即便为具有金属凸块的半导体芯片60，也可以获得所述实施方式的效果。 
虽然说明了本发明的几种实施方式，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些实施方式可以通过其他各种方式而实施，可以在不脱离发明的主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化是与包含于发明的范围或主旨同样地，包含于权利要求书中记载的发明及其均等的范围者。 
[符号的说明] 
1       搬送载具 
10      半导体装置 
20      基板 
21      芯材 
22、23  阻焊剂 
25      端子 
30      密封材料 
40      电磁屏蔽 
ST      阶差 
TR      槽。 

Claims (8)

1.一种半导体装置，其特征在于包括：
基板；
半导体芯片，配置于所述基板的第1面上；
密封材料，被覆所述半导体芯片；以及
导电膜，被覆所述密封材料的上表面及侧面；且
在所述基板的与所述第1面相反侧的第2面的外缘设置着阶差、斜面或槽。
2.根据权利要求1所述的半导体装置，其特征在于：所述基板的外缘相比所述密封材料的外缘位于更内侧，所述阶差是通过所述基板与所述密封材料而形成。
3.根据权利要求1所述的半导体装置，其特征在于：所述基板包含被覆所述第2面的绝缘膜；
在所述第2面的外缘去除所述绝缘膜，所述阶差是通过所述绝缘膜与所述基板而形成。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于：所述基板包含被覆所述第2面的绝缘膜；且
所述绝缘膜沿所述基板的所述第2面的外缘具有环状的槽。
5.根据权利要求1至3中任一项所述的半导体装置，其特征在于：所述导电膜是从所述密封材料的上表面向侧面连续设置，在所述的阶差、斜面或槽中间断。
6.一种半导体装置的制造方法，其特征在于包括：
通过以密封材料被覆配置于基板的第1面上的半导体芯片，而在所述基板上形成多个半导体封装体；
从所述基板的与所述第1面为相反侧的第2面对所述基板切入具有第1深度及最大值是第1宽度的切口；
通过以比所述第1宽度窄的第2宽度沿所述切口切断所述密封材料，将所述半导体封装体单片化。
7.根据权利要求6所述的半导体装置的制造方法，其特征在于：在所述半导体封装体的单片化后还包括：
在将所述第2面朝向载具的状态下将多个所述半导体封装体搭载于该载具；且在所述半导体封装体的所述密封材料的上表面及侧面形成导电膜。
8.根据权利要求6或7所述的半导体装置的制造方法，其特征在于：所述切口是使用具有尖细形状的刀片而形成。
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