CN103400825A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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CN103400825A
CN103400825A CN2013103286311A CN201310328631A CN103400825A CN 103400825 A CN103400825 A CN 103400825A CN 2013103286311 A CN2013103286311 A CN 2013103286311A CN 201310328631 A CN201310328631 A CN 201310328631A CN 103400825 A CN103400825 A CN 103400825A
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substrate
lateral surface
ground plane
semiconductor package
package part
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CN103400825B (zh
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杨俊洋
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装件及其制造方法。半导体封装件包括基板、接地层、芯片、封装体及屏蔽层。基板具有外侧面及底面。接地层内埋基板且横向地延伸并从基板的外侧面露出。芯片设于基板上。封装体包覆芯片且具有外侧面。屏蔽层覆盖封装体的外侧面、基板的外侧面及露出的接地层，其中屏蔽层的底面与基板的底面相间隔。

Description

半导体封装件及其制造方法
技术领域
本发明是有关于一种半导体封装件及其制造方法，且特别是有关于一种具有横向延伸的接地层的半导体封装件及其制造方法。
背景技术
受到提升工艺速度及尺寸缩小化的需求，半导体元件变得甚复杂。当工艺速度的提升及小尺寸的效益明显增加时，半导体元件的特性也出现问题。特别是指，较高的工作时脉（clock speed）在信号电平（signal level）之间导致更频繁的转态（transition），因而导致在高频下或短波下的较高强度的电磁放射（electromagneticemission）。电磁放射可以从半导体元件及邻近的半导体元件开始辐射。假如邻近的半导体元件的电磁放射的强度较高，此电磁放射负面地影响半导体元件的运作。若整个电子系统内具有高密度分布的半导体元件，则半导体元件之间的电磁干扰更显严重。
因此，如何降低电磁干扰本技术领域业界努力的重点之一。
发明内容
本发明有关于一种半导体封装件及其制造方法，可降低电磁干扰对半导体封装件的负面影响。
根据本发明一实施例，提出一种半导体封装件。半导体封装件包括一基板、一接地层、一芯片、一封装体及一屏蔽层。基板具有一外侧面及一底面。接地层内埋基板且横向地延伸并从基板的外侧面露出。芯片设于基板上。封装体包覆芯片且具有一外侧面。屏蔽层覆盖封装体的外侧面、基板的外侧面及露出的接地层，其中屏蔽层的底面与基板的底面相间隔。
根据本发明另一实施例，提出一种半导体封装件。半导体封装件包括一基板、一接地层、一接地走线、一芯片、一封装体及一屏蔽层。基板具有一外侧面。接地层形成于基板，接地层横向地延伸且与基板的外侧面相间隔。接地走线形成于基板且从接地层延伸至基板的外侧面而露出于基板的外侧面，其中接地走线的宽度小于接地层的宽度。芯片设于基板上。封装体包覆芯片且具有一外侧面。屏蔽层覆盖封装体的外侧面、基板的外侧面及露出的接地走线。
根据本发明另一实施例，提出一种半导体封装件的制造方法。制造方法包括以下步骤。提供一基板，基板具有一底面且内埋有一横向延伸的接地层；设置一芯片于基板上；形成一封装体包覆芯片；形成一第一切割道经过封装体、基板的一部分及接地层，使封装体及基板各形成一外侧面，其中接地层从基板的外侧面露出；形成一屏蔽层覆盖封装体的外侧面、基板的外侧面及露出的接地层；以及，形成一第二切割道经过基板的其余部分，以切断基板并于屏蔽层形成一底面，其中屏蔽层的底面与基板的底面相间隔。
为让本发明的上述内容能更明显易懂，下文特举实施例，并配合附图，作详细说明如下：
附图说明
图1A绘示依照本发明一实施例的半导体封装件的剖视图。
图1B绘示图1A的俯视图。
图2绘示依照本发明另一实施例的半导体封装件的俯视图。
图3A绘示依照本发明另一实施例的半导体封装件的剖视图。
图3B绘示图3A的俯视图。
图4A绘示依照本发明另一实施例的半导体封装件的剖视图。
图4B绘示图4A的仰视图。
图5，其绘示依照本发明另一实施例的半导体封装件的仰视图。
图6A至6F绘示图1A的半导体封装件的制造过程图。
图7至15绘示本发明上述实施例的半导体封装件的测试结果图。
主要元件符号说明：
100、200、300、400、500：半导体封装件
110：基板
110s1：第一外侧面
110s2：第二外侧面
110b：底面
110u、130u：上表面
120：芯片
125：焊线
130：封装体
130s、160s：外侧面
140：屏蔽层
140b：底面
150：电性接点
151：接地接点
160：接地层
270：接地走线
380：导通孔
W1、W2：宽度
具体实施方式
请参照图1A，其绘示依照本发明一实施例的半导体封装件的剖视图。半导体封装件100包括基板110、芯片120、至少一焊线125、封装体130、屏蔽层140、至少一电性接点150及至少一接地层160。
基板110例如是单层或多层基板，本实施例以多层基板为例说明。基板110具有第一外侧面110s1及第二外侧面110s2。第一外侧面110s1及第二外侧面110s2于二不同切割工艺中形成，因此第二外侧面110s2与第一外侧面110s1横向地错开一距离。本例中，第一外侧面110s1相对第二外侧面110s2内陷。
本例中，由于基板110的第二外侧面110s2、封装体130的外侧面130s与接地层160的外侧面160s于同一切割工艺中形成，因此外侧面110s2、130s与160s大致上对齐，如齐平。
芯片120以其主动面朝上方位设于基板110的上表面110u且通过至少一焊线125电性连接于基板110。另一实施例中，芯片120可以其主动面朝下方位设于基板110的上表面110u且通过至少一焊球电性连接于基板110，此种芯片120称为覆晶（flip chip）。
封装体130覆盖基板110的上表面110u且包覆芯片120及焊线125。封装体130可包括酚醛基树脂（Novolac-based resin）、环氧基树脂（epoxy-based resin）、硅基树脂（silicone-based resin）或其他适当的包覆剂。封装体130亦可包括适当的填充剂，例如是粉状的二氧化硅。可利用数种封装技术形成封装体130，例如是压缩成型（compression molding）、液态封装型（liquid encapsulation）、注射成型（injection molding）或转注成型（transfer molding）。
屏蔽层140覆盖封装体130的上表面130u及外侧面130s、基板110的第二外侧面110s2及从第二外侧面110s2露出的接地层160。由于基板110的第一外侧面110s1相对第二外侧面110s2内陷，使屏蔽层140的底面140b与基板110的底面110b间隔一距离，如此可减少屏蔽层140与电性接点150及外部电路元件（如电路板、芯片或半导体封装件）短路的机率。
屏蔽层140的材料铝、铜、铬、锡、金、银、镍、不锈钢或上述材料的组合所制成，其可应用例如是化学蒸镀（Chemical Vapor Deposition,CVD）、无电镀（electroless plating）、电镀、印刷（printing）、喷布（spraying）、溅镀或真空沉积（vacuum deposition）等技术制成。
屏蔽层140可以是单层或多层材料。例如，屏蔽层140三层结构，其内层不锈钢层、中间层铜层，而外层不锈钢层；或者，屏蔽层140双层结构，其内层铜层，而其外层不锈钢层。
电性接点150例如是焊球、凸块或导电柱，本例以焊球为例说明。电性接点150包含至少一接地接点151，其可电性连接于一外部接地（未绘示），外部接地例如是电路板、芯片或半导体封装件，使接地层160通过接地接点151而接地，进而使屏蔽层140通过接地层160而接地，以保护半导体封装件100内部的电子元件受到电磁干扰。
本实施例中，接地层160内埋于基板110内，即，接地层160设置于基板110第二层的上表面，因此接地层160不从基板110的上表面110u或底面110b露出。另一实施例中，接地层160可设置于基板110其它层的上表面。本实施例的接地层以单层为例说明，然另一实施例中，接地层160的数量可以是多层。接地层160横向地延伸至基板110的第二外侧面110s2而露出于基板110的第二外侧面110s2，使屏蔽层160可接触到露出的接地层160。此外，接地层160的直向厚度t可介于5微米至50微米之间。一实施例中，接地层160可采用电镀形成。
相较于以导电柱电性连接屏蔽层，本实施例的接地层160的尺寸细微，因此不会占据基板110的边缘面积，故可缩小半导体封装件100的面积。
请参照图1B，其绘示图1A的俯视图。本实施例中，接地层160直接延伸至基板110的第二外侧面110s2，而不需通过任何走线。一实施例中，接地层160的横向面积占基板的横向面积的5至50%，使接地层160产生优良的电磁防护效果。此外，本发明实施例不限定接地层160的形状，其可以是圆形、椭圆形、矩形、甚至是不规则形。本发明实施例也不限定接地层160的延伸区域，一实施例中，接地层160可沿基板110的整个第二外侧面110s2延伸，而形成一封闭环形，可提升对电磁干扰的屏蔽效果。
请参照图2，其绘示依照本发明另一实施例的半导体封装件的俯视图。半导体封装件200包括基板110、芯片120、至少一焊线125、封装体130、屏蔽层140、至少一电性接点150（未绘示）、至少一接地层160及至少一接地走线270。
与图1A的半导体封装件100不同的是，本实施例的接地层160与基板110的第二外侧面110s2相隔一距离，接地层160与第二外侧面通过接地走线270直接连接，使接地层160通过接地走线270电性连接于屏蔽层140。亦即，接地层160的外侧面160s与基板110的第二外侧面110s2并未齐平，而是通过至少一接地走线270而连接至屏蔽层140。接地走线270的线径小于接地层160的宽度，因此接地层160与接地走线270的横向面积合占基板110的横向面积的5至75%，使接地层160及接地走线270产生优良的电磁防护效果。
请参照图3A，其绘示依照本发明另一实施例的半导体封装件的剖视图。半导体封装件300包括基板110、芯片120、至少一焊线125、封装体130、屏蔽层140、至少一电性接点150、至少一接地层160、至少一接地走线270及至少一导通孔380。
本例中，基板110、封装体130与接地走线270分别具有外侧面110s、130s与270s，由于整个外侧面110s、130s与270s于同一切割工艺中形成，因此整个外侧面110s、130s与270s大致上对齐，如齐平。
虽然接地层160与基板110的外侧面110s相间隔，然接地走线270延伸至基板110的第二外侧面110s2而与屏蔽层140接触，进而使屏蔽层140通过接地走线270、导电孔380、接地层160与接地接点151而接地。于另一实施例中，接地层160亦可延伸至基板110的外侧面110s而与屏蔽层140接触，但仍同时通过导电孔380、接地走线270与屏蔽层140连接。
如图3A所示，本实施例的接地走线270与接地层160配置基板110的相异二层。例如，接地走线270形成于基板110的上表面110u上，而接地层160内埋于基板110内，接地走线270与接地层160通过至少一导通孔380电性连接。
请参照图3B，其绘示图3A的俯视图。焊线125包括至少一接地焊线125g，接地焊线125g电性连接芯片120与接地走线270，使芯片120可通过接地焊线125g、接地走线270与屏蔽层140而接地。
请参照图4A，其绘示依照本发明另一实施例的半导体封装件的剖视图。半导体封装件400包括基板110、芯片120、至少一焊线125、封装体130、屏蔽层140、至少一电性接点150、至少一接地层160及至少一接地走线270。
本实施例中，电性接点150及接地层160接垫，其形成于基板110的底面110b上，使半导体封装件400成为一平面栅格阵列（land grid array,LGA）封装件。接地层160形成于基板110且横向地延伸，并与基板110的外侧面110s相间隔，亦即接地层160的外侧面160s并未露出于基板110的外侧面110s。接地走线270形成于基板110且从接地层160延伸至基板110的外侧面110s而露出于基板110的外侧面110s，使屏蔽层140电性接触露出的接地走线270而接地。本例中，接地层160的数量多层，其分别形成于基板110的底面110b及基板110的内部。另一例中，至少一接地层160可形成于基板110的底面110b、基板110的上表面110u与基板110内部的至少一者，本发明实施例并不限定接地层160的层数及形成位置。
请参照图4B，其绘示图4A的仰视图。接地走线270的宽度W1小于接地层160的宽度W2。当接地走线270的宽度W1愈细，接地品质会愈差，但愈节省材料；当接地走线270的宽度W1愈宽，接地品质会愈佳，但愈浪费材料。一实施例中，宽度W1与宽度W2的比值介于5%与120%之间，可兼顾接地品质及容许的材料用量。然若要达到更佳的接地品质，接地走线270的宽度W1也可以大于接地层160的宽度W2。
请参照图5，其绘示依照本发明另一实施例的半导体封装件的仰视图。半导体封装件500包括基板110、芯片120（未绘示）、至少一焊线125（未绘示）、封装体130、屏蔽层140、至少一电性接点150及至少一接地层160。
如图5所示，本实施例的接地层160直接延伸至基板110的外侧面110s，使接地层160的延伸面积增大。由于接地层160直接延伸至基板110的外侧面110s，故本实施例可省略接地走线270。
请参照图6A至6F，其绘示图1A的半导体封装件的制造过程图。
如图6A所示，提供基板110，其中基板110上设有芯片120，芯片120通过至少一焊线125电性连接基板110。基板110内埋有横向延伸的接地层160，以对芯片120产生电磁干扰防护作用。
如图6B所示，形成封装体130覆盖基板110的上表面110u并包覆芯片120及焊线125。
如图6C所示，可采用例如是激光或刀具，形成至少一第一切割道P1经过封装体130、基板110的一部分及接地层160，使封装体130、基板110与接地层160分别形成外侧面130s、第二外侧面110s2与外侧面160s，其中接地层160的外侧面160s从基板110的第二外侧面110s2露出。由于外侧面130s、第二外侧面110s2与外侧面160s于同一切割工艺中形成，故外侧面130s、第二外侧面110s2与外侧面160s大致上对齐，如齐平。
如图6D所示，可采用例如是化学气相沉积、无电镀法、电解电镀、印刷、旋涂、喷涂、溅镀或真空沉积法，形成屏蔽层140覆盖封装体130的外侧面130s及上表面130u、基板110的第二外侧面110s2及露出的接地层160的外侧面160s。
如图6E所示，形成至少一焊球150于基板110的底面110b。
如图6F所示，可采用例如是刀具或激光，从基板110的底面110b形成至少一第二切割道P2经过基板110的其余部分，以切断基板110。这样的切割方式称为半穿切（half-cut）。切割后，基板110形成第一外侧面110s1。由于第二切割道P2的宽度W2大于第一切割道P1的宽度W1，故第一外侧面110s1相对第二外侧面110s2内陷。切割后，屏蔽层140形成底面140b，其中屏蔽层140的底面140b与基板110的底面110b相间隔，亦即，屏蔽层140的底面140b与基板110的底面110b沿基板110的厚度方向具有一距离。此外，在形成第二切割道P2之前，可先倒置基板110与封装体130，使基板110朝向刀具或激光，以便于切割。
图2的半导体封装件200的制造方法相似于半导体封装件100，容此不再赘述。图3A的半导体封装件300的制造方法与半导体封装件100的制造方法差异的处在于，半导体封装件300的制造方法可省略第二切割道P2的形成，且第一切割道P1经过整个封装体130与整个基板110，以完全切断封装体130与基板110。半导体封装件400及500的制造方法则相似于半导体封装件300，容此不再赘述。
请参照图7至15，其绘示本发明上述实施例的半导体封装件的测试结果图。图7至图9绘示数层接地层160同时形成于基板110内部及底面110b的电磁干扰防护测试图，其中图7的基板110的线路密度较高，图8次之，而图9的基板110的线路密度较低。图10至图12绘示接地层160只形成于基板110内部的电磁干扰防护测试图，其中图10的基板110的线路密度较高，图11次之，而图12的基板110的线路密度较低。图13至图15绘示接地层160只形成于基板110的底面110b的电磁干扰防护测试图，其中图13的基板110的线路密度较高，图14次之，而图15的基板110的线路密度较低。其中，横轴为操作频率（frequency）单位为兆赫兹（GHz），纵轴则为电磁干扰防护效果，单位为分贝（dB）。
由上述测试图可知，接地层160同时形成于基板110内部及底面110b的电磁干扰防护效果近似于接地层160只形成于基板110的底面110b的电磁干扰防护效果。此外，相较于接地层160只形成于基板110内部的电磁干扰防护效果，接地层160同时形成于基板110内部及底面110b的电磁干扰防护效果以及接地层160只形成于基板110的底面110b的电磁干扰防护效果都较优良。
综上所述，虽然本发明已以实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (18)

1.一种半导体封装件，包括：
一基板，具有一外侧面及一底面；
一接地层，内埋该基板且横向地延伸，并从该基板的该外侧面露出；
一芯片，设于该基板上；
一封装体，包覆该芯片且具有一外侧面；以及
一屏蔽层，覆盖该封装体的该外侧面、该基板的该外侧面及露出的该接地层，其中该屏蔽层的底面与该基板的该底面相间隔。
2.如权利要求1所述的半导体封装件，其特征在于，该接地层直接延伸至该基板的该外侧面。
3.如权利要求1所述的半导体封装件，其特征在于，该接地层与该基板的该外侧面相间隔，该半导体封装件更包括：
一接地走线，从该接地层延伸至该基板的该外侧面。
4.如权利要求1所述的半导体封装件，其特征在于，该接地层与该基板的该外侧面相间隔，该半导体封装件更包括：
一接地走线，延伸至该基板的该外侧面，且与该接地层配置于该基板的相异二层；以及
一导通孔，形成于该接地走线与该接地层之间，以电性连接该接地走线与该接地层。
5.如权利要求1所述的半导体封装件，其特征在于，包括：
数个该接地层，内埋于该基板。
6.如权利要求1所述的半导体封装件，其特征在于，该接地层的横向面积占该基板的横向面积的5%至50%。
7.如权利要求1所述的半导体封装件，其特征在于，该接地层的直向厚度介于5微米至50微米之间。
8.一种半导体封装件，包括：
一基板，具有一外侧面；
一接地层，形成于该基板，该接地层横向地延伸，且与该基板的该外侧面相间隔；
一接地走线，形成于该基板，且从该接地层延伸至该基板的该外侧面而露出于该基板的该外侧面，其中该接地走线的宽度小于该接地层的宽度；
一芯片，设于该基板上；
一封装体，包覆该芯片且具有一外侧面；以及
一屏蔽层，覆盖该封装体的该外侧面、该基板的该外侧面及露出的该接地走线。
9.如权利要求8所述的半导体封装件，其特征在于，该基板具有一底面，该接地层形成于该基板的该底面。
10.如权利要求8所述的半导体封装件，其特征在于，该接地层内埋于该基板内。
11.如权利要求8所述的半导体封装件，其特征在于，该接地走线具有一外侧面从该基板的该外侧面露出，该封装体的该外侧面、该基板的该外侧面与该接地走线的该外侧面对齐。
12.如权利要求8所述的半导体封装件，其特征在于，包括：
数个该接地层，形成于该基板；以及
数个该接地走线，各该接地走线从对应的该接地层延伸至该基板的该外侧面。
13.如权利要求8所述的半导体封装件，其特征在于，该接地层与该接地走线的横向面积的合占该基板的横向面积的5%至50%。
14.如权利要求8所述的半导体封装件，其特征在于，该接地层的直向厚度与该接地走线的直向厚度各介于5微米至50微米之间。
15.如权利要求8所述的半导体封装件，其特征在于，该接地层具有一从该基板的该外侧面露出的外侧面，该封装体的该外侧面、该基板的该外侧面与该接地层的该外侧面对齐。
16.一种半导体封装件的制造方法，包括：
提供一基板，该基板具有一底面且内埋有一横向延伸的接地层；
设置一芯片于该基板上；
形成一封装体包覆该芯片；
形成一第一切割道经过该封装体、该基板的一部分及该接地层，使该封装体及该基板各形成一外侧面，其中该接地层从该基板的该外侧面露出；
形成一屏蔽层覆盖该封装体的该外侧面、该基板的该外侧面及露出的该接地层；以及
形成一第二切割道经过该基板的其余部分，以切断该基板并于该屏蔽层形成一底面，其中该屏蔽层的该底面与该基板的该底面相间隔。
17.如权利要求16所述的制造方法，其特征在于，该第二切割道的宽度大于该第一切割道的宽度。
18.一种半导体封装件的制造方法，包括：
提供一基板，一接地层形成于该基板，该接地层横向地延伸，且一接地走线形成于该基板，其中该接地走线的宽度小于该接地层的宽度；
设置一芯片该基板上；
形成一封装体包覆该芯片；
形成一切割道经过该封装体、该基板及该接地走线，使该封装体及该基板各形成一外侧面，其中该接地层与该基板的该外侧面相间隔而该接地走线从该基板的该外侧面露出；以及
形成一屏蔽层覆盖该封装体的该外侧面、该基板的该外侧面及露出的该接地走线。
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