CN106935571A - 具有电磁干扰屏蔽的电子封装体及相关联方法 - Google Patents

具有电磁干扰屏蔽的电子封装体及相关联方法 Download PDF

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CN106935571A
CN106935571A CN201610195207.8A CN201610195207A CN106935571A CN 106935571 A CN106935571 A CN 106935571A CN 201610195207 A CN201610195207 A CN 201610195207A CN 106935571 A CN106935571 A CN 106935571A
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conductive
substrate
electronic packing
conductive region
packing body
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G·迪玛尤加
F·阿雷拉诺
M·塔比拉
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STMicroelectronics Inc Philippines
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Abstract

一种电子封装体包括具有相反的第一表面和第二表面的衬底。多个导电区域在该衬底的该第一表面上并且包括至少一个边缘导电区域。多个导电凸块在该衬底的该第二表面上并且耦接于这些导电区域中的多个对应导电区域。集成电路(IC)由该衬底所承载。多条键合接线耦接在该IC与这些导电区域中的多个对应导电区域之间。包封材料在该IC以及该衬底的多个相邻部分之上。导电层在该包封材料上，并且至少一个导电体耦接在该至少一个边缘导电区域与该导电层之间。

Description

具有电磁干扰屏蔽的电子封装体及相关联方法
技术领域
本披露涉及电子封装体，并且更具体地，本披露涉及一种在包封材料上具有导电层以用于电磁干扰(EMI)屏蔽的电子封装体。
背景技术
电子器件通常使用电磁干扰(EMI)屏蔽来防止由操作环境中所存在的电磁场引起的对它们性能的破坏。一些电子器件包含围绕电子器件以形成电磁屏蔽的金属容器或“罐”，该金属容器或“罐”电性地连接至器件中的地线。这种屏蔽在EMI场到达器件之前对其进行衰减。其他EMI隔离系统使用配合于板装电子器件之上的金属板。包括集成电路(IC)的封装电子器件(如球栅阵列(BGA)电子封装体)可以包括在封装体上通过溅射或化学汽相沉积(CVD)而沉积的金属膜。这个金属膜电性地连接至接地导体层，如在IC下面延伸至封装体的壁以将IC与电磁干扰隔离开来。
在另一个示例中，具有悬浮在流体载体中的金属颗粒的导电涂料被喷射到电子封装体(例如，球栅阵列封装体)的外部表面上。所喷射的导电涂料被固化以去除流体载体，留下金属膜涂覆到电子封装体的外部。多个沟槽被切入到表面中(如在包封材料中)，以便将导电涂料暴露于位于接地导体层处的接地导体电路。这个系统可能需要封装体中的延伸至封装体周边的接地导体层。针对电子封装体的其他EMI屏蔽系统使用从IC到封装体上的屏蔽层的接线键合。这些技术可能增加制造复杂性并提高成本。
发明内容
一种电子封装体包括具有相反的第一表面和第二表面的衬底。多个导电区域在该衬底的该第一表面上。该多个导电区域可以包括在该衬底的边缘处的至少一个边缘导电区域。多个导电凸块在该衬底的该第二表面上并且耦接于该多个导电区域中的多个对应导电区域。集成电路(IC)由该衬底所承载。多条键合接线耦接在该IC与该多个导电区域中的多个对应导电区域之间。包封材料在该IC以及该衬底的多个相邻部分之上。导电层在该包封材料上，并且至少一个导电体可以耦接在该至少一个边缘导电区域与该导电层之间。
至少一个边缘导电区域可以包括在衬底上的接地迹线。电子封装体可以包括球栅阵列电子封装体。在包封材料上的导电层可以包括导电涂料。在包封材料上的导电层可以包括银涂层。银涂层可以具有从5微米到15微米的厚度。该至少一个导电体可以包括球形键合，并且在一个示例中包括多个球形键合。导电层可以具有不大于5欧姆每平方的电阻。
一种形成电子封装体的方法可以包括：在衬底的第一表面上形成多个导电区域。该多个导电区域可以包括在该衬底的边缘处的至少一个边缘导电区域。该方法包括：在该至少一个边缘导电区域上形成至少一个导电体并且形成多个导电凸块，该多个导电凸块在该衬底的该第二表面上并且耦接至多个导电区域中的多个对应导电区域。该方法进一步包括：将多条键合接线耦接在由该衬底所承载的集成电路(IC)与该多个导电区域中的多个对应导电区域之间。该方法包括：在IC以及衬底的多个相邻部分之上形成包封材料，并且在包封材料上形成导电层，该导电层通过该至少一个导电体耦接到该至少一个边缘导电区域。
附图说明
其它特征和优势将从下面结合附图给出的详细描述中变得显而易见，在附图中：
图1是电子封装体的截面图，示出了根据非限制性示例的耦接在至少一个边缘导电区域与导电层之间的导电体。
图2是高级流程图，示出了根据非限制性示例的一种形成电子封装体的方法。
图3是截面图，示出了根据非限制性示例在制造电子封装体过程中将IC附接到衬底。
图4是截面图，示出了根据非限制性示例将至少一个导电体作为球形键合进行附接。
图5是截面图，示出了根据非限制性示例在IC与多个导电区域的多个对应导电区域之间的接线键合。
图6是截面图，示出了根据非限制性示例在IC和衬底之上的包封材料的模制。
图7是截面图，示出了根据非限制性示例附接在衬底的第二表面上的导电凸块。
图8是截面图，示出了根据非限制性示例将胶带安装在导电凸块之上以便用于与拾放设备一起使用。
图9是截面图，示出了根据非限制性示例在包封材料中制作的用于将导电体的一部分暴露为球形键合的锯槽。
图10是截面图，示出了根据非限制性示例被喷射到包封材料上并且被喷射到锯槽中的导电层。
图11是截面图，示出了根据非限制性示例用于将电子封装体单片化的最终切割。
具体实施方式
现在将在下面参照附图更充分地描述不同实施例，在附图中示出了优选实施例。可以对许多不同的形式进行阐述，并且所描述的实施例不应被解释为被限制到在此所阐述的实施例。而且，提供这些实施例使得本公开内容将是透彻和完整的，并且这些实施例将向本领域技术人员充分传递范围。
在图1中总体上以10示出了一种示例电子封装体。如所展示的，电子封装体10被形成为球栅阵列电子封装体。可以使用其他封装体设计，包括平面栅格阵列、双列直插封装体(DIP)、四列扁平封装体(QFP)或倒装芯片。如本领域众所周知的，电子封装体10包括具有第一表面12a和第二表面12b的电介质衬底12并且包括一个或多个导电层、导孔或有涂层的过孔以用于互连。金属化层14由衬底12承载在该衬底的第一表面12a上并且包括裸片附接层16，在该裸片附接层上作为裸片的集成电路(IC)18由衬底承载。多个导电区域20在衬底12的第一表面12a上，并且在一个示例中被形成为接线键合区域。这些导电区域20包括在衬底12的边缘处的至少一个边缘导电区域22并且在此示例中被形成为接地迹线。多个导电凸块24被形成为在衬底12的第二表面12b上的焊球并且使用不同的导电层、导孔、导电过孔或对本领域技术人员已知的其他技术耦接至该多个导电区域20的对应导电区域。多条键合接线26耦接于IC 18与多个导电区域20中的对应导电区域以及边缘导电区域22之间。包封材料28在IC 18以及衬底12的多个相邻部分之上形成。如本领域技术人员已知的，不同的材料可用于包封材料28。
如所展示的，在包封材料28上形成导电层30。至少一个导电体32耦接在该至少一个边缘导电区域22与导电层30之间。在所展示的这个实施例中，该至少一个导电体32形成为球形键合，并且如所示的，多个球形键合与在图1中所展示的两个球形键合一起使用。球形键合32被定位在边缘导电区域22之上在半导体封装体10的边缘处，并且通过切割进入包封材料28且部分地进入球形键合而被暴露。然后，球形键合32的暴露部分被导电层30所涂覆。如以下更详细地解释的，可以通过使用接线键合技术形成球形键合32，在这些接线键合技术中，使用热量在边缘导电区域22上形成球形键合并且接线随后被去除以使球形键合完整无缺。还可以使用现有技术通过焊球布置形成导电体32。
包封材料28上的导电层30可以由不同的材料形成并且具有不同的厚度以屏蔽IC18免遭EMI或者防止EMI从封装体中辐射出来。在一个示例中，导电层30是具有从5微米到15微米厚度的银涂层。还有可能使用被喷射到包封材料28上的导电涂料。导电涂料可以包括悬浮在流体载体中的金属颗粒，该流体载体随后被干燥。导电涂料可以包括不同的金属颗粒，包括但不限于铜、银、不锈钢、镍、以及其他用于实现EMI屏蔽效果的导电颗粒。在一个示例中，此导电层30具有不大于5欧姆每平方的电阻，但是可以根据电子封装体10的设计和性能要求而发生变化。作为球形键合的导电体32被连接在电子封装体10的边缘处的衬底12的边缘导电区域22处，并且通过在封装体包封之后进行切割而被暴露并且通过在切割之后通常被喷射到包封材料28上的银或其他导电涂层而被短路至导电层30。
在图2中以50示出了一种示例制造方法。该过程在框52处开始。在衬底12的第一表面12a上形成多个导电区域20，包括作为接地迹线的至少一个边缘导电区域22(框54)。在示例中，在边缘导电区域22处的接地迹线上形成作为球形键合32的至少一个导电体(框56)。
将多条键合接线耦接于由衬底12承载的IC 18与这些导电区域20的对应导电区域之间(框58)。在IC 18以及衬底12的多个相邻部分之上形成包封材料28(框60)。在示例中，如本领域技术人员已知的，作为焊球的多个导电凸块24形成于衬底12的第二表面12b上并且如通过在衬底12中形成的导电层、互连和有涂层的过孔而耦接至多个导电区域20的对应导电区域(框62)。
对包封材料进行切割以暴露球形键合，并且将导电层30形成在包封材料28和至少一个导电体32上。因此，球形键合32耦接于至少一个边缘导电区域22与导电层30之间，接着通过进行切割从而使得这些封装体被分隔开或者“被单片化”(框64)。该过程在框66处结束。
图3至图11示出了根据非限制性示例针对电子封装体10的制造步骤的序列。在衬底12上展示了作为裸片1和裸片2的两个IC。应理解的是，如以下所解释的，其他数量的IC18可以被附接到单个较大的衬底12上，该衬底随后被切割或“被单片化”成多个单独的电子封装体10。
图3示出了具有两个IC的衬底12，这两个IC作为由裸片附接层16上的衬底承载的裸片1和裸片2，该裸片附接层被施加于金属层14之上。还展示了导电区域20和边缘导电区域22。如以下进一步描述的，在切割和单片化成单独的电子封装体之后，靠近边缘导电区域22的这个区域变成电子封装体10的衬底12的边缘。作为球形键合32的导电体被定位在边缘导电区域22上(图4)。如前所述，作为球形键合32的多个导电本体可以如通过接线键合技术以及随后去除接线而形成，或者通过在边缘导电区域22上放置焊料凸块或焊球而形成。在图4和随后附图的示例中，在每个边缘导电区域22上仅示出一个球形键合32。应该理解的是，可以使用在图1中示出的多个(例如，两个或更多个)球形键合。图1示出了电子封装体10，该电子封装体具有两个彼此堆叠的球形键合32以给出更大的覆盖表面区域从而接合用于EMI屏蔽的导电层30。
图5示出了接线键合工艺，其中，多条键合接线26耦接在该IC 18与该多个导电区域20的多个对应导电区域之间。在这之后，通过在IC 18之上施加包封材料28而进行模制以覆盖所有键合接线26、IC 18以及作为导电本体32的球形键合(图6)。如本领域技术人员已知的，导电凸块24在衬底12的第二表面12b上形成(图7)，并且使用多个导电层、导孔、和/或有涂层的过孔被耦接至该多个导电区域20的多个对应导电区域。如本领域技术人员已知的，可以使用不同的技术将导电凸块24附接于衬底10，如应用焊球或其他导电凸块。
如本领域技术人员已知的，胶带80被安装在衬底12的第二表面12b处安装到导电凸块24上，并且用作用于稍后的经切割和单片化的单独电子封装体10的承载介质，其中，使用拾放机械装置或者使用类似的制造技术将这些单片化单独电子封装体附接于电路板或者其他衬底上。在这之后，用机械锯进行预切割(图9)，以便在对应于每个封装体10的未来侧边缘的两个IC 18之间形成锯槽82。在一些示例中，该锯槽82在宽度和深度上通常小于约200微米并且在宽度和深度上范围从50微米到100微米，但是部分地延伸穿过如所展示的作为球形键合32的每个导电体。如通过在包封材料上喷射一层银而在包封材料28上形成导电层30(图10)。该银延伸进入在球形键合32的暴露部分之上的锯槽82中。通过切穿衬底12的其余部分而对每个电子封装体10进行切割和单片化，例如，通过使用更加精确并且将不会损坏导电层30的激光。胶带80保持完整以便与拾放设备或其他电子封装机械装置一起使用(图11)。
所描述的此工艺提供了一种用于对电子封装体10(如球栅阵列电子封装体)应用EMI屏蔽的高效技术。该技术将在可以破坏性能的恶劣操作环境中屏蔽IC 18免遭电磁场。在一个示例中，该工艺是廉价的并且在边缘导电区域22上使用作为球形键合32的导电体的布置，该边缘导电区域具有经修改的衬底12以接受在衬底的边缘导电区域处的包封材料28的那些区域处的球形键合。该工艺在IC之上不使用“EMI”罐或其他金属层，也不需要在任何包封材料中切割多个沟槽以暴露如位于衬底的底部上或被模制到封装体的引线。可能需要对衬底12进行微小的修改，如将接地迹线22延伸至将要被切割的衬底12的这些区域中，从而暴露任何附接的球形键合32。这是针对衬底12的相对微小的修改。
本发明的许多修改和其他实施例对于受益于前面的描述和相关附图中呈现的教导的本领域技术人员来说将是显而易见的。因此，应当理解本发明不限于所披露的具体实施例，并且那些修改及实施例旨在被包括于所附权利要求书的范围内。

Claims (21)

1.一种电子封装体，包括：
衬底，所述衬底具有相反的第一表面和第二表面；
在所述衬底的所述第一表面上的多个导电区域，所述多个导电区域包括在所述衬底的边缘处的至少一个边缘导电区域；
多个导电凸块，所述多个导电凸块在所述衬底的所述第二表面上并且耦接至所述多个导电区域中的多个对应导电区域；
由所述衬底承载的集成电路(IC)；
多条键合接线，所述多条键合接线耦接在所述IC与所述多个导电区域中的多个对应区域之间；
在所述IC以及所述衬底的多个相邻部分之上的包封材料；
在所述包封材料上的导电层；以及
耦接在所述至少一个边缘导电区域与所述导电层之间的至少一个导电体。
2.根据权利要求1所述的电子封装体，其中，所述至少一个边缘导电区域包括接地迹线。
3.根据权利要求1所述的电子封装体，其中，所述导电层包括导电涂料。
4.根据权利要求1所述的电子封装体，其中，所述导电层包括银层。
5.根据权利要求4所述的电子封装体，其中，所述银层具有5微米到15微米之间的厚度。
6.根据权利要求1所述的电子封装体，其中，所述至少一个导电体包括球形键合。
7.根据权利要求1所述的电子封装体，其中，所述至少一个导电体包括多个球形键合。
8.根据权利要求1所述的电子封装体，其中，所述导电层具有不大于5欧姆每平方的电阻。
9.一种电子封装体，包括：
衬底，所述衬底具有相反的第一表面和第二表面；
在所述衬底的所述第一表面上的多个导电区域，所述多个导电区域包括在所述衬底的边缘处的至少一条接地迹线；
多个导电凸块，所述多个导电凸块在所述衬底的所述第二表面上并且耦接至所述多个导电区域中的多个对应导电区域；
由所述衬底承载的集成电路(IC)；
多条键合接线，所述多条键合接线耦接在所述IC与所述多个导电区域中的多个对应区域之间；
在所述IC以及所述衬底的多个相邻部分之上的包封材料；
在所述包封材料上的导电层；以及
耦接在所述至少一条接地迹线与所述导电层之间的至少一个球形键合。
10.根据权利要求9所述的电子封装体，其中，所述导电层包括导电涂料。
11.根据权利要求9所述的电子封装体，其中，所述导电层包括银层。
12.根据权利要求11所述的电子封装体，其中，所述银层具有5微米到15微米之间的厚度。
13.根据权利要求9所述的电子封装体，其中，所述至少一个球形键合包括多个球形键合。
14.根据权利要求9所述的电子封装体，其中，所述导电层具有不大于5欧姆每平方的电阻。
15.一种形成电子封装体的方法，所述方法包括：
在衬底的第一表面上形成多个导电区域，所述多个导电区域包括在所述衬底的边缘处的至少一个边缘导电区域；
在所述至少一个边缘导电区域上形成至少一个导电体；
形成多个导电凸块，所述多个导电凸块在所述衬底的所述第二表面上并且耦接于所述多个导电区域中的多个对应导电区域；
将多条键合接线耦接在由所述衬底承载的集成电路(IC)与所述多个导电区域中的多个对应区域之间；
在所述IC以及所述衬底的多个相邻部分之上形成包封材料；并且
在所述包封材料上形成导电层，所述导电层通过所述至少一个导电体耦接至所述至少一个边缘导电区域。
16.根据权利要求15所述的方法，其中，所述至少一个边缘导电区域包括接地迹线。
17.根据权利要求15所述的方法，其中，形成所述导电层包括施加导电涂料。
18.根据权利要求15所述的方法，其中，在所述包封材料上形成所述导电层包括施加银层。
19.根据权利要求18所述的方法，其中，所述银层具有5微米到15微米之间的厚度。
20.根据权利要求15所述的方法，其中，形成所述至少一个导电体包括形成至少一个球形键合。
21.根据权利要求15所述的方法，其中，所述导电层具有不大于5欧姆每平方的电阻。
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