CN108305868A - 具有电磁干扰屏蔽的半导体封装及其制造方法 - Google Patents

具有电磁干扰屏蔽的半导体封装及其制造方法 Download PDF

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CN108305868A
CN108305868A CN201810003422.2A CN201810003422A CN108305868A CN 108305868 A CN108305868 A CN 108305868A CN 201810003422 A CN201810003422 A CN 201810003422A CN 108305868 A CN108305868 A CN 108305868A
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electromagnetic interference
encapsulant
semiconductor
semiconductor packages
opening
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CN108305868B (zh
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新督尚
李泰勇
李琼延
金宋珠
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Imark Technology Co
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Imark Technology Co
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Abstract

具有电磁干扰屏蔽的半导体装置及其制造方法。一种半导体封装包含：一个或多个半导体装置；电磁干扰屏蔽，在所述半导体封装的所有外表面上；以及开口，在所述开口中放置有电性互连以形成与衬垫的电性接触。在一个实施例中，所述半导体装置包含在所述半导体装置的所有六个表面上的电磁干扰屏蔽而没有使用分离的电磁干扰盖。

Description

具有电磁干扰屏蔽的半导体封装及其制造方法
技术领域
本发明的某些实施例关于具有电磁干扰(EMI)屏蔽的半导体封装及其制造方法。
背景技术
半导体封装可发射电磁干扰，其可能干扰其他半导体封装的操作。因此，各种半导体封装可包含电磁干扰屏蔽以助于减少电磁干扰被发射并且阻隔来自其他来源的电磁干扰。
通过将熟知和传统方法的系统与本文其余参考附图所阐述的本发明揭露内容的一些态样进行比较，熟知和传统方法的进一步限制和缺点将对所属技术领域中具有通常知识者而言变得显而易见。
发明内容
本发明提供一种具有电磁干扰屏蔽的半导体封装及其制造方法。
本发明的一态样是一种半导体封装，其包含：一个或多个半导体装置；电磁干扰屏蔽，在所述半导体封装的所有外表面上；以及开口，在所述开口中放置有电性互连以形成与衬垫的电性接触。
所述半导体封装可包含内部电磁干扰屏蔽，其在所述一个或多个半导体晶粒中的两个半导体晶粒之间。
在所述半导体封装中，所述电性互连是电性地连接至所述电磁干扰屏蔽。
在所述半导体封装中，所述电性互连是电性地连接至所述半导体封装的接地迹线。
在所述半导体封装中，所述电性互连是焊球。
在所述半导体封装中，所述开口是形成在所述电磁干扰屏蔽的一部分之中并且在所述半导体封装的底部上的囊封物之中。
在所述半导体封装中，所述开口包含没有被所述电性互连所占据的空间的体积，并且所述空间的体积是实质上被回填以形成与所述囊封物的底部实质上共平面的底部表面。
本发明的另一态样是一种用于屏蔽半导体装置的方法，所述方法包含：对于包含顶部囊封物和底部囊封物的所述半导体装置，附接第一载体到所述底部囊封物的底部表面；在没有被所述第一载体覆盖的所述半导体装置的所有外表面上形成外部电磁干扰屏蔽；附接第二载体到所述顶部囊封物的顶部表面；从所述半导体装置的所述底部囊封物移除所述第一载体；以及形成外部底部电磁干扰屏蔽于所述底部囊封物的底部表面上。
所述方法包含附接电性互连至所述半导体装置。
在所述方法中，所述电性互连被电性地连接至所述外部电磁干扰屏蔽以及所述外部底部电磁干扰屏蔽。
所述方法包含形成开口，所述开口穿透所述外部底部电磁干扰屏蔽并且穿透所述底部囊封物以暴露衬垫，并且其中前述附接所述电性互连包含经由所述开口而附接所述电性互连至所述衬垫。
在所述方法中，前述形成所述开口包含使用镭射以形成所述开口。
在所述方法中，前述形成所述开口包含：形成第一凹陷；以及形成第二凹陷，其中所述第二凹陷是窄于所述第一凹陷并且暴露所述衬垫。
所述方法包含在前述附接所述电性互连至所述衬垫之后回填所述开口。
在所述方法中，前述形成所述外部电磁干扰屏蔽包含使用溅镀以形成所述外部电磁干扰屏蔽的至少一部分；并且前述形成所述外部底部电磁干扰屏蔽包含使用溅镀以形成所述外部底部电磁干扰屏蔽的至少一部分。
所述方法包含移除所述顶部囊封物的一部分以形成在两个半导体晶粒之间的空间。
所述方法包含形成内部电磁干扰屏蔽在两个半导体晶粒之间的所述空间中。
在所述方法中，前述形成所述内部电磁干扰屏蔽包含使用溅镀以形成所述内部电磁干扰屏蔽。
在所述方法中，所述内部电磁干扰屏蔽被电性地连接至所述外部电磁干扰屏蔽和所述外部底部电磁干扰屏蔽。
本发明的又一态样是一种半导体封装，其包括：半导体装置；顶部囊封物和底部囊封物，其中所述顶部囊封物囊封至少两个所述半导体装置；电磁干扰屏蔽，在所述半导体封装的所有外表面上；内部电磁干扰屏蔽，在所述至少两个所述半导体装置之间；以及电性互连，通过衬垫而电性地连接至所述半导体装置中的至少一者，其中所述衬垫是位在所述底部囊封物中。
根据下文对较佳实施例的描述，本揭示的上述和其他目的将被描述或变得显而易见。
附图说明
图1是可能会互相干扰的多个装置的示意图。
图2是图示根据本揭示的范例性实施例的半导体封装的横截面视图。
图3-9是图示根据本揭示的范例性实施例屏蔽半导体装置的各个阶段的横截面视图。
图10是根据本揭示的范例性实施例用于屏蔽半导体装置的流程图的范例。
图11是图示根据本揭示的范例性实施例的半导体封装的横截面视图。。
具体实施方式
以下配合图式及本发明的较佳实施例，进一步阐述本发明为达成预定发明目的所采取的技术手段。
本揭示的各种范例性实施例将参照随附图式而被详细地描述，使得所属技术领域中具有通常知识者可以制造并使用这些实施例。
本揭示的各个态样可以以许多不同的形式来实施，并且不应该被解释为局限于在本阐述的范例性实施例中。而是，提供本揭示的这些范例性实施例，使得本揭示是彻底且完整的，并将向所属技术领域中具有通常知识者传达本揭示的各个态样。
这里所使用的术语仅仅是为了描述特定实施例的目的，并不意图限制本揭示。在图式中，为了清楚起见，层和区域的厚度可能被夸大。相同的元件符号始终代表相同的元件。
如本文所使用的，“及/或”表示通过“及/或”连接的列表中的任何一个或多个项目。作为范例，“x及/或y”表示三元素集合{(x)，(y)，(x，y)}中的任何元素。换句话说，“x及/或y”表示“x和y中的一个或两个”。作为另一个例子，“x、y及/或z”表示七元素集合{(x)，(y)，(z)，(x，y)，(x，z)，(y，z)，(x，y，z)}。换句话说，“x、y及/或z”表示“x、y和z中的一个或多个”。如本文所使用的，用语“示例性”代表是非限制性的范例、例子或例证。如本文所使用的，用语“例如”和“举例而言”列出一个或多个非限制性的范例、例子或例证。
再者，单数形式也意图包括复数形式，除非上下文另有明确指出。进一步理解，在本说明书中使用的用语“包括”、“包含”、“包括有”以及“包含有”指定存在所描述的特征、数量、步骤、操作、元件及/或组件，但不排除存在或添加一个或多个其他特征、数量、步骤、操作、元件、组件及/或其群组。
再者，将可以理解的是当元件A被称为“连接到(或耦合到)”元件B，则所述元件A可以直接连接到(或耦合到)所述元件B，或者是中间元件C可出现在所述元件A和B之间，使得所述元件A间接连接到所述元件B。
又，虽然可使用术语第一、第二等来描述各种部件、元件、区域、层和/或区段，但是这些部件、元件、区域、层和/或区段不应受这些术语所限制。这些术语仅用于将一个部件、元件、区域、层和/或区段与另一者区分开。因此，举例而言，在不脱离本揭示的教示的情况下，下面讨论的第一部件、第一元件、第一区域、第一层和/或第一区段可被称为第二部件、第二元件、第二区域、第二层和/或第二区段。
类似地，诸如“上部”、“下部”、“侧边”和类似者的空间相关术语会在本文中使用，以利于描述所附图式中的一元件或特征与另一元件或特征的关系。将理解的是，空间相关术语旨在包括除了所附图示中所绘的指向之外的使用或操作中的装置的不同取向。举例而言，如果所述装置在图式中被上下翻转，被描述为在其他元件或是特征“之下”或“下面”的元件将被定向为在所述其他元件或是特征“之上”。因此，范例性术语“在…之下”可以涵盖上方和下方两种方向。
为了便于参考，根据本揭示的实施例的所有侧面都被屏蔽的半导体装置可被称为半导体封装。然而，使用此用语“半导体封装”并不以任何方式限制本揭示的各种实施例。
为了使描述/解释更清楚，图式和描述可以省略半导体装置/封装的一些部分。因此，应当理解的是，本揭示的各种实施例可以包括不在本文描述的特定的部分(例如，通孔、一个或多个电连接层、一个或多个介电层/钝化/绝缘层、底部填充物…等等)。
图1是各种装置的示意图，这些装置可能彼此互相干扰。参照图1，智能手机100和笔记型电脑102。在一般的操作之下，所述智能手机100和所述笔记型电脑102可彼此无线地通信。然而，这些装置的每一个也可能发射对于其他装置是没有帮助的电子信号(杂讯)。在某些情况之下，所述杂讯可能足够强而干扰到其他装置的操作。某些物件可能也想要减少装置所发射出的电子信号以用于安全性目的。举例来说，笔记型电脑所发射出来的电子信号可被附近的人所接收以重建显示于所述笔记型电脑的显示影像。
为了减少装置所发射出来的杂讯以及减少感受到来自其他装置的杂讯，装置制造者可对于所述装置提供电磁干扰(EMI)屏蔽。所述电磁干扰屏蔽可能在系统级(例如对于整个智能手机100或笔记型电脑102)、在晶片或电子构件级(例如半导体封装或半导体晶粒)或是在不同层级之间。
因此，本说明书的范例性实施例可以是半导体封装，其包含一个或多个半导体装置、在所述半导体封装的所有外部表面上的电磁干扰(EMI)屏蔽以及开口，在所述开口中放置有电性互连以形成与衬垫的电性接触。
本说明书的另一范例性实施例可以是一种用于屏蔽半导体装置的方法，其中所述方法包含对于包含顶部囊封物和底部囊封物的所述半导体装置，附接第一载体到所述底部囊封物的底部表面，例如当所述半导体装置不具有已附接的第一载体时。所述方法可包含在没有被所述第一载体所覆盖的所述半导体装置的所有外表面上形成外部电磁干扰屏蔽。第二载体可被附接到所述顶部囊封物的顶部表面并且所述第一载体可从所述半导体装置的所述底部囊封物移除。外部底部电磁干扰屏蔽可接着被形成于所述底部囊封物的底部表面上。
本说明书的另外的范例性实施例可以是一种包含半导体装置的半导体封装，其中所述半导体封装也包含顶部囊封物和底部囊封物，并且所述顶部囊封物可囊封所述半导体装置中的至少两个。电磁干扰(EMI)屏蔽可在所述半导体封装的所有外部表面上，并且内部电磁干扰屏蔽可在所述半导体装置中的两个之间。再者，电性互连可通过衬垫以电性连接至所述半导体装置中的至少一个，其中所述衬垫是位在所述底部囊封物中。
图2是图示根据本揭示的范例性实施例的半导体封装的横截面视图。参照图2，显示半导体封装200，其经电磁干扰屏蔽于所述半导体封装200的所有六个侧面上。所述半导体封装200包含由囊封物210所覆盖的半导体晶粒212、214以及由囊封物220所覆盖的半导体晶粒222、224。所述半导体晶粒212、214、222和224可被电性地连接至不同的导电迹线204(通孔、重新分布层(RDLs)、衬垫、导线、电性互连…等)。所述导电迹线204可被埋藏，例如被埋藏在基板201(例如有芯(cored)或无芯(coreless)基板、印刷电路板、包含一个或多个介电层及/或导电层的组合式信号分布结构…等等)中。电子装置232可被连接至所述导电迹线204，所述导电迹线204可例如被部分地或全部地埋置在所述基板201中。所述导电迹线204和所述电子装置232可被认为例如是所述基板201的一部分。电子装置234也可被耦接至所述基板201的下表面。所述电子装置232和234的每一个可以是被动装置、主动装置或被动装置和主动装置的结合。
所述电子连接器206(例如互连结构，像是导电球或凸块、导电柱或杆…等等)可被耦接至所述衬垫208，所述衬垫208在所述基板201的下侧。所述电子装置234、所述电子连接器206以及所述衬垫208可被囊封物230所覆盖。
当所述用语“囊封物”被使用时，应理解的是任何覆盖或囊封所述各种半导体晶粒212、214、222和224、所述电子装置232和234、所述导电迹线204、所述衬垫208…等等的相似结构也可以被称为“囊封物”。因此，模制成型也可以是囊封物的范例。囊封物可包含囊封物材料/层、绝缘材料/层、钝化材料/层、介电材料/层…等等。
囊封物材料的一些范例可以是预浸渍材料(pre-preg)、组成膜(build-up film)、聚合物、聚酰亚胺(PI)、苯环丁烯(BCB)、聚苯恶唑(PBO)、双马来酰亚胺-三氮杂苯(BT)、模制材料、酚醛树脂(phenolic resin)、环氧、硅、丙烯酸聚合物、前述材料的组合物、前述材料的等同物…等等。
内屏蔽202’可运作以阻隔电磁信号与所述经囊封物210所覆盖的装置，反之亦然。在所述半导体封装200的所述顶部、底部、四个侧面上的外屏蔽202可运作以阻隔来自所述半导体封装200的电磁信号传播到半导体封装200的外侧，并且阻隔来自其他半导体装置(未显示)的电磁信号进入所述半导体封装200。因为除了在所述半导体封装200的底部的座落有所述电子连接器206的小区域之外，所述半导体封装200已经在其的所有六个侧面被电磁干扰屏蔽，所以由所述半导体封装200所造成的电磁干扰对于其他电子装置而言应该是最小的。相似地，由在所述半导体封装200外部的其他电子装置所造成的电磁干扰对于所述半导体封装200而言可以是最小的。
虽然具体提到了半导体晶粒，然而本揭示的各种实施例也可包含阻隔来自/传送到在所述半导体封装200中的被动装置(例如电阻器、电容器、电感器)以及来自信号迹线的电磁干扰。此外，半导体晶粒可由半导体装置所取代，所述半导体装置可包含半导体晶粒、离散的主动装置及/或被动装置。
图3-9是显示根据本揭示的实施例屏蔽半导体装置的各种阶段的横截面示图。
图10是用于根据本揭示的实施例屏蔽半导体装置之范例性流程图。图3-9将更详细地解释关于图10的范例性流程图。
在方块1002，图3的包含两侧模制的装置的半导体装置300可被备制以用于电磁干扰屏蔽。所述备制的部分可例如为，如果没有载体存在，则附接所述半导体装置300至载体310。所述载体310可包含一层的材料，其被附接至所述半导体装置300以允许各种操作和处理被执行于所述半导体装置300上。举例而言，所述载体310可包含金属板、玻璃板、半导体晶圆或面板…等等。所述载体310可藉由任何各种方式而被附接至所述半导体装置300，例如使用粘着剂(例如可热剥离粘着剂、化学式可剥离粘着剂、紫外光可剥离粘着剂…等等)、使用真空压力、使用机械箝夹…等等。
所述半导体装置300可例如包含半导体晶粒312、314、322和324，以及电子装置332和334，其可为被动装置或主动装置，或是被动装置和主动装置的组合。所述半导体装置300也可以包含导电迹线302(通孔、RDL、衬垫、导线、电性互连…等等)。所述导电迹线302可例如被埋置在基板308中。所述半导体晶粒312、314、322和324可被囊封物306(例如上囊封物)所覆盖，并且所述导电迹线302和所述电子装置332可被埋置在所述基板308中。所述电子装置334可被囊封物304(例如下囊封物)所覆盖。应注意的是，所述囊封物306和所述囊封物304可以是相同材料，但是并非必须。
当所述用语“囊封物”被使用时，应理解的是任何覆盖或囊封所述各种半导体晶粒312、314、322和324、所述电子装置334…等等的相似结构也可以被称为“囊封物”。因此，囊封物可包含任何适当的囊封物材料/层、绝缘材料/层、钝化材料/层、介电材料/层…等等。
囊封物材料的一些范例可以是预浸渍材料(pre-preg)、组成膜(build-up film)、聚合物、聚酰亚胺(PI)、苯环丁烯(BCB)、聚苯恶唑(PBO)、双马来酰亚胺-三氮杂苯(BT)、模制材料、酚醛树脂(phenolic resin)、环氧、硅、丙烯酸聚合物、前述材料的组合物、前述材料的等同物。
在方块1004，内部屏蔽被形成。在图4A的所述半导体装置300中可看出，空间401被形成在所述囊封物306中，并且在图4B的所述半导体装置300中，内部屏蔽402被形成在所述空间401中。图4A中所显示的所述空间401可藉由移除所述囊封物306的一部分以形成所述分隔开的囊封物410和420而被形成，其中囊封物410覆盖所述半导体晶粒312、314并且囊封物420覆盖所述半导体晶粒322、324。可使用任何适当的方法使所述囊封物306的一部分清除而形成所述空间401，例如使用诸如切锯的机械处理、使用化学处理、使用镭射、使用流体或气体喷射…等等。举例而言，所述空间401可完全地延伸在所述半导体装置300的相对侧之间，但是并非必须。举例而言，所述空间401可被特征化为一间隙、沟槽、孔洞…等等。
如图4B中所示，所述空间401可被适当的用于电磁干扰屏蔽的材料填满以形成所述内部屏蔽402。所述内部屏蔽402可以是适当的材料，其可以阻隔至少一些电磁干扰信号。举例而言，所述内部屏蔽402可包含一个或多个适当的屏蔽材料，像是铜、银、金、铝、锡、黄铜、青铜、钢、超合金、μ金属(mumetal)、石墨、复合材料…等等。
用于所述内部屏蔽402的所述材料可使用适当的沉积制程而被沉积，其是根据所述内部屏蔽402的尺寸及/或所述材料的特性，例如像是溅镀、电镀、无电电镀、真空沉积、浸渍、印刷、注入、满溢(flooding)…等等。
在方块1006，外部电磁干扰屏蔽备提供于所述半导体装置的五个侧面处。举例而言，图5的半导体装置300被显示具有额外的外部屏蔽502在所述五个被暴露的(即没有被载体310所覆盖的)侧面上。所述外部屏蔽502可由一个或多个适当的电磁干扰屏蔽材料所形成，例如像是铜、银、金、铝、锡、黄铜、青铜、钢、超合金、μ金属(mumetal)、石墨、复合材料…等等。用于所述外部屏蔽502的所述材料可使用适当的沉积制程而被沉积，例如像是溅镀、电镀、无电电镀、真空沉积、浸渍、印刷、注入、满溢(flooding)…等等。应注意的是，所述外部屏蔽502与所述内部屏蔽402可以是由相同材料所形成，但不必须是由相同材料所形成。又应注意的是，方块1006以及在方块1004中所述屏蔽的形成可使用相同的形成(或沉积)制程而被同时地执行。
在方块1008，载体610是被加至所述半导体装置300的顶部上，如图6A中所示，并且所述载体310是从所述半导体装置300的所述底部而被移除，如图6B中所示。参照图6A，举例而言，所述载体610可相似于所述载体310而被附接至所述半导体装置300的所述顶部。举例而言，所述载体610可被附接至所述半导体装置300的所述顶部，其是以相似于所述载体310被附接至所述半导体装置300的所述底部的方式而被附接，或者是使用其他适当的方法而被附接。
参照图6B，在附接所述载体610之后，可使用任何各种适当的方法移除所述载体310。举例而言，所述载体310可被拉开或剥除；如果有使用粘着剂，所述粘着剂可被溶解或热解胶或UV解胶；所述载体310可使用镭射、磨蚀、研磨、流体或气体喷射…等等而被蚀刻或移除。因此，所述半导体装置300的所述底部表面可被暴露。
在方块1010，如图7中所示，举例而言，当所述顶部表面及/或所述垂直侧表面被沉积有电磁干扰屏蔽材料，所述底部表面可被沉积有电磁干扰屏蔽材料。所述半导体装置300现在被处理成为半导体封装700，其中所有侧面都被电磁干扰屏蔽。用于所述底部表面的外底部屏蔽702的所述电磁干扰屏蔽材料可相似于用于所述外部屏蔽502的所述电磁干扰屏蔽材料，虽然它们不必须为相同的材料。形成所述外底部屏蔽702的制程也可相似于形成用于所述半导体封装700的所述顶部表面的所述外部屏蔽502的制程，虽然它们不必须为相同的方法。应注意的是，为了说明清楚，如图7所示的装置700的定向与其他图保持一致。在所述外底部屏蔽702的形成过程中或是在本文所探讨的任何处理步骤的过程中，所述装置700的定向或显示于本文中的任何范例装置的定向都可被改变。
在方块1012，图8A的所述半导体封装700可具有多个部分的所述电磁干扰屏蔽材料702并且所述囊封物304被移除以形成开口802，所述开口802提供通道给衬垫320。所述电磁干扰屏蔽材料702可以任何适当的方法被移除，例如机械磨蚀、化学蚀刻、镭射消蚀、使用流体或气体喷射…等等。一但所述囊封物304被暴露，用于暴露所述衬垫320的所述制程可以是任何适当的方法。举例来说，多个部分的所述囊封物304可使用适当的制程而被移除，例如镭射消蚀，然而，如果适合，也可以使用其他制程例如化学消蚀、机械消蚀、使用流体或气体喷射以用于消蚀所述囊封物304的多个部分…等等。
所述消蚀制程可以是单一步骤或是多个步骤的制程。举例而言，两个步骤的消蚀制程被显示于图8B到8D。在显示于图8B和图8C的第一个步骤中，例如镭射(或是其他材料移除技术)可被使用来移除所述电磁干扰屏蔽材料702以开启所述开口802，并且所述镭射可被进一步用来移除所述囊封物材料304的第一期望部分以形成第一凹陷(或所述开口802的第一部分)。接着在图8D所显示的第二步骤中，所述镭射(或其他材料移除技术)可被使用以形成第二凹陷(或所述开口802的第二部分)以暴露所述衬垫320。举例而言，所述第二凹陷可以窄于所述第一凹陷，但是这不是必须的情况。每个所述各别的凹陷(或开口部分)可以具有各别的垂直或斜侧面。如图8D中所示，在一范例性执行过程中，所述第二凹陷窄于所述第一凹陷，可能有隔板在所述第一凹陷和第二凹陷之间。例如，此隔板可以提供在电子连接器(其随后被附接至所述衬垫320)和所述外底部屏蔽702之间的缓冲空间。
举例而言，另一制程可以是三个步骤的制程，其包含首先移除所述电磁干扰屏蔽材料702，接着执行所述囊封物材料304的第一阶段移除，接着执行所述囊封物材料304的第二阶段移除。举例而言，另一制程可以允许所述镭射(或气体或液体的喷射)的多个扫描，其中所述凹陷的宽度是被所述镭射的每次扫描所控制。因此，各种制程可被使用以形成不同形状的所述开口802以暴露所述衬垫320。
又在另一范例执行中，一个步骤制程可被使用以形成所述开口802。举例而言，单一镭射消蚀(或是其他材料移除)步骤可被执行以形成所述开口802。在此执行中，所述开口802可具有连续侧壁(例如，垂直侧壁、斜侧壁…等等)。
在方块1014，图9的所述半导体封装700可具有附接到所述衬垫320的电性互连902。所述电性互连902可以是任何适当的互连，例如导电球或导电柱。所述导电球或导电柱可由任何适当的材料所制成。例如，所述电性互连902可以是焊球，其可被加热(例如使用焊料回焊制程)至熔化所述焊球的至少一些，而当所述熔化的焊料冷却时，则形成至所述衬垫320的连接。又举例来说，所述电性互连902可包含铜柱或杆，其通过所述开口802而被放置在所述衬垫320上。任何适当的方法可被用来附接所述电性互连902到所述衬垫320。附接所述电性互连902的方法可根据所述互连的种类。
当所述半导体封装700的所述电磁干扰屏蔽完成时，所述载体610可以一适当的方法被移除，所述方法可以是相似于关于所述载体310的方法。所述半导体封装700可接着准备用于组装件以作为例如印刷电路板的部分。
各种其他制程可被接着执行以用于屏蔽半导体装置的所有六个侧面。举例而言，某些实施例可同时形成所述内部屏蔽402和所述外部屏蔽502。其它实施例可只有形成所述外部屏蔽502于所述半导体装置300的垂直侧表面的一部分上，以及所述外部屏蔽502在所述半导体装置300的顶部表面上。接着，在随后的步骤中，所述外部屏蔽502的残留物可被形成于所述半导体装置300的垂直侧表面上，以及形成所述外底部屏蔽702在所述半导体装置300的所述底部表面上。
在这样的制程中，可能有另一步骤来铺平可能是在所述半导体封装700的所述垂直侧表面上的所述外部屏蔽502的任何重叠。所述重叠可例如是，来自当所述外部屏蔽502被形成在所述半导体装置300的所述顶部表面上时以及来自当所述外底部屏蔽702被形成在所述半导体装置300的所述底部表面上时，发生在所述垂直侧表面上的一给定区上的重叠。所述铺平步骤也可以被用来实施于有需要的其他实施例。
此外，各种实施例也可以以填充材料、模制材料、绝缘材料或任何其他适当的材料回填所述开口。再者，所述内部屏蔽402、所述外部屏蔽502及/或所述外底部屏蔽702可选择性地例如连接至所述半导体封装700的接地路径/平面或连接至电性互连，其中所述电性互连会被连接到所述半导体封装700所安装的装置/PCB的接地路径/平面。
举例来说，参照图9，所述内部屏蔽402、所述外部屏蔽502及/或所述外底部屏蔽702的接地可被做成，例如藉由电性连接所述内部屏蔽402到导电迹线302的接地部分或是藉由电性连接所述外部屏蔽502到所述半导体封装700的所述侧面处的所述导电迹线302的接地部分。
图11是图示根据本说明书的实施例的半导体封装之横截面示图。参照图11，显示一实施例，其中所述内部屏蔽402、所述外部屏蔽502及/或所述外底部屏蔽702是电性连接至导电互连1102。在此情况中，形成电性连接1104可例如从所述外底部屏蔽702到导电互连1102。当此电性连接1104被形成，其中放置有所述导电互连1102的所述开口802可被回填以提供所述电性连接1104的支撑，所述电性连接1104将连接所述外底部屏蔽702到所述导电互连1102。所述回填1106可使用任何适当的材料，例如像是填充材料、模制材料、绝缘材料及/和其它适当的材料。用于回填的所述特定材料可例如根据用来做成所述囊封物304的材料。所述衬垫1108不是跟所述半导体封装700的其他部分绝缘就是连接至所述半导体封装700的接地迹线/平面。
在另一实施中，第一个所述开口802(例如对应于接地互连)可被形成而窄于其他的所述开口802(例如对应于一般电信号)。在此实施中，当所述互连被形成时(例如焊料回焊)，所述互连可与所述外底部屏蔽电性接触以提供接地信号接触。
然而，典型的半导体装置可具有六侧面，此叙述也适用于具有不同数目的侧面的半导体装置。此外，所述半导体装置可具有不同数量的半导体晶粒、不同数量的内部屏蔽、不同数量的半导体晶粒的层…等等。此外，当所述各种半导体装置/封装200、300、700被描述有包含半导体晶粒时，应理解的是，半导体装置/封装可包含其他半导体装置/封装、半导体晶粒、被动装置…等等。
此外，当描述于此的所述电性互连902被电性连接至所述衬垫320，所述衬垫320是被所述囊封物304覆盖，然而本揭示的各种实施例不需要被此限缩。举例来说，衬垫320可被埋置在所述囊封物304之中，而至少所述衬垫320的底部表面被暴露。然而，应注意的是，如果除了所述衬垫320的底部表面还有其它地方从所述囊封物304暴露，且如果所述外底部屏蔽702和所述衬垫320之间的电性连接是不希望的，则所述衬垫320的所述暴露区可能需要被绝缘以防止对于所述外底部屏蔽702的短路。所述绝缘不是被提供于所述囊封物304的形成期间就是在形成所述外底部屏蔽702之前藉由额外的步骤所提供。
尽管已经参照某些支持实施例描述了根据本揭示的各种态样的具有电磁干扰屏蔽的半导体封装及其制造方法，但是所属技术领域中具有通常知识者将会理解，本揭示不限于所揭露的特定实施例，而是本揭示将包括落入所附权利要求书的范畴内的所有实施例。
以上所述仅是本发明的优选实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以优选实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案的范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本实用发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (20)

1.一种半导体封装，其特征在于，包含：
一个或多个半导体装置；
电磁干扰屏蔽，在所述半导体封装的所有外表面上；以及
开口，在所述开口中放置有电性互连以形成与衬垫的电性接触。
2.如权利要求1所述的半导体封装，其特征在于，包含内部电磁干扰屏蔽，其在所述一个或多个半导体装置中的两个半导体装置之间。
3.如权利要求1所述的半导体封装，其特征在于，所述电性互连是电性地连接至所述电磁干扰屏蔽。
4.如权利要求1所述的半导体封装，其特征在于，所述电性互连是电性地连接至所述半导体封装的接地迹线。
5.如权利要求1所述的半导体封装，其特征在于，所述电性互连是焊球。
6.如权利要求1所述的半导体封装，其特征在于，所述开口是形成在所述电磁干扰屏蔽的一部分之中并且在所述半导体封装的底部上的囊封物之中。
7.如权利要求6所述的半导体封装，其特征在于，所述开口包含没有被所述电性互连所占据的空间的体积，并且所述空间的体积是实质上被回填以形成与所述囊封物的底部实质上共平面的底部表面。
8.一种用于屏蔽半导体装置的方法，其特征在于，包含：
对于包含顶部囊封物和底部囊封物的所述半导体装置，附接第一载体到所述底部囊封物的底部表面；
在没有被所述第一载体覆盖的所述半导体装置的所有外表面上形成外部电磁干扰屏蔽；
附接第二载体到所述顶部囊封物的顶部表面；
从所述半导体装置的所述底部囊封物移除所述第一载体；以及
形成外部底部电磁干扰屏蔽于所述底部囊封物的底部表面上。
9.如权利要求8所述的方法，其特征在于，包含附接电性互连至所述半导体装置。
10.如权利要求9所述的方法，其特征在于，所述电性互连被电性地连接至所述外部电磁干扰屏蔽以及所述外部底部电磁干扰屏蔽。
11.如权利要求9所述的方法，其特征在于，包含形成开口，所述开口穿透所述外部底部电磁干扰屏蔽并且穿透所述底部囊封物以暴露衬垫，并且其中前述附接所述电性互连包含经由所述开口而附接所述电性互连至所述衬垫。
12.如权利要求11所述的方法，其特征在于，前述形成所述开口包含使用镭射以形成所述开口。
13.如权利要求11所述的方法，其特征在于，前述形成所述开口包含：
形成第一凹陷；以及
形成第二凹陷，其中所述第二凹陷是窄于所述第一凹陷并且暴露所述衬垫。
14.如权利要求11所述的方法，其特征在于，包含在前述附接所述电性互连至所述衬垫之后回填所述开口。
15.如权利要求8所述的方法，其特征在于：
前述形成所述外部电磁干扰屏蔽包含使用溅镀以形成所述外部电磁干扰屏蔽的至少一部分；并且
前述形成所述外部底部电磁干扰屏蔽包含使用溅镀以形成所述外部底部电磁干扰屏蔽的至少一部分。
16.如权利要求8所述的方法，其特征在于，包含移除所述顶部囊封物的一部分以形成在两个半导体晶粒之间的空间。
17.如权利要求16所述的方法，其特征在于，包含形成内部电磁干扰屏蔽在两个半导体晶粒之间的所述空间中。
18.如权利要求17所述的方法，其特征在于，前述形成所述内部电磁干扰屏蔽包含使用溅镀以形成所述内部电磁干扰屏蔽。
19.如权利要求17所述的方法，其特征在于，所述内部电磁干扰屏蔽被电性地连接至所述外部电磁干扰屏蔽和所述外部底部电磁干扰屏蔽。
20.一种半导体封装，其特征在于，包括：
半导体装置；
顶部囊封物和底部囊封物，其中所述顶部囊封物囊封至少两个所述半导体装置；
电磁干扰屏蔽，在所述半导体封装的所有外表面上；
内部电磁干扰屏蔽，在所述至少两个所述半导体装置之间；以及
电性互连，通过衬垫而电性地连接至所述半导体装置中的至少一者，其中所述衬垫是位在所述底部囊封物中。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110993508A (zh) * 2019-11-22 2020-04-10 青岛歌尔智能传感器有限公司 封装结构及其制作方法、以及电子设备
CN111863775A (zh) * 2020-06-16 2020-10-30 珠海越亚半导体股份有限公司 散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板
CN113410145A (zh) * 2021-06-21 2021-09-17 东莞记忆存储科技有限公司 六面电磁屏蔽的倒装芯片封装方法
CN113611688A (zh) * 2021-08-03 2021-11-05 东莞记忆存储科技有限公司 一种芯片结构及其加工方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6822555B2 (ja) * 2017-04-19 2021-01-27 株式会社村田製作所 モジュール
US10453762B2 (en) * 2017-07-28 2019-10-22 Micron Technology, Inc. Shielded fan-out packaged semiconductor device and method of manufacturing
US10636742B2 (en) * 2017-09-28 2020-04-28 Dialog Semiconductor (US) Limited Very thin embedded trace substrate-system in package (SIP)
FR3079068B1 (fr) * 2018-03-13 2023-05-26 St Microelectronics Grenoble 2 Dispositifs electroniques et procedes de fabrication
US10566313B1 (en) * 2018-08-21 2020-02-18 International Business Machines Corporation Integrated circuit chip carrier with in-plane thermal conductance layer
TWI679744B (zh) * 2018-10-04 2019-12-11 力成科技股份有限公司 多層封裝基板
US11075167B2 (en) 2019-02-01 2021-07-27 Dialog Semiconductor (Uk) Limited Pillared cavity down MIS-SIP
US20200388576A1 (en) * 2019-06-10 2020-12-10 Intel Corporation Layer for etched identification marks on a package
US11774519B2 (en) * 2019-08-27 2023-10-03 Texas Instruments Incorporated Shielded sensor structure and method of making same
US11127647B2 (en) * 2019-12-04 2021-09-21 Amkor Technology Singapore Holding Pte. Ltd Semiconductor devices and related methods
US11605598B2 (en) * 2020-04-17 2023-03-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN112103269B (zh) * 2020-08-07 2022-09-20 珠海越亚半导体股份有限公司 一种具有屏蔽腔的嵌入式封装结构及其制造方法
KR20220020018A (ko) * 2020-08-11 2022-02-18 삼성전기주식회사 부품 패키지 및 이에 이용되는 인쇄회로기판
US11728280B2 (en) * 2021-01-15 2023-08-15 Amkor Technology Singapore Holding Pte. Lid. Semiconductor devices and methods of manufacturing semiconductor devices
CN113823605A (zh) * 2021-08-11 2021-12-21 紫光宏茂微电子(上海)有限公司 芯片封装结构及其制作方法
TWI818458B (zh) * 2022-03-04 2023-10-11 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060220209A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US20090194851A1 (en) * 2008-02-05 2009-08-06 Chi-Tsung Chiu Semiconductor device packages with electromagnetic interference shielding
US8093691B1 (en) * 2009-07-14 2012-01-10 Amkor Technology, Inc. System and method for RF shielding of a semiconductor package
US20120217642A1 (en) * 2011-02-28 2012-08-30 Yu-Ching Sun Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US20120223429A1 (en) * 2011-03-03 2012-09-06 Broadcom Corporation Package 3D Interconnection and Method of Making Same
US20120228749A1 (en) * 2011-03-08 2012-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to tsv interposer
DE102012104345A1 (de) * 2011-05-30 2012-12-06 Samsung Electronics Co., Ltd. Halbleitervorrichtung, Halbleitergehäuse und elektronische Vorrichtung
US20130223041A1 (en) * 2012-02-23 2013-08-29 Apple Inc. Low profile, space efficient circuit shields
CN105552061A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装元件
US20160126220A1 (en) * 2014-10-30 2016-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic Discharge Protection Structure and Method
US9397074B1 (en) * 2015-04-29 2016-07-19 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US20160218049A1 (en) * 2015-01-23 2016-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufactures
US20160270213A1 (en) * 2015-02-11 2016-09-15 Apple Inc. Low-profile space-efficient shielding for sip module
US20160276307A1 (en) * 2015-03-17 2016-09-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming POP Semiconductor Device with RDL Over Top Package
US20160300797A1 (en) * 2015-04-09 2016-10-13 Stats Chippac, Ltd. Double-Sided Semiconductor Package and Dual-Mold Method of Making Same
KR101674322B1 (ko) * 2015-11-18 2016-11-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
CN106169445A (zh) * 2015-05-22 2016-11-30 艾马克科技公司 用以制造具有多层模制导电基板和结构半导体封装的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090140419A1 (en) * 2007-11-29 2009-06-04 Kenneth Rhyner Extended plating trace in flip chip solder mask window
US7851894B1 (en) 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
JP2012019091A (ja) 2010-07-08 2012-01-26 Sony Corp モジュールおよび携帯端末
TWI397964B (zh) * 2011-01-19 2013-06-01 Unisem Mauritius Holdings Ltd 部分圖案化之引線框架及其在半導體封裝中製作與使用的方法
US20120228751A1 (en) * 2011-03-07 2012-09-13 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US9196588B2 (en) * 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US8420437B1 (en) * 2011-12-05 2013-04-16 Powertech Technology Inc. Method for forming an EMI shielding layer on all surfaces of a semiconductor package
US9281281B2 (en) * 2014-03-03 2016-03-08 Intel Corporation Integrated circuit component shielding
KR101598688B1 (ko) 2014-03-25 2016-02-29 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI611533B (zh) * 2014-09-30 2018-01-11 矽品精密工業股份有限公司 半導體封裝件及其製法
KR20160048277A (ko) * 2014-10-23 2016-05-04 에스케이하이닉스 주식회사 칩 내장 패키지 및 그 제조방법
US9570406B2 (en) * 2015-06-01 2017-02-14 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
US9842826B2 (en) * 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US20170118877A1 (en) * 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with bond wires to provide internal shielding between electronic components
KR101712288B1 (ko) 2015-11-12 2017-03-03 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US9818722B1 (en) * 2016-08-05 2017-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for manufacturing thereof
WO2018067578A1 (en) * 2016-10-04 2018-04-12 Skyworks Solutions, Inc. Dual-sided radio-frequency package with overmold structure

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060220209A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US20090194851A1 (en) * 2008-02-05 2009-08-06 Chi-Tsung Chiu Semiconductor device packages with electromagnetic interference shielding
US8093691B1 (en) * 2009-07-14 2012-01-10 Amkor Technology, Inc. System and method for RF shielding of a semiconductor package
US20120217642A1 (en) * 2011-02-28 2012-08-30 Yu-Ching Sun Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US20120223429A1 (en) * 2011-03-03 2012-09-06 Broadcom Corporation Package 3D Interconnection and Method of Making Same
US20120228749A1 (en) * 2011-03-08 2012-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to tsv interposer
DE102012104345A1 (de) * 2011-05-30 2012-12-06 Samsung Electronics Co., Ltd. Halbleitervorrichtung, Halbleitergehäuse und elektronische Vorrichtung
US20130223041A1 (en) * 2012-02-23 2013-08-29 Apple Inc. Low profile, space efficient circuit shields
CN105552061A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装元件
US20160126220A1 (en) * 2014-10-30 2016-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic Discharge Protection Structure and Method
US20160218049A1 (en) * 2015-01-23 2016-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufactures
US20160270213A1 (en) * 2015-02-11 2016-09-15 Apple Inc. Low-profile space-efficient shielding for sip module
US20160276307A1 (en) * 2015-03-17 2016-09-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming POP Semiconductor Device with RDL Over Top Package
US20160300797A1 (en) * 2015-04-09 2016-10-13 Stats Chippac, Ltd. Double-Sided Semiconductor Package and Dual-Mold Method of Making Same
US9397074B1 (en) * 2015-04-29 2016-07-19 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN106169445A (zh) * 2015-05-22 2016-11-30 艾马克科技公司 用以制造具有多层模制导电基板和结构半导体封装的方法
KR101674322B1 (ko) * 2015-11-18 2016-11-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110993508A (zh) * 2019-11-22 2020-04-10 青岛歌尔智能传感器有限公司 封装结构及其制作方法、以及电子设备
CN111863775A (zh) * 2020-06-16 2020-10-30 珠海越亚半导体股份有限公司 散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板
CN111863775B (zh) * 2020-06-16 2022-07-26 珠海越亚半导体股份有限公司 散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板
CN113410145A (zh) * 2021-06-21 2021-09-17 东莞记忆存储科技有限公司 六面电磁屏蔽的倒装芯片封装方法
CN113611688A (zh) * 2021-08-03 2021-11-05 东莞记忆存储科技有限公司 一种芯片结构及其加工方法

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