CN112103269B - 一种具有屏蔽腔的嵌入式封装结构及其制造方法 - Google Patents

一种具有屏蔽腔的嵌入式封装结构及其制造方法 Download PDF

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CN112103269B
CN112103269B CN202010791224.4A CN202010791224A CN112103269B CN 112103269 B CN112103269 B CN 112103269B CN 202010791224 A CN202010791224 A CN 202010791224A CN 112103269 B CN112103269 B CN 112103269B
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layer
shielding
insulating layer
copper
cavity
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CN112103269A (zh
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陈先明
顾敏
冯磊
姜丽娜
黄本霞
王闻师
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Zhuhai Yueya Semiconductor Co ltd
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Abstract

本发明公开了一种具有屏蔽腔的嵌入式封装结构,包括嵌埋在绝缘层内的器件和封闭所述器件的屏蔽腔,其中所述屏蔽腔由嵌入在所述绝缘层中四面围绕所述器件的屏蔽墙以及覆盖在所述屏蔽墙的第一端面和第二端面上的第一线路层和第二线路层构成,所述第一线路层和第二线路层与所述屏蔽墙电连接;其中在所述屏蔽墙的第一端面与所述第一线路层之间形成有引线开口,连接所述器件的端子的信号线从所述引线开口引出所述屏蔽腔。还公开了一种具有屏蔽腔的嵌入式封装结构的制造方法。

Description

一种具有屏蔽腔的嵌入式封装结构及其制造方法
技术领域
本发明涉及电子器件封装结构,具体涉及具有屏蔽腔的嵌入式封装结构及其制造方法。
背景技术
电磁干扰主要由干扰源、传输路径和敏感设备组成,其中干扰源包括微处理器、微控制器、传送器、静电放电和瞬时功率执行元件,如机电式继电器、开关电源、雷电等。在微控制器系统中,时钟电路是最大的宽带噪声发生器,而这个噪声被扩散到整个频谱,随着大量的高速半导体器件的发展,其边沿跳变速率很快,这种电路将产生高达300MHz的谐波干扰。
电磁干扰对电子系统和电子设备的危害在于:强烈的电磁干扰可能使灵敏电子设备因过载而损坏,一般硅晶体管发射极与基极间的反向击穿电压为2~5V,很易损坏,而且其反向击穿电压随温度升高而下降,电磁干扰引起的尖峰电压能使发射结和集电结中某点杂质浓度增加,导致晶体管击穿或内部短路,在强射频电磁场下工作的晶体管会吸收足够的能量,使结温超过允许温升而导致损坏;增加了发、输、供和用电设备的附加损耗,使设备过热,降低设备的效率和利用率,由于谐波电流的频率为基波频率的整数倍,高频电流流过导体时,因集肤效应的作用,使导体对谐波电流的有效电阻增加,从而增加了设备的功率损耗、电能损耗,使导体的发热严重。
在传统的表面贴装产品中,器件作为电磁干扰的干扰源及敏感部分,如IGBT(绝缘栅双极晶体管),通常是在封装体外部(5个面)加一个金属外壳,用来降低大量的电磁辐射溢出或外界电磁干扰,而在第6面上为引脚,无屏蔽。
现有技术的缺点在于:1.封装后加金属外壳屏蔽的方式只适用于表面贴装,而不能用于嵌埋产品;2.使用金属外壳只能防止5个方向上的电磁辐射,无法防止辐射从无屏蔽的另一面溢出和进入,电磁辐射和干扰可以从引脚位置产生影响;3.引脚通过锡球焊接在母板上,锡球的直径和高度目前普遍在百微米级,此面无屏蔽防护难以实现从信号的发出端到传输路径上的整体屏蔽。
因此,目前对于嵌入式封装器件急需能够实现全面电磁屏蔽的屏蔽结构。
发明内容
本发明的实施方案涉及提供一种具有屏蔽腔结构的嵌入式封装结构及其制造方法,以解决上述技术问题。本发明通过在嵌入式器件周围的六个面形成几乎完全封闭的屏蔽腔结构,实现了对嵌入式器件的完美屏蔽效果,从而可以减小相邻器件间的距离,提高集成度,减小封装体积。
本发明第一方面涉及一种具有屏蔽腔的封装结构,包括嵌埋在绝缘层内的器件和封闭所述器件的屏蔽腔,其中所述屏蔽腔由嵌入在所述绝缘层中四面围绕所述器件的屏蔽墙以及覆盖在所述屏蔽墙的第一端面和第二端面上的第一线路层和第二线路层构成,所述第一线路层和第二线路层与所述屏蔽墙电连接;其中在所述屏蔽墙的第一端面与所述第一线路层之间形成有引线开口,连接所述器件的端子的信号线从所述引线开口引出所述屏蔽腔。
在一些实施方案中,所述屏蔽墙由铜柱形成。
在一些实施方案中,在所述信号线两侧设置有与所述信号线平行的接地屏蔽线,以防止信号线受到干扰。
在一些实施方案中,所述绝缘层包括封装材料,所述封装材料通常为聚合物电介质,优选选自半固化片、双马来酰亚胺/三嗪树脂、聚酰亚胺、聚氯乙烯、膜状有机树脂、环氧树脂或聚苯醚中的一种或多种的组合。
在一些实施方案中,所述器件选自裸芯片、无源器件和封装体中的任意一种或多种的组合,优选地,所述器件包括电容器、电感器、射频芯片或振荡器等。
在一些实施方案中,所述屏蔽腔接地。
在本发明的第二方面,提供一种具有屏蔽腔的嵌入式封装结构的制造方法,包括如下步骤:
(A)制作具有贯通空腔的框架,其中所述框架包括聚合物电介质和嵌入在所述聚合物电介质中包围所述贯通空腔的屏蔽铜柱;
(B)在所述贯通空腔中置入器件并填充封装材料形成第一绝缘层;
(C)在所述第一绝缘层的第一表面上施加聚合物电介质形成第二绝缘层;
(D)在所述第二绝缘层上开孔暴露出所述屏蔽铜柱的第一端面和所述器件的端子,同时保留预定的信号线引出开口位置的聚合物电介质;
(E)在所述第二绝缘层上形成连接所述器件的端子的信号线,其中所述信号线穿过所述信号线引出开口位置;
(F)将所述屏蔽铜柱从第一端面增层延伸超出第二绝缘层;
(G)在所述屏蔽铜柱上施加聚合物电介质形成第三绝缘层;
(H)减薄第一绝缘层和第三绝缘层暴露出所述屏蔽铜柱的第一端面和第二端面;
(I)在所述第三绝缘层和第一绝缘层上形成第一线路层和第二线路层,其中第一线路层和第二线路层覆盖在所述屏蔽铜柱的第一端面和第二端面上并与所述屏蔽铜柱电连接。
在一些实施方案中,步骤A还包括:
-在临时承载板上施加光刻胶层,经曝光显影形成第一图案;
-在所述第一图案中镀覆金属铜,形成屏蔽铜柱和牺牲铜柱;
-移除所述光刻胶层;
-施加聚合物电介质层以覆盖所述屏蔽铜柱和牺牲铜柱;
-减薄所述聚合物电介质层以暴露出所述屏蔽铜柱和牺牲铜柱的顶端面;
-移除所述临时承载板;
-蚀刻所述牺牲铜柱形成贯通空腔,其中所述屏蔽铜柱包围所述贯通空腔,由此得到具有贯通空腔的框架。
在另一些实施方案中,步骤A还包括:
-在临时承载板上施加光刻胶层,经曝光显影形成第一图案;
-在所述第一图案中镀覆金属铜,形成屏蔽铜柱;
-移除所述光刻胶层;
-施加聚合物电介质层覆盖所述屏蔽铜柱;
-减薄所述聚合物电介质层以暴露出所述屏蔽铜柱的顶端面;
-移除所述临时承载板;
-对所述聚合物电介质层进行机械冲压或激光钻孔的方式形成被所述屏蔽铜柱包围的贯通空腔,由此得到具有贯通空腔的框架。
在一些实施方案中,步骤B包括:
-在所述框架的一面上施加胶带;
-在所述贯通空腔中置入器件并使所述器件贴装在所述胶带上;
-在所述框架的另一面上施加封装材料形成第一绝缘层,其中所述封装
材料填充所述器件与框架之间的间隙;
-移除所述胶带。
在一些实施方案中,所述聚合物电介质选自半固化片、双马来酰亚胺/三嗪树脂、聚酰亚胺、聚氯乙烯、膜状有机树脂、环氧树脂或聚苯醚中的一种或多种的组合。优选地,所述聚合物电介质可以是感光型树脂材料,例如感光型聚酰亚胺或感光型聚苯醚。
在一些实施方案中,步骤E还包括:
-在所述信号线的两侧形成屏蔽线,并且所述屏蔽线与所述信号线一起穿过所述信号线引出开口位置。
在一些实施方案中,步骤F还包括:
-在所述第二绝缘层上施加光刻胶层,
-对所述光刻胶层曝光显影形成开孔,暴露出所述屏蔽铜柱的第一端面;
-对所述开孔镀铜,形成增层屏蔽铜柱;
-移除所述光刻胶。
在一些实施方案中,步骤H还包括:
-通过机械研磨或等离子体蚀刻的方式进行减薄。
在一些实施方案中,步骤I还包括:
-在暴露出所述屏蔽铜柱的第一端面和第二端面的第三绝缘层和第一绝缘层上施加种子层;
-在种子层上施加光刻胶层;
-图案化形成线路图案;
-在线路图案中镀铜;
-剥除光刻胶;
-移除种子层。
附图说明
为了更好地理解本发明并示出本发明的实施方式,以下纯粹以举例的方式参照附图。
具体参照附图时,必须强调的是特定的图示是示例性的并且目的仅在于说明性地讨论本发明的优选实施方案,并且基于提供被认为是对于本发明的原理和概念方面的描述最有用和最易于理解的图示的原因而被呈现。就此而言,没有试图将本发明的结构细节以超出对本发明基本理解所必须的详细程度来图示;参照附图的说明使本领域技术人员认识到本发明的几种形式可如何实际体现出来。在附图中:
图1为根据本发明的一个实施方案的具有屏蔽腔的嵌入式封装结构的截面示意图;
图2(a)~2(q)示出图1所示的封装结构的制造方法的各步骤中间结构的示意图。
具体实施方式
参照图1,示出嵌入式封装结构100的截面示意图。封装结构100包括第一绝缘层141和嵌埋在第一绝缘层141内的器件170,以及包围封闭器件170的屏蔽腔180,其中屏蔽腔180由嵌入在聚合物电介质140中四面围绕器件170的屏蔽墙131以及覆盖在屏蔽墙131的第一端面121和第二端面122上的第一线路层135和第二线路层136构成,第一线路层135和第二线路层136与屏蔽墙131电连接。在屏蔽墙131与第一线路层135之间形成有引线开口181,连接器件170的端子171的信号线133从引线开口181引出屏蔽腔180。
第一绝缘层141可以是封装材料,通常为聚合物电介质,优选选自半固化片、双马来酰亚胺/三嗪树脂、聚酰亚胺、聚氯乙烯、膜状有机树脂(ABF)、环氧树脂或聚苯醚中的一种或多种的组合。优选地,第一绝缘层141可以是热固性树脂材料(例如TaiyoZaristo909S)或感光型树脂材料(例如Hitachi PVF-02)。
嵌埋器件170可以是发射电磁干扰或对电磁干扰敏感的器件,可以是裸芯片、无源器件和封装体中的任意一种或多种的组合。优选地,所述器件包括电容器、电感器、射频芯片或振荡器等。
屏蔽墙131可以是由铜通孔柱构成的回字形结构,在四个面围绕器件170,防止横向电磁干扰。
从器件170的端子171引出的信号线133的两侧还可以设置屏蔽线132,屏蔽线132可以连接屏蔽墙或者接地,以防止信号线133在传输过程中受到电磁干扰。
信号线133引出屏蔽腔180后可以形成端子,以与基板进行电连接。
参照图2(a)~2(o),示出图1的具有屏蔽腔的嵌入式封装结构100的制造方法的各个步骤的中间结构的示意图。
嵌入式封装结构100的制造方法包括如下步骤:
在临时承载板110上施加光刻胶层120,经曝光显影后形成第一图案121,如图2(a)所示。临时承载板102可以是玻璃基板、牺牲铜箔或覆铜板(CCL),例如可以是单面或双面覆有双层铜箔的覆铜板。本发明可以通过临时承载板进行单面或双面增层,本实施方案仅示出单面增层作为示例。
在第一图案121中镀覆金属铜并移除光刻胶层120,形成屏蔽铜柱131和牺牲铜柱130,如图2(b)所示。镀覆金属铜通常可以通过电镀进行,第一图案121可以根据设计包括更多的铜柱,例如用于导通特征结构的导通铜柱等。
施加聚合物电介质层140以覆盖屏蔽铜柱131和牺牲铜柱130,接着减薄聚合物电介质层141以暴露出屏蔽铜柱131和牺牲铜柱130的顶端面,如图2(c)所示。聚合物电介质层140构成框架的主体,为框架提供刚性支撑,通常选自半固化片、双马来酰亚胺/三嗪树脂、聚酰亚胺、聚氯乙烯、膜状有机树脂(ABF)、环氧树脂或聚苯醚中的一种或多种的组合。
图2(d)为图2(c)的俯视图,图2(c)是沿图2(d)的A-A'线的截面图。如图2(d)所示,屏蔽铜柱131和牺牲铜柱130形成屏蔽铜柱131围绕牺牲铜柱130的“回”字型图案。
接着,移除临时承载板110,如图2(e)所示。
然后,蚀刻掉牺牲铜柱131,在框架140中形成贯通空腔150,其中屏蔽铜柱131包围贯通空腔150,由此得到具有贯通空腔150的框架140,如图2(f)所示。当临时承载板110为双层铜箔覆铜板时,由于双层铜箔是通过物理压合附着在一起,因此可以通过简单分开双层铜箔来移除覆铜板,附着在框架140上的单层铜箔可以通过蚀刻移除。蚀刻牺牲铜柱130的方法可以是利用光刻胶图案化形成蚀刻阻挡层,蚀刻后移除蚀刻阻挡层。
作为替代方案,形成具有贯通空腔150的方法还可以包括:在临时承载板110上仅形成“口”字型的屏蔽铜柱131,在层压聚合物电介质层140并减薄暴露出屏蔽铜柱131的顶端面后,移除临时承载板110,对聚合物电介质层140进行机械冲压或激光钻孔形成被屏蔽铜柱131包围的贯通空腔150,由此得到具有贯通空腔150的框架140。
图2(g)是图2(f)的俯视图,其中屏蔽铜柱131形成为包围贯通空腔150的“口”字型屏蔽墙。
接着,在框架140的一面上施加胶带160,在贯通空腔150中置入器件170并使器件170贴附固定在胶带160上,如图2(h)所示。胶带160可以是热解型或光解型胶带,可以通过加热或照射紫外光而崩解。在蚀刻后的空腔150区域内放置器件170,器件170可以是对外界产生电磁干扰的电容器、电感器等,也可以是需要抗干扰的射频芯片、振荡器等功能器件。器件170利用胶带160临时固定,器件的端子面171固定在胶带160上。
多个器件170可以根据功能及设计贴在同一个空腔150内,也可以为了防止不同器件间的互相干扰而贴装在具有独立屏蔽墙的独立空腔内,不需要屏蔽的多个器件也可以设置在一个或多个无屏蔽结构的空腔内。
器件170的厚度与空腔150的深度之间的高度差应不低于5μm,通常5~30μm,但当嵌埋的器件170工作在极高压条件下时,可适当根据封装材料的耐电压性能增加器件背面与空腔150的上边缘之间的高度差,以防止被击穿,例如当嵌埋器件在12V的电压下工作时,高度差可控制在15μm,但当嵌埋器件在650V的电压下工作时,高度差应控制在50~70μm。当然,该高度差并非限制性的,可以通过选择封装材料的耐电性能来确定。
然后,在框架140的另一面上施加封装材料形成第一绝缘层141,使得封装材料填充器件170与框架140之间的间隙,如图2(i)所示。封装材料141通常需要具有很好的缝隙填充能力,优选封装材料为膜状、粉末状或液态的,可以通过贴膜、注塑、涂布/网印的方式填充空腔150与器件170间的间隙,优选选自聚酰亚胺、聚氯乙烯、膜状有机树脂(ABF)、聚苯醚或环氧树脂等,可以与聚合物电介质层140相同或不同。框架140通常需要为结构提供刚性支撑,而封装材料141通常要具有很好的缝隙填充能力,因此优选二者组合使用不同的封装材料,例如可以采用半固化片(PP)或BT树脂作为框架材料140,采用膜状有机树脂(ABF)作为第一绝缘层141,ABF具有良好的流动性可以较好地填充器件间的间隙,而PP或BT因具有玻璃纤维结构能够提供足够的刚性支撑。
接着,移除胶带160,如图2(j)所示。可以通过加热或照射紫外光使胶带160发生崩解而将其移除。
然后,在第一绝缘层141的第一表面(下表面)也就是器件的端子面171上施加树脂材料覆盖整个板面,形成第二绝缘层142,如图2(k)所示。第二绝缘层142的材料可以是半固化片(PP)或膜状的增层材料,如ABF、PI、PPO等。
然后,在第二绝缘层142上开孔暴露出屏蔽铜柱131的底端面和器件170的端子面171,但预定的信号线引出开口位置的树脂保留,以避免信号线与屏蔽铜柱131接触;接着,在第二绝缘层142上形成连接器件170的端子171的信号线133,使得信号线133穿过信号线引出开口位置181,如图2(l)所示。同时,也可以将其它铜柱例如导通铜柱的底端面打开并暴露,以使导通铜柱能够随着屏蔽铜柱131同步增层。
打开第二绝缘层142暴露铜柱底端面的方式通常情况下是激光钻孔,但并不局限于此。例如,当树脂材料142使用感光型树脂材料时(如PI),可以直接通过曝光显影的方式进行。
图2(l)是图2(k)的底视图,其中图2(k)是沿图2(l)的B-B'线的截面图。在信号线133的两侧通常各设置一条与其平行的屏蔽线132,这两条与信号线133平行的屏蔽线132最终接地,使得信号线133上高频信号产生的电磁感应能够被及时导入地下,避免对其它线路或周围器件产生电磁干扰。
接着,对屏蔽铜柱131从暴露的底端面向下进行增层使其延伸超出第二绝缘层142,如图2(m)所示。同时,可以对其它铜柱例如导通铜柱同时进行增层。该增层可以采用珠海越亚的无芯基板增层工艺,例如在第二绝缘层142上施加光刻胶层,对光刻胶层图案化形成开孔,暴露出屏蔽铜柱131的底端面;对开孔镀铜增层,形成增层屏蔽铜柱131;以及移除光刻胶。
然后,在屏蔽铜柱131的底端面上施加聚合物电介质形成第三绝缘层143,如图2(n)所示。
接着,进行双面减薄,减薄第一绝缘层141和第三绝缘层143暴露出屏蔽铜柱131的底端面和顶端面,如图2(o)所示。同时,也可以暴露出导通铜柱的两个端面以便于进一步增层。减薄工艺可以采用化学机械研磨或等离子气体蚀刻(plasma蚀刻)等。
最后,在第三绝缘层143和第一绝缘层141上分别形成第一线路层135和第二线路层136,使得第一线路层135和第二线路层136覆盖在屏蔽铜柱131的顶端面和底端面上并与屏蔽铜柱131电连接,如图2(p)所示。
通常,布线层采用铜或铝制成,可通过层间导通铜柱导通第一和第二线路层135、136。形成第一线路层135和第二线路层136的工艺可包括分别在第三绝缘层143的下表面和第一绝缘层141的上表面上分别溅射种子层,例如铜、钛等金属;然后施加光刻胶并图案化形成通孔或特征结构;接着在图案中电镀铜;剥除光刻胶;然后蚀刻掉暴露的种子层。
然后,还可以继续在线路层135、136上施加绝缘层和特征层来进行增层操作,形成多层互连结构,例如封装上封装等。
由此,“口”形屏蔽铜柱131与上下两层线路层135、136共同形成将器件170包围的屏蔽腔180。除信号线引出开口181外,屏蔽腔180几近将器件170密闭包封。由于信号线引出开口181的宽度(即第二绝缘层的厚度)只有信号线133宽度的2-4倍,并且信号线133的两侧还可以伴有平行的屏蔽线132,因此本发明的屏蔽腔180能够实现几乎完美的器件电磁屏蔽,使得屏蔽腔180中的器件所发出或感应到的电磁干扰最小化。
屏蔽腔180最终需要接地,以实时将在屏蔽腔180表面产生的电磁感应电流导入大地,以避免信号串扰。屏蔽线132可以通过连接屏蔽铜柱131实现接地。
图2(q)是沿图2(p)的A-A线的截面图。信号线133可以与屏蔽线132一起从信号线引出开口181引出屏蔽腔180。从器件170的端子171引出的信号线133可以通过开孔、填铜等工艺在第三绝缘层143上形成端子,以连接基板,例如PCB板。
在制程最后,可以将封装面板框架分割成单独的封装组件。分割或切割可以使用旋转锯片或其它切割技术来实现,例如激光器。
本领域技术人员将会认识到,本发明不限于上下文中具体图示和描述的内容。而且,本发明的范围由所附权利要求限定,包括上文所述的各个技术特征的组合和子组合以及其变化和改进,本领域技术人员在阅读前述说明后将会预见到这样的组合、变化和改进。
在权利要求书中,术语“包括”及其变体例如“包含”、“含有”等是指所列举的组件被包括在内,但一般不排除其他组件。

Claims (8)

1.一种具有屏蔽腔的嵌入式封装结构的制造方法,包括如下步骤:
(A)制作具有贯通空腔的框架,其中所述框架包括聚合物电介质和嵌入在所述聚合物电介质中包围所述贯通空腔的屏蔽铜柱;
(B)在所述贯通空腔中置入器件并填充封装材料形成第一绝缘层;
(C)在所述第一绝缘层的第一表面上施加聚合物电介质形成第二绝缘层;
(D)在所述第二绝缘层上开孔暴露出所述屏蔽铜柱的第一端面和所述器件的端子,同时保留预定的信号线引出开口位置的聚合物电介质;
(E)在所述第二绝缘层上形成连接所述器件的端子的信号线,在所述信号线的两侧形成屏蔽线,并且所述屏蔽线与所述信号线一起穿过所述信号线引出开口位置;
(F)将所述屏蔽铜柱从第一端面增层使其延伸超出第二绝缘层;
(G)在所述屏蔽铜柱上施加聚合物电介质形成第三绝缘层;
(H)减薄第一绝缘层和第三绝缘层暴露出所述屏蔽铜柱的第一端面和第二端面;
(I)在所述第三绝缘层和第一绝缘层上形成第一线路层和第二线路层,其中第一线路层和第二线路层覆盖在所述屏蔽铜柱的第一端面和第二端面上并与所述屏蔽铜柱电连接。
2.根据权利要求1所述的制造方法,其中步骤A还包括:
-在临时承载板上施加光刻胶层,经曝光显影形成第一图案;
-在所述第一图案中镀覆金属铜,形成屏蔽铜柱和牺牲铜柱;
-移除所述光刻胶层;
-施加聚合物电介质层以覆盖所述屏蔽铜柱和牺牲铜柱;
-减薄所述聚合物电介质层以暴露出所述屏蔽铜柱和牺牲铜柱的顶端面;
-移除所述临时承载板;
-蚀刻所述牺牲铜柱形成贯通空腔,其中所述屏蔽铜柱包围所述贯通空腔,由此得到具有贯通空腔的框架。
3.根据权利要求1所述的制造方法,其中步骤A还包括:
-在临时承载板上施加光刻胶层,经曝光显影形成第一图案;
-在所述第一图案中镀覆金属铜,形成屏蔽铜柱;
-移除所述光刻胶层;
-施加聚合物电介质层覆盖所述屏蔽铜柱;
-减薄所述聚合物电介质层以暴露出所述屏蔽铜柱的顶端面;
-移除所述临时承载板;
-对所述聚合物电介质层进行机械冲压或激光钻孔的方式形成被所述屏蔽铜柱包围的贯通空腔,由此得到具有贯通空腔的框架。
4.根据权利要求1所述的制造方法,其中步骤B包括:
-在所述框架的一面上施加胶带;
-在所述贯通空腔中置入器件并使所述器件贴装在所述胶带上;
-在所述框架的另一面上施加封装材料形成第一绝缘层,其中所述封装材料填充所述器件与框架之间的间隙;
-移除所述胶带。
5.根据权利要求1所述的制造方法,其中所述聚合物电介质选自半固化片、双马来酰亚胺/三嗪树脂、聚酰亚胺、聚氯乙烯、膜状有机树脂、环氧树脂或聚苯醚中的一种或多种的组合。
6.根据权利要求1所述的制造方法,其中步骤F还包括:
-在所述第二绝缘层上施加光刻胶层,
-对所述光刻胶层曝光显影形成开孔,暴露出所述屏蔽铜柱的第一端面;
-对所述开孔镀铜,形成增层屏蔽铜柱;
-移除所述光刻胶。
7.根据权利要求1所述的制造方法,其中步骤H还包括:
-通过机械研磨或等离子体蚀刻的方式进行减薄。
8.根据权利要求1所述的制造方法,其中步骤I还包括:
-在暴露出所述屏蔽铜柱的第一端面和第二端面的第三绝缘层和第一绝缘层上施加种子层;
-在种子层上施加光刻胶层;
-图案化形成线路图案;
-在线路图案中镀铜;
-剥除光刻胶;
-移除种子层。
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