JP4508620B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP4508620B2 JP4508620B2 JP2003411134A JP2003411134A JP4508620B2 JP 4508620 B2 JP4508620 B2 JP 4508620B2 JP 2003411134 A JP2003411134 A JP 2003411134A JP 2003411134 A JP2003411134 A JP 2003411134A JP 4508620 B2 JP4508620 B2 JP 4508620B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- wiring
- insulating layer
- wiring conductor
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structure Of Printed Boards (AREA)
Description
2cs:配線導体
11:導体層
Claims (1)
- 複数の屈曲部と該屈曲部によって形成された互いに並行な複数の並行部とを有するクランク形状の平面パターンを備え、絶縁層の表面に形成された線状の配線導体と、
前記絶縁層の表面の前記各並行部及びその延長線に挟まれた領域のみに形成された、前記配線導体と電気的に独立した複数の導体層と、
を具備してなり、
前記複数の導体層は、接地又は電源電位に接続され、前記絶縁層の表面にて互いに離間しており、前記各並行部に対して平行な細長形状であることを特徴とする配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003411134A JP4508620B2 (ja) | 2003-12-10 | 2003-12-10 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003411134A JP4508620B2 (ja) | 2003-12-10 | 2003-12-10 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005175097A JP2005175097A (ja) | 2005-06-30 |
JP4508620B2 true JP4508620B2 (ja) | 2010-07-21 |
Family
ID=34731959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003411134A Expired - Fee Related JP4508620B2 (ja) | 2003-12-10 | 2003-12-10 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4508620B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5190291B2 (ja) * | 2008-04-17 | 2013-04-24 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59191794U (ja) * | 1983-06-07 | 1984-12-19 | 株式会社 マツクエイト | プリント基板 |
JPS6379350A (ja) * | 1986-09-24 | 1988-04-09 | Hitachi Vlsi Eng Corp | 半導体装置 |
JPS6378396U (ja) * | 1986-11-12 | 1988-05-24 | ||
JP2000277928A (ja) * | 1999-03-25 | 2000-10-06 | Kyocera Corp | 多層配線基板 |
JP2003152290A (ja) * | 2001-11-13 | 2003-05-23 | Canon Inc | プリント配線基板 |
-
2003
- 2003-12-10 JP JP2003411134A patent/JP4508620B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59191794U (ja) * | 1983-06-07 | 1984-12-19 | 株式会社 マツクエイト | プリント基板 |
JPS6379350A (ja) * | 1986-09-24 | 1988-04-09 | Hitachi Vlsi Eng Corp | 半導体装置 |
JPS6378396U (ja) * | 1986-11-12 | 1988-05-24 | ||
JP2000277928A (ja) * | 1999-03-25 | 2000-10-06 | Kyocera Corp | 多層配線基板 |
JP2003152290A (ja) * | 2001-11-13 | 2003-05-23 | Canon Inc | プリント配線基板 |
Also Published As
Publication number | Publication date |
---|---|
JP2005175097A (ja) | 2005-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7613010B2 (en) | Stereoscopic electronic circuit device, and relay board and relay frame used therein | |
US8238109B2 (en) | Flex-rigid wiring board and electronic device | |
JP6626697B2 (ja) | 配線基板およびその製造方法 | |
JP2005294383A (ja) | キャパシタ実装配線基板及びその製造方法 | |
JP5729186B2 (ja) | 半導体装置及びその製造方法 | |
KR20090130727A (ko) | 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
JP5311653B2 (ja) | 配線基板 | |
JP2010109243A (ja) | 配線基板 | |
JP2013065811A (ja) | プリント回路基板及びその製造方法 | |
JP4508620B2 (ja) | 配線基板 | |
JP4235092B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP2005072503A (ja) | 配線基板およびそれを用いた電子装置 | |
JP5370883B2 (ja) | 配線基板 | |
JP4508540B2 (ja) | 配線基板および電子装置 | |
JP4349891B2 (ja) | 配線基板および電子装置 | |
JP2005159092A (ja) | 配線基板 | |
JP4360617B2 (ja) | 配線基板 | |
JP2009290044A (ja) | 配線基板 | |
JP2004327633A (ja) | 配線基板 | |
JP7128098B2 (ja) | 配線基板 | |
JP2014123592A (ja) | プリント配線板の製造方法及びプリント配線板 | |
JP5890978B2 (ja) | 配線基板の製造方法 | |
JP4227502B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP7010727B2 (ja) | 配線基板 | |
JP4439248B2 (ja) | 配線基板およびこれを用いた半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061117 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080501 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090804 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091002 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091201 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100127 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100330 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100427 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140514 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |