JP5311653B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP5311653B2 JP5311653B2 JP2009110056A JP2009110056A JP5311653B2 JP 5311653 B2 JP5311653 B2 JP 5311653B2 JP 2009110056 A JP2009110056 A JP 2009110056A JP 2009110056 A JP2009110056 A JP 2009110056A JP 5311653 B2 JP5311653 B2 JP 5311653B2
- Authority
- JP
- Japan
- Prior art keywords
- pair
- semiconductor element
- connection pads
- strip
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
1a コア基板としての絶縁層
1b,1c ビルドアップ絶縁層としての絶縁層
2 配線導体層
2a 第1の帯状配線導体のペア
2b 第2の帯状配線導体のペア
3 半導体素子接続パッド
3a 第1の半導体素子接続パッドのペア
3b 第2の半導体素子接続パッドのペア
4 外部接続パッド
4a 第1の外部接続パッドのペア
4b 第2の外部接続パッドのペア
S 半導体素子
Claims (4)
- 複数のスルーホールを有するコア基板の上下面に、複数のビアホールを有するビルドアップ絶縁層を積層して成る絶縁基板と、前記コア基板の上下面に被着された接地導体層または電源導体層と、前記絶縁基板の上面に形成されており、送信用の信号を半導体素子から出力するための第1の半導体素子接続パッドのペアおよび受信用の信号を半導体素子に入力するための第2の半導体素子接続パッドのペアを含む複数の半導体素子接続パッドと、前記絶縁基板の下面に形成されており、送信用の信号を外部電気回路に出力するための第1の外部接続パッドのペアおよび受信用の信号を外部電気回路から入力するための第2の外部接続パッドのペアを含む複数の外部接続パッドと、前記ビルドアップ絶縁層上に互いに隣接して延在するように形成されており、前記第1の半導体素子接続パッドのペアと前記第1の外部接続パッドのペアとの間を前記スルーホールおよび前記ビアホールに被着された配線導体を介して電気的に接続する第1の帯状配線導体のペアおよび前記第2の半導体素子接続パッドのペアと前記第2の外部接続パッドのペアとの間を前記スルーホールおよび前記ビアホールに被着された配線導体を介して電気的に接続する第2の帯状配線導体のペアとを具備して成る配線基板であって、前記第1の帯状配線導体のペアと前記第2の帯状配線導体のペアとが間に前記接地導体層または電源導体層を挟んで前記コア基板の上面側と下面側との互いに異なるビルドアップ絶縁層上に形成されており、かつ前記下面側の帯状配線導体の各ペアに接続する前記上面側の帯状配線導体のペアの間隔が前記上面側に配置されたビアホールから前記下面側に配置されたスルーホールに向けて拡がっていることを特徴とする配線基板。
- 前記第1の帯状配線導体のペアと前記第2の帯状配線導体のペアとの間に、互いに異なる電位に接続される接地導体層または電源導体層が2層以上介在していることを特徴とする請求項1記載の配線基板。
- 前記第1の半導体素子接続パッドのペアと前記第2の半導体素子接続パッドのペアとの間に接地用または電源用の半導体素子接続パッドが介在していることを特徴とする請求項1または2に記載の配線基板。
- 前記第1の外部接続パッドのペアと前記第2の外部接続パッドのペアとの間に接地用または電源用の外部接続パッドが介在していることを特徴とする請求項1乃至3のいずれかに記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009110056A JP5311653B2 (ja) | 2009-04-28 | 2009-04-28 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009110056A JP5311653B2 (ja) | 2009-04-28 | 2009-04-28 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010258390A JP2010258390A (ja) | 2010-11-11 |
JP5311653B2 true JP5311653B2 (ja) | 2013-10-09 |
Family
ID=43318927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009110056A Expired - Fee Related JP5311653B2 (ja) | 2009-04-28 | 2009-04-28 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5311653B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5586441B2 (ja) * | 2010-11-30 | 2014-09-10 | 京セラSlcテクノロジー株式会社 | 配線基板 |
TWI479956B (zh) * | 2010-12-09 | 2015-04-01 | Hon Hai Prec Ind Co Ltd | 具有高速差分訊號佈線結構的印刷電路板 |
JP6028297B2 (ja) * | 2012-03-06 | 2016-11-16 | 国立研究開発法人産業技術総合研究所 | 伝送線路構造、多層配線基板、半導体装置、および半導体システム |
JP5955124B2 (ja) * | 2012-06-22 | 2016-07-20 | 京セラ株式会社 | 配線基板 |
JP2014038971A (ja) * | 2012-08-18 | 2014-02-27 | Kyocer Slc Technologies Corp | 配線基板 |
US9565750B2 (en) | 2012-08-18 | 2017-02-07 | Kyocera Corporation | Wiring board for mounting a semiconductor element |
DE202014008844U1 (de) * | 2014-11-06 | 2014-11-24 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Elektrisches Interface |
JP6466722B2 (ja) * | 2015-01-26 | 2019-02-06 | 京セラ株式会社 | 配線基板 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003218480A (ja) * | 2002-01-25 | 2003-07-31 | Mitsubishi Electric Corp | プリント配線板及びその製造方法 |
JP2004253746A (ja) * | 2002-12-26 | 2004-09-09 | Kyocera Corp | 配線基板 |
JP4387231B2 (ja) * | 2004-03-31 | 2009-12-16 | 新光電気工業株式会社 | キャパシタ実装配線基板及びその製造方法 |
JP2005353835A (ja) * | 2004-06-10 | 2005-12-22 | Ngk Spark Plug Co Ltd | 配線基板 |
JP4916300B2 (ja) * | 2006-12-19 | 2012-04-11 | 新光電気工業株式会社 | 多層配線基板 |
JP4978269B2 (ja) * | 2007-03-27 | 2012-07-18 | 日本電気株式会社 | 多層配線基板 |
-
2009
- 2009-04-28 JP JP2009110056A patent/JP5311653B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010258390A (ja) | 2010-11-11 |
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