JP2005159133A - 配線基板およびこれを用いた半導体装置 - Google Patents
配線基板およびこれを用いた半導体装置 Download PDFInfo
- Publication number
- JP2005159133A JP2005159133A JP2003397309A JP2003397309A JP2005159133A JP 2005159133 A JP2005159133 A JP 2005159133A JP 2003397309 A JP2003397309 A JP 2003397309A JP 2003397309 A JP2003397309 A JP 2003397309A JP 2005159133 A JP2005159133 A JP 2005159133A
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- Prior art keywords
- layer
- conductor
- insulating
- layers
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Structure Of Printed Boards (AREA)
Abstract
【解決手段】 絶縁層1bの第1の層間に隣接して配設された接地用または電源用の第1および第2の導体層2a,2bと、絶縁層1bの第2の層間に隣接して配設された接地用または電源用の第3および第4の導体層2c,2dとは、それぞれの間の間隙G1,G2が平面視で重ならないように配設されている。
【選択図】 図2
Description
1b:絶縁層
2a:第1の導体層
2b:第2の導体層
2c:第3の導体層
2d:第4の導体層
3:半導体素子
G1:導体層2a,2b間の間隙
G2:導体層2c,2d間の間隙
Claims (2)
- 複数の絶縁層が積層されて成り、上面の中央部に半導体素子がフリップチップ接続により搭載される搭載部を有する絶縁基板と、前記絶縁層の第1の層間に隣接して配設された接地用または電源用の第1の導体層および第2の導体層と、前記絶縁層の第2の層間に隣接して配設された、前記第1の導体層に電気的に接続された第3の導体層および前記第2の導体層に電気的に接続された第4の導体層とを具備しており、前記第1乃至第4の導体層は、前記第1および第2の導体層間の間隙と前記第3および第4の導体層間の間隙とが平面視で重ならないように配設されていることを特徴とする配線基板。
- 請求項1記載の配線基板の前記搭載部に前記半導体素子がフリップチップ接続により搭載されていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003397309A JP4235092B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003397309A JP4235092B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005159133A true JP2005159133A (ja) | 2005-06-16 |
JP4235092B2 JP4235092B2 (ja) | 2009-03-04 |
Family
ID=34722495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003397309A Expired - Fee Related JP4235092B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Country Status (1)
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JP (1) | JP4235092B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009239137A (ja) * | 2008-03-28 | 2009-10-15 | Toppan Printing Co Ltd | 配線基板 |
JP2012199426A (ja) * | 2011-03-22 | 2012-10-18 | Fujitsu Semiconductor Ltd | 配線基板 |
JP2016063089A (ja) * | 2014-09-18 | 2016-04-25 | 日立オートモティブシステムズ株式会社 | 回路基板及び電子制御装置 |
JP2017212380A (ja) * | 2016-05-27 | 2017-11-30 | 京セラ株式会社 | 配線基板 |
-
2003
- 2003-11-27 JP JP2003397309A patent/JP4235092B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009239137A (ja) * | 2008-03-28 | 2009-10-15 | Toppan Printing Co Ltd | 配線基板 |
JP2012199426A (ja) * | 2011-03-22 | 2012-10-18 | Fujitsu Semiconductor Ltd | 配線基板 |
US8653381B2 (en) | 2011-03-22 | 2014-02-18 | Fujitsu Semiconductor Limited | Wiring board comprising wirings arranged with crest and trough |
JP2016063089A (ja) * | 2014-09-18 | 2016-04-25 | 日立オートモティブシステムズ株式会社 | 回路基板及び電子制御装置 |
JP2017212380A (ja) * | 2016-05-27 | 2017-11-30 | 京セラ株式会社 | 配線基板 |
Also Published As
Publication number | Publication date |
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JP4235092B2 (ja) | 2009-03-04 |
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